CN103856257A - Satellite communication gateway station signal demodulation processing board - Google Patents
Satellite communication gateway station signal demodulation processing board Download PDFInfo
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- CN103856257A CN103856257A CN201210499051.4A CN201210499051A CN103856257A CN 103856257 A CN103856257 A CN 103856257A CN 201210499051 A CN201210499051 A CN 201210499051A CN 103856257 A CN103856257 A CN 103856257A
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Abstract
The invention discloses a satellite communication gateway station signal demodulation processing board comprising an intermediate-frequency signal receiver. The intermediate-frequency signal receiver is connected with at least two A/D converters, wherein one A/D converter is directly connected with an FPGA unit, and the rest A/D converters are connected with a DDC (digital down converter). The DDC is connected with the FPGA unit, and the FPGA unit is connected with a DSP unit and a communication interface. The FPGA unit includes a numerically controlled oscillation module, the numerically controlled oscillation module is connected with a cascaded integrator comb filter module, the cascaded integrator comb filter module is connected with a half-band filter module, and the half-band filter module is connected with a channelized poly-phase filter bank module. According to the satellite communication gateway station signal demodulation processing board of the invention, the function of the DDC (digital down converter) is realized by the use of the FPGA, and simultaneous multi-channel signal processing is realized without improving the structure of the processing board as the channelized poly-phase filter bank is arranged in the FPGA unit.
Description
Technical field
The present invention relates to satellite mobile communication handshaking technical field, particularly a kind of satellite communication gateway station signal demodulation process plate.
Background technology
Satellite mobile communication be exactly between the radio communication station (comprising in ground and lower atmosphere layer) on the earth, utilize satellite as in the communication then carried out.Satellite plays relay station aloft, electromagnetic wave that earth station is put forward counter another earth station of sending back to again after amplifying.Gateway station is the link that satellite system forms, and the effect of gateway station is mainly to provide the interface of satellite mobile communication system and ground fixed communication network, land mobile communication net, realizes and interconnecting; Control satellite mobile terminal access satellite communication system, and guarantee that its signal in communication process does not interrupt.
Satellite communication gateway station signal demodulation process plate is the important component part of satellite mobile communication system, and satellite communication gateway station signal demodulation process plate carries out demodulation, processing to the intermediate-freuqncy signal of satellite launch, then output.Along with the development of satellite communication, the signal demodulation process information of gateway station improves constantly, image, voice-and-data information constantly improve, and need the image of gateway station signal demodulation process plate processing, voice-and-data information also constantly to increase, and message transmission rate improves constantly.Digital down converter (DDC), has the function such as Digital Down Convert, data pick-up, is one of important components and parts of satellite communication gateway station signal demodulation process plate.Traditional DDC digital down converter is not considered the filtering extraction of bandwidth signal, processes bandwidth and can not reach the multichannel requirement in broadband, can only, with limited combination configuration filter and withdrawal device, cause satellite communication gateway station signal demodulation process plate structure to increase.In addition, the structure of special purpose DDC chip is fixed, and bandwidth can not meet the requirement of high-speed data (as being greater than 400Mbps) demodulation.
Summary of the invention
The object of the present invention is to provide a kind of satellite communication gateway station signal demodulation process plate, this signal demodulation process plate utilizes FPGA to complete Digital Down Convert, realizes multi-channel signal processing, and does not increase disposable plates structure.
In order to realize foregoing invention object, the invention provides following technical scheme:
A kind of satellite communication gateway station signal demodulation process plate, comprise intermediate-freuqncy signal receiver, described intermediate-freuqncy signal receiver is connected with at least two A/D converters, one of them A/D converter directly connects FPGA unit, all the other A/D converters all connect DDC digital down converter, described DDC digital down converter connects FPGA unit, FPGA unit connects DSP unit and communication interface, FPGA unit comprises numerical control oscillation module, described numerical control oscillation module connects cascaded integrator-comb filtration module, described cascaded integrator-comb filtration module connects semi-band filtering module, described semi-band filtering module connecting channel multiphase filter pack module.
Described A/D converter has been used for the digital translation of analog intermediate frequency signal; Described DDC digital down converter is for filtering, signal adjustment and down-converted; Described FPGA unit will carry out format conversion, semi-band filtering, demodulation code through the digital signal of DDC digital down converter processing on the one hand, directly the digital signal after A/D converter conversion is carried out to down-converted on the other hand, then carry out filtering and demodulation; Described DSP unit is configured computing to the signal receiving, and information exchange after treatment is crossed communication interface output.
Preferably, described communication interface is VPX interface.VPX interface has more I/O port, supports transfer of data at a high speed, is applicable to the timely processing of high-speed digital signal, and disposal ability can be expanded, and external interface is replaceable, and anti-seismic performance is high.
compared with prior art, beneficial effect of the present invention: satellite communication gateway station signal demodulation process plate of the present invention, utilize FPGA to realize DDC digital down converter function, and channelizing multiphase filter group is set in FPGA unit, on the basis that does not increase disposable plates structure, realize multi channel signals and processed simultaneously.And, by forming the functional module of DDC digital down converter in configuration FPGA unit, can realize the data demodulates that transmission rate is greater than 400Mbps.
Accompanying drawing explanation:
Fig. 1 is the transmission of satellite communication system signal, process flow block diagram;
Fig. 2 is signal demodulation process plate structure block diagram of the present invention;
Fig. 3 is intermediate-freuqncy signal receiver and A/D converter catenation principle block diagram;
Fig. 4 is DDC digital down converter and FPGA unit catenation principle block diagram;
Fig. 5 is the theory diagram of realizing multi channel signals down-converted in FPGA unit;
Fig. 6 is FPGA unit and DSP unit catenation principle block diagram;
Fig. 7 is A/D converter and FPGA unit catenation principle block diagram;
Fig. 8 is FPGA unit and VPX interface catenation principle block diagram.
Embodiment
Below in conjunction with test example and embodiment, the present invention is described in further detail.But this should be interpreted as to the scope of the above-mentioned theme of the present invention only limits to following embodiment, all technology realizing based on content of the present invention all belong to scope of the present invention.
As shown in Figure 1, satellite sends signal, ground-plane antenna by this signal through downlink transmission to earth station; This small-signal receiving is transferred to low noise amplifier unit by earth station, to guarantee to receive the quality of signal; This signal through amplifying carries out frequency translation through low-converter again, signal is amplified again to the intermediate-freuqncy signal of output different frequency; This intermediate-freuqncy signal of further amplifying obtains corresponding information after demodulator signal-processing board carries out demodulation, coding, and exports this information.
With reference to figure 2, Fig. 5, the satellite communication gateway station signal demodulation process plate that the present embodiment is enumerated comprises intermediate-freuqncy signal receiver, at least two A/D converters, DDC digital down converter, FPGA unit, DSP unit, and VPX interface, wherein, described intermediate-freuqncy signal receiver connects A/D converter, one of them A/D converter is directly connected with FPGA unit, FPGA unit comprises numerical control oscillation module, described numerical control oscillation module connects cascaded integrator-comb filtration module (CIC), described cascaded integrator-comb filtration module connects semi-band filtering module (HB), described semi-band filtering module connecting channel multiphase filter pack module, remaining A/D converter connects DDC digital down converter, described DDC digital down converter connects FPGA unit, FPGA unit connects DSP unit and VPX interface.Numerical control oscillation module, cascaded integrator-comb filtration module, semi-band filtering module and channelizing multiphase filter pack module in FPGA unit are the graphical devices generating by programming.
Numerical control oscillation module in FPGA unit, cascaded integrator-comb filtration module, semi-band filtering module realize the down-converted function of traditional DDC digital down converter, in conjunction with channelizing multiphase filter pack module, can realize multi-channel signal processing.Utilize FPGA to realize and be familiar with frequency down-conversion function, reduced the use amount of DDC digital down converter, reduce costs, also reduced the structure of disposable plates simultaneously; Realize multi-channel signal processing, reduce processing cost on the one hand, also avoided on the other hand the disposable plates structure causing because of the use of channelizing multiphase filter group to increase.
The workflow of satellite communication gateway station signal demodulation process plate of the present invention is: the analog intermediate frequency signal of reception is transferred to A/D converter by intermediate-freuqncy signal receiving element, analog intermediate frequency signal is converted to digital signal by A/D converter, then the digital data transmission of portion of channel to each DDC digital down converter (is provided with multiple DDC digital down converters in disposable plates conventionally, a DDC digital down converter carries out down-converted to the digital signal of a passage), each DDC digital down converter carries out filtering to this digital signal, signal is adjusted and down-converted, then transfer to FPGA unit, FPGA unit carries out format conversion to the digital signal through down-converted, semi-band filtering, demodulation, decoding, the digital signal of another part passage directly transfers to FPGA unit: the local oscillation signal that the digital controlled oscillator from digital intermediate frequency signal and the FPGA unit of A/D converter output produces multiplies each other, this digital intermediate frequency signal is down-converted to zero intermediate frequency signals, this zero intermediate frequency signals is passed through cascade integral comb filter more successively, half-band filter and channelizing multiphase filter group, carry out filtering extraction, broadband signal is evenly divided into some sub-band signal output simultaneously, complete the down-conversion of DDC digital down converter module to intermediate-freuqncy signal, filtering, signal adjustment processing, then transfer to DSP unit.DSP unit is configured computing, digital demodulation processing to the digital signal receiving, signal after treatment is back to FPGA unit again, signal after treatment is exported by VPX interface after FPGA unit filtering, VPX interface is connected to computer and disk array, this information exchange is crossed RAID RAID card and is stored in computer disk array, facilitates researcher's research.
Each component units of satellite communication gateway station signal demodulation process plate of the present invention and each unit connection relation specifically describe as follows.
With reference to figure 3, intermediate-freuqncy signal receiving element comprises tuner, and analog intermediate frequency signal is received by tuner, then transfers to A/D converter after impedance transformation.The input clock of A/D converter can be inputted by external clock, also can be provided by common crystals or constant-temperature crystal oscillator, and in the present embodiment, the input clock of A/D converter is provided by constant-temperature crystal oscillator.A/D converter sampling clock requires quality high, and phase noise is low, if clock signal shake is larger, signal to noise ratio easily worsens, and is difficult to guarantee the precision of effective sampling resolution.For Optimal performance, the clock input of A/D converter adopts the clock input of difference low jitter, input clock is treated to LVPECL signal, by being ac-coupled to A/D converter.
A DDC digital down converter can connect 4 A/D converters, and each A/D converter takies a data channel of DDC digital down converter.The output level of A/D converter, DDC digital down converter is 3.3V, adopts direct-current coupling mode to connect.A/D converter outputs data bits width is 14, and DDC digital down converter data input bit width is 17.A/D converter is output as TWOS complement code form, and due to data bit width misalignment, so A/D converter is alignd according to highest order with the data of DDC digital down converter, the unnecessary low level of DDC digital down converter is drop-down.
Can connect 4 DDC digital down converters with reference to 4, one FPGA unit of figure.The interconnection of DDC digital down converter and FPGA unit comprises input control interconnection, output signal interconnection, the control signal interconnection of DDC digital down converter.
DDC digital down converter comprises that four input enable pin and FPGA unit carry out input control interconnection, and every DDC digital down converter takies 4 3.3V I/O pins of FPGA unit altogether.
In the present embodiment, the output data channel divided data of DDC digital down converter enables, frame synchronization enables, output enable three classes.The output signal of DDC digital down converter also provides a road VGA/ decay to control output channel and two output clock pins, and the signal that DDC digital down converter is connected on FPGA unit comprises A, B, C, tetra-output data channel of D and two output clock pins.
The control signal interconnection of DDC digital down converter and FPGA unit comprises hardware controls and Microprocessor Interface control two classes.Hardware controls has synchronous input, synchronous output, the three kinds of signals that reset, and takies altogether 4 3.3V I/O pins of FPGA unit.Microprocessor Interface control takies 23 3.3V I/O pins of FPGA unit altogether.
With reference to figure 6, the data channel of FPGA unit and DSP unit interconnects in the mode of direct-current coupling by the EMIFA of DSP.DSP unit controls and status signal have reset (RESET) signal, non-maskable interrupts (NMI) signal, reset mode output (RESETSTAT) signal, electrification reset (POR) signal, GPIO[3:0] signal, TIMER1 signal, TIMER2 signal, IIC signal.The AECLKIN signal pins of DSP unit and AECLKOUT signal pins are connected to the clock pin of FPGA unit.
The two-way McBSP of DSP unit is with form and the FPGA cell interconnection of multi-channel synchronous serial ports.
With reference to figure 7, the interconnection between A/D converter and FPGA unit need to be passed backboard connector, and the control between A/D converter and FPGA unit is connected by OVR and two pins of RDY with condition line.
With reference to figure 8, VPX interface completes communicating by letter of FPGA unit and host computer, and local bus is transformed in VPX bus fast.Between FPGA and VPX bus interface by 3.3V LVTTL(Low Voltage Transistor-Transistor Logic) be connected, FPGA and VPX have 8 single-ended LVTTL pin direct interconnection, also have two single-ended LVTTL pins and serial ports control chip MAX3232 interconnection to realize two-way serial ports and are connected to VPX.
Claims (3)
1. a satellite communication gateway station signal demodulation process plate, comprise intermediate-freuqncy signal receiver, described intermediate-freuqncy signal receiver is connected with at least two A/D converters, it is characterized in that, one of them A/D converter directly connects FPGA unit, all the other A/D converters all connect DDC digital down converter, described DDC digital down converter connects FPGA unit, FPGA unit connects DSP unit and communication interface, FPGA unit comprises numerical control oscillation module, described numerical control oscillation module connects cascaded integrator-comb filtration module, described cascaded integrator-comb filtration module connects semi-band filtering module, described semi-band filtering module connecting channel multiphase filter pack module.
2. the satellite communication gateway station signal demodulation process plate based on PCI-E interface according to claim 1, is characterized in that, described A/D converter completes the digital translation of analog intermediate frequency signal; Described DDC digital down converter is for filtering, signal adjustment and down-converted; Described FPGA unit will carry out format conversion, semi-band filtering, demodulation code through the digital signal of DDC digital down converter processing on the one hand, directly the digital signal after A/D converter conversion is carried out to down-converted on the other hand, then carry out filtering and demodulation; Described DSP unit is configured computing to the signal receiving, and information exchange after treatment is crossed communication interface output.
3. the satellite communication gateway station signal demodulation process plate based on PCI-E interface according to claim 1 and 2, is characterized in that, described communication interface is VPX interface.
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| CN201210499051.4A CN103856257A (en) | 2012-11-29 | 2012-11-29 | Satellite communication gateway station signal demodulation processing board |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2530289A (en) * | 2014-09-17 | 2016-03-23 | Trl Technology Ltd | Low-complexity channelisation scheme catering for signals of arbitrary centre frequency and bandwidth |
| CN107919903A (en) * | 2017-11-21 | 2018-04-17 | 中国电子科技集团公司第五十四研究所 | A kind of multi-mode satellite communication apparatus based on VPX frameworks |
| CN111416654A (en) * | 2020-03-16 | 2020-07-14 | 北京邮电大学 | Satellite virtualization gateway station transmission architecture based on hardware acceleration |
| CN112564763A (en) * | 2020-11-23 | 2021-03-26 | 中国人民解放军国防科技大学 | Universal digital satellite load hardware platform |
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| CN202043074U (en) * | 2011-04-06 | 2011-11-16 | 天津光电通信技术有限公司 | Configurable digital downconverter |
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| US20060274857A1 (en) * | 2005-06-02 | 2006-12-07 | Chiu Lihu M | RFID receiver with digital down conversion |
| CN202043074U (en) * | 2011-04-06 | 2011-11-16 | 天津光电通信技术有限公司 | Configurable digital downconverter |
| CN102694557A (en) * | 2012-06-12 | 2012-09-26 | 成都林海电子有限责任公司 | Multi-channel demodulation signal processing platform based on CPCI (compact programmable communication interface) |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2530289A (en) * | 2014-09-17 | 2016-03-23 | Trl Technology Ltd | Low-complexity channelisation scheme catering for signals of arbitrary centre frequency and bandwidth |
| GB2530289B (en) * | 2014-09-17 | 2017-03-15 | Trl Tech Ltd | Low-complexity channelisation scheme catering for signals of arbitrary centre frequency and bandwidth |
| CN107919903A (en) * | 2017-11-21 | 2018-04-17 | 中国电子科技集团公司第五十四研究所 | A kind of multi-mode satellite communication apparatus based on VPX frameworks |
| CN111416654A (en) * | 2020-03-16 | 2020-07-14 | 北京邮电大学 | Satellite virtualization gateway station transmission architecture based on hardware acceleration |
| CN112564763A (en) * | 2020-11-23 | 2021-03-26 | 中国人民解放军国防科技大学 | Universal digital satellite load hardware platform |
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