CN114897171B - Superconducting quantum bit low-delay feedback control circuit and superconducting quantum feedback control method - Google Patents
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Abstract
The application relates to a superconducting qubit low-delay feedback control circuit, comprising: the device comprises an analysis module and a feedback driving module; the analysis module is configured to read the radio frequency signal released by the superconducting quantum chip, process the radio frequency signal to obtain state feedback data, and output the state feedback data to the feedback driving module; the feedback driving module is configured to receive the state feedback data and output the state feedback data to the control unit; the system also comprises a feedback equalization module and a control module which are connected in sequence; the feedback equalization module is configured to receive the state feedback data, perform equalization processing on the state feedback data and output the state feedback data to the control module; the control module is configured to receive the state feedback data after the equalization processing, select needed feedback data from the received state feedback data, and output the selected feedback data to the superconducting quantum chip; the analysis module and the control module are realized through the FPGA chip, so that the expansibility of the system is effectively improved.
Description
Technical Field
The disclosure relates to the technical field of superconducting quantum computing, in particular to a superconducting quantum bit low-delay feedback control circuit and a superconducting quantum feedback control method.
Background
Along with the promotion of the preparation of superconducting quantum computing chips, control algorithms and other aspects, the realization of more quantum bits is a primary target faced in the current stage engineering. With the increase of superconducting quantum computing qubits, the system scale is rapidly expanded, and a low-delay feedback control circuit scheme is needed to provide necessary hardware foundation for realizing more complex qubit operation in a shorter time. In the related art, in the field of superconducting quantum computing, for an occasion requiring low-delay feedback control, a back plate in a chassis is generally used to transmit a feedback signal. However, when the feedback signal is transmitted by adopting the back plate in the chassis, the topological structure of the back plate is fixed, and the back plate cannot be changed after the design is finished, so that the system is not beneficial to reconstruction, and the expansibility and the topological flexibility of the system are limited to a certain extent.
Disclosure of Invention
In view of this, the present disclosure proposes a superconducting qubit low-delay feedback control circuit, which can effectively improve the expansibility and flexibility of the system.
According to an aspect of the present disclosure, there is provided a superconducting qubit low-delay feedback control circuit including:
a reading unit and a control unit;
the reading unit comprises an analysis module and a feedback driving module which are sequentially connected;
the analysis module is configured to read the radio frequency signal released by the superconducting quantum chip, process the radio frequency signal to obtain state feedback data, and output the state feedback data to the feedback driving module;
the feedback driving module is configured to receive the state feedback data and output the state feedback data to the control unit;
the control unit comprises a feedback equalization module and a control module which are sequentially connected;
the feedback equalization module is configured to receive the state feedback data, perform equalization processing on the state feedback data and output the state feedback data to the control module;
the control module is configured to receive the state feedback data after the equalization processing, select needed feedback data from the received state feedback data, and output the selected feedback data to the superconducting quantum chip;
the analysis module and the control module are realized through an FPGA chip.
In one possible implementation, the feedback driving module and the feedback equalizing module are electrically connected through a signal line.
In one possible implementation manner, the system further comprises a signal sampling module and a signal output module;
the signal sampling module is electrically connected between the superconducting quantum chip and the analysis module and is configured to collect radio frequency signals released by the superconducting quantum chip and send the radio frequency signals to the analysis module;
the signal output module is electrically connected between the control module and the superconducting quantum chip, and is configured to receive feedback data output by the control module and input the feedback data to the superconducting quantum chip.
In one possible implementation manner, the filter further comprises a first filtering module and a second filtering module;
the first filtering module is suitable for being electrically connected between the superconducting quantum chip and the analysis module and is used for filtering the radio frequency signal released by the superconducting quantum chip;
the second filtering module is suitable for being electrically connected between the control module and the superconducting quantum chip and used for filtering the output feedback data and then inputting the feedback data into the superconducting quantum chip.
In one possible implementation, the parsing module includes a qubit state acquisition sub-module, a qubit matching sub-module, and a first conversion sub-module;
the qubit state acquisition submodule is configured to perform operation processing on the radio frequency signal to obtain a qubit state of the superconducting quantum chip;
the qubit matching module is configured to match the qubit state with ID information of a preset target control device, and obtain corresponding state feedback data according to a matching result;
the first conversion sub-module is configured to convert the state feedback data from a parallel signal to a serial signal and then output the state feedback data converted to a serial signal format to the feedback driving module.
In one possible implementation, the feedback driving module includes a feedback driving sub-module and a first ID conversion sub-module;
the input end of the first ID conversion sub-module is electrically connected with the feedback equalization module and is configured to acquire ID information of the control equipment by the feedback equalization module;
the output end of the first ID conversion sub-module is electrically connected with the analysis module and is configured to send the acquired ID information of the control equipment to the analysis module;
the input end of the feedback driving sub-module is electrically connected with the analysis module and is configured to receive state feedback data output by the analysis module;
the output end of the feedback driving sub-module is electrically connected with the feedback equalization module and is configured to output the received state feedback data to the feedback equalization module.
In one possible implementation manner, the control module includes a second conversion sub-module and a data selection sub-module;
the second conversion sub-module is configured to convert the state feedback data output by the feedback equalization module into a parallel signal format from a serial signal format to obtain state feedback data in a parallel format;
the data selecting sub-module is configured to select feedback data currently needed from the parallel state feedback data according to the ID information of the control equipment.
In one possible implementation, the feedback equalization module includes a feedback equalization sub-module and a second ID conversion sub-module;
the input end of the second ID conversion sub-module is electrically connected with the control module and is configured to acquire the ID information of preset control equipment through the control module;
the output end of the second ID conversion sub-module is electrically connected with the feedback driving module and is configured to transmit the acquired ID information of the control equipment to the feedback driving module;
the input end of the feedback equalization sub-module is electrically connected with the feedback driving module and is configured to receive state feedback data output by the feedback driving module;
the output end of the feedback equalization sub-module is electrically connected with the control module and is configured to perform equalization on the received state feedback data and then transmit the state feedback data to the control module.
According to another aspect of the present application, there is also provided a superconducting qubit low-delay feedback control method, based on any one of the above superconducting qubit low-delay feedback control circuits, including:
reading a radio frequency signal released by the superconducting quantum chip, and processing the radio frequency signal to obtain state feedback data;
receiving the state feedback data and carrying out equalization processing on the state feedback data;
and selecting needed feedback data from the state feedback data after the equalization processing, and outputting the selected feedback data to the superconducting quantum chip.
In one possible implementation manner, when the radio frequency signal is processed to obtain state feedback data, the method includes:
performing operation processing on the radio frequency signals to obtain the quantum bit state of the superconducting quantum chip;
and matching the quantum bit state with ID information of preset target control equipment, and obtaining corresponding state feedback data according to a matching result.
According to the control circuit, the analysis module and the control module are respectively realized by adopting the FPGA chip, so that the transmission processing circuit of the radio frequency signals released by the superconducting quantum chip in the control circuit is realized by the FPGA chip, and the transmission of the feedback data after transmission processing is also realized by the FPGA chip. Meanwhile, the control circuit of the embodiment of the application realizes the transmission processing of the feedback signal through the FPGA chip, the control circuit can be directly installed in the cabinet, and the reading unit and the control unit only need to be in communication connection through the signal wire.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 illustrates a schematic block diagram of a superconducting qubit low-delay feedback control circuit of an embodiment of the present disclosure;
fig. 2 shows a flow chart of a superconducting qubit low-delay feedback control method of an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
Fig. 1 illustrates a functional block diagram of a superconducting qubit low-delay feedback control circuit 100 according to an embodiment of the present disclosure. As shown in fig. 1, the control circuit 100 includes: a reading unit 110 and a control unit 120. Wherein both the reading unit 110 and the control unit 120 are adapted to be arranged in a cabinet of the control device. Specifically, the reading unit 110 includes an parsing module 111 and a feedback driving module 112 that are sequentially connected. The analysis module 111 is configured to read the radio frequency signal released by the superconducting quantum chip 200, process the radio frequency signal to obtain state feedback data, and output the state feedback data to the feedback driving module 112. The feedback driving module 112 is configured to receive the status feedback data and output the status feedback data to the control unit 120. Here, it is understood by those skilled in the art that the radio frequency signal released by the superconducting quantum chip 200 read by the parsing module 111 is a released signal generated by the superconducting quantum chip 200 under the driving of the received control signal. Meanwhile, the state feedback data obtained by the analysis module 111 after the read radio frequency signal is analyzed is data capable of representing the current operation state of the superconducting quantum chip 200, and the data is transmitted in a signal mode.
The control unit 120 includes a feedback equalization module 121 and a control module 122 sequentially connected. The feedback equalization module 121 is configured to receive the status feedback data, perform equalization processing on the status feedback data, and output the status feedback data to the control module 122. The control module 122 is configured to receive the state feedback data after the equalization processing, select the needed feedback data from the received state feedback data, and output the selected feedback data to the superconducting quantum chip 200 as a radio frequency signal for controlling the superconducting quantum chip 200.
In the control circuit 100 of the embodiment of the present application, the parsing module 111 and the control module 122 are implemented by FPGA chips.
Therefore, the control circuit 100 in the embodiment of the present application implements the parsing module 111 and the control module 122 by using FPGA chips, so that the transmission processing circuit of the radio frequency signal released by the superconducting quantum chip 200 in the control circuit 100 is implemented by using FPGA chips, and the transmission of the feedback data after the transmission processing is also implemented by using FPGA chips, thereby implementing the feedback data transmission circuit by FPGA, and providing a scheme of selecting and transmitting delay lower than 200ns from reading parsing to control waveform for the whole superconducting quantum bit reading and controlling operation.
Meanwhile, in the control circuit 100 of the embodiment of the application, the transmission processing of the feedback signal is realized through the FPGA chip, the control circuit 100 can be directly installed in the cabinet, and the reading unit 110 and the control unit 120 only need to be in communication connection through the signal line, so that the flexibility of the topology structure of the device is effectively improved compared with the mode of transmitting the feedback signal through the back plate in the cabinet.
It should be noted that, referring to fig. 1, the control circuit 100 of the embodiment of the present application further includes a signal sampling module 113 and a signal output module 123. The signal sampling module 113 is electrically connected between the superconducting quantum chip 200 and the parsing module 111, and is configured to collect radio frequency signals released by the superconducting quantum chip 200 and send the radio frequency signals to the parsing module 111. The signal output module 123 is electrically connected between the control module 122 and the superconducting quantum chip 200, and is configured to receive feedback data output by the control module 122 and input the feedback data to the superconducting quantum chip 200.
Here, it should be noted that the signal sampling module 113 and the signal output module 123 may be implemented using an ADC chip and a DAC chip, respectively.
Still further, in the control circuit 100 of the embodiment of the present application, a first filtering module 114 and a second filtering module 124 may also be included. The first filtering module 114 is adapted to be electrically connected between the superconducting quantum chip 200 and the parsing module 111, and is used for filtering the radio frequency signal released by the superconducting quantum chip 200. The second filtering module 124 is adapted to be electrically connected between the control module 122 and the superconducting quantum chip 200, and is used for filtering the output feedback data and inputting the filtered feedback data to the superconducting quantum chip 200.
In one possible implementation, both the first filtering module 114 and the second filtering module 124 may be implemented with bandpass filters. Meanwhile, it should also be noted that, in the control circuit 100 of the embodiment of the present application, the connection among the first filtering module 114, the signal acquisition module, the parsing module 111 and the feedback driving module 112 in the reading unit 110 may be implemented through a communication interface.
Correspondingly, the communication connection among the feedback equalization module 121, the control module 122, the signal output module 123 and the second filtering module 124 in the control unit 120 is also implemented by adopting a communication interface.
Here, it should be noted that the reading unit 110 and the control unit 120 may be installed between different cabinets, respectively, and the closed loop of the feedback circuit is completed through the data transfer between the reading unit 110 and the control unit 120.
The feedback may be implemented by using standard communication interfaces such as a standard computer network UDP, TCP/IP, wireless signals, PCIE, etc., or by designing a special hardware circuit to implement feedback data transfer between the control unit 120 and the reading unit 110. Here, it should also be noted that the indicators of the feedback circuit include data loans, transmission delays, and bit error rates.
Further, in the control circuit 100 of the embodiment of the present application, for the parsing module 111 implemented in the reading unit 110 by using an FPGA chip, the qubit state obtaining sub-module, the qubit matching sub-module, and the first converting sub-module may be specifically included.
The qubit state obtaining submodule is configured to perform operation processing on the radio frequency signal to obtain a qubit state of the superconducting quantum chip 200. The quantum bit matching module is configured to match the quantum bit state with ID information of preset target control equipment, and obtain corresponding state feedback data according to a matching result. The first conversion sub-module is configured to convert the status feedback data from a parallel signal to a serial signal, and then output the status feedback data converted to a serial signal format to the feedback driving module 112.
That is, the signal sampling module 113 (high-speed ADC chip) directly collects the microwave signal output by the superconducting quantum chip 200 by using radio frequency, and the quantum bit sample microwave signal is affected by the design and process of the sample of the superconducting quantum chip 200, which is generally between 3GHz and 7 GHz. The radio frequency signal passband of the ADC chip and the front-end circuit is up to 8GHz, the sampling rate of 4Gsps to 6Gsps is set, the microwave signal (amplified and filtered) output by the superconducting quantum chip 200 is directly sampled, and the sampled microwave signal is sent to the FPGA parsing module 111.
The FPGA parsing module 111 receives the sampled data of the ADC chip, and first performs an operation process on the radio frequency signal by the qubit state obtaining submodule, to obtain a qubit state of the superconducting quantum chip 200. Here, it should be noted that, when the qubit state obtaining submodule performs operation processing on the radio frequency signal, the qubit state obtaining submodule mainly includes internal lock-in amplification operation, average operation, complex plane rotation operation and decision operation, and obtains a certain qubit state.
In general, a qubit chip has a plurality of qubits, and different qubits have different eigenfrequencies. Therefore, for the qubit state acquisition submodule, multiple paths of qubit state acquisition submodules can be configured in the analysis module 111, and multiple qubit state reading operations can be completed in parallel and in real time by the multiple paths of qubit state acquisition submodules.
And then, matching the quantum bit state with ID information of a preset target control device by a quantum bit matching module, and obtaining corresponding state feedback data according to a matching result. That is, after the reading of the plurality of qubit states is completed through the multi-path qubit state acquisition submodule, the plurality of qubit states are matched and packed according to the ID information of the target control device set by the system (that is, the qubit controlled by the control device is matched with the ID information, and the corresponding state feedback data is packed according to the corresponding qubit).
Then, the first converting sub-module converts the packed status feedback data from parallel signals to serial signals, and then outputs the status feedback data converted to serial signal format to the feedback driving module 112. In the control circuit 100 according to the embodiment of the present application, when the state feedback data is converted from parallel to serial, the state feedback data is generally converted from 32bit@156.25MHz parallel data to 4bit@1.25Gbps high-speed serial data, and then is output to the feedback driving module 112 through the high-speed differential signal of the FPGA.
In the control circuit 100 of the embodiment of the present application, referring to fig. 1, the feedback driving module 112 further includes a feedback driving sub-module (which may be implemented by a feedback driving chip) and a first ID conversion sub-module (which may be implemented by an ID data level conversion chip).
Specifically, as shown in fig. 1, the input end of the first ID conversion sub-module is electrically connected to the feedback equalization module 121, and is configured to obtain, by the feedback equalization module 121, an ID signal of the control device. The output end of the first ID conversion sub-module is electrically connected to the parsing module 111, and is configured to send the acquired ID signal of the control device to the parsing module 111. The input end of the feedback driving sub-module is electrically connected with the analysis module 111 and configured to receive the state feedback data output by the analysis module 111. Meanwhile, the output end of the feedback driving sub-module is electrically connected with the feedback equalization module 121 and configured to output the received state feedback data to the feedback equalization module 121.
More specifically, in one possible implementation, the feedback driving module 112 may be implemented using a chip such as DS25BR 440. The cost performance of the chip of the model is higher, and a single chip can directly provide 4-channel differential signal driving. When the feedback driving module 112 is implemented by using the chip with the above model, the selection rate is more than 2Gbps, and the pre-emphasis depth level is adjustable. The feedback data signals after driving are transmitted in parallel through a high-speed commercial connector such as HDMI, displayPort. The reading device is generally provided with at least one feedback data output interface, and in the control circuit 100 of the embodiment of the present application, the reading device is configured with 8 feedback data output interfaces, so that 8 control devices can be connected simultaneously.
Further, the reading unit 110 and the control unit 120 may be connected by using a high-speed commercial signal line such as HDMI, displayPort, which is commonly used in industry, and the length of the signal line may be selected according to the distance between the cabinet loaded by the reading unit 110 and the cabinet loaded by the control unit 120. In general, the length of the signal line may vary from several tens of centimeters to several meters, such as: 1-10 m. Here, the length of the signal line is not particularly limited.
After receiving the status feedback data sent by the feedback driving module 112 in the reading unit 110, the control unit 120 may perform corresponding processing on the received status feedback data to obtain a corresponding control signal. When the control unit 120 processes the received state feedback data, the feedback equalization module 121 first receives the state feedback data, and equalizes the state feedback data and outputs the state feedback data to the control module 122. And then the control module 122 receives the state feedback data after the equalization processing, selects the needed feedback data from the received state feedback data, and outputs the selected feedback data to the superconducting quantum chip 200.
Referring to fig. 1, when receiving the status feedback data sent from the reading unit 110, the control unit 120 may also receive the status feedback data through a high-speed commercial connector such as HDMI, displayPort. After receiving the status feedback data from the high-speed commercial connector, the feedback equalization module 121 performs equalization processing on the status feedback data, and the control module 122 selects the needed feedback data from the equalized status feedback data.
Here, it should be noted that, after the status feedback data is received through the high-speed commercial connector, the status feedback data is 4bit@1.25Gbps high-speed serial data at this time, and the signal has become worse due to the long-distance transmission quality, so that it is necessary to perform equalization processing on the received status feedback data to improve or restore the quality of the status feedback data received at the end of the control unit 120.
In one possible implementation, when the received state feedback book is equalized, the feedback equalization module 121 may be implemented in the following manner.
As shown in fig. 1, the feedback equalization module 121 includes a feedback equalization sub-module and a second ID conversion sub-module. The input end of the second ID conversion sub-module is electrically connected to the control module 122, and is configured to obtain ID information of a preset control device through the control module 122. The output end of the second ID conversion sub-module is electrically connected to the feedback driving module 112 and configured to transmit the acquired ID information of the control device to the feedback driving module 112. The input end of the feedback equalization sub-module is electrically connected to the feedback driving module 112 and configured to receive the status feedback data output by the feedback driving module 112. The output end of the feedback equalization sub-module is electrically connected with the control module 122, and is configured to perform equalization on the received state feedback data and then transmit the state feedback data to the control module 122.
It should be noted that, in the above possible implementation manner, referring to fig. 1, the feedback equalization submodule may also be implemented by using a feedback data driving chip with a model number of DS25BR 440. The state feedback data is reasonably equalized by the chip, and the high-speed serial feedback data with recovered signal quality is output to the control module 122. The second ID conversion sub-module may also be implemented using an ID data level conversion chip, and the type and model of the chip used to implement the second ID conversion sub-module are not specifically limited in this application.
After the feedback equalization sub-module (i.e., the feedback data driving chip) equalizes the state feedback data, the control module 122 (i.e., the FPGA chip) of the control device outputs high-speed serial feedback data with recovered signal quality, and the control module 122 converts the 4bit@1.25Gbps high-speed serial data into 32bit@156.25MHz parallel data with low delay through digital logic, and selects the required feedback data according to the DAC channel, the control device ID information, and the like. The selected feedback data is provided to the DAC chip (the signal output module 123) for output to complete the control feedback by a preset control waveform mapping scheme.
That is, the second conversion sub-module and the data selection sub-module are provided in the control module 122. The second conversion sub-module is configured to convert the state feedback data output by the feedback equalization module 121 into a serial signal format to a parallel signal format (i.e., convert the high-speed serial feedback data into parallel data with low delay through digital logic), so as to obtain the state feedback data in the parallel format. And the data selection sub-module is configured to select feedback data currently required from the parallel state feedback data according to the ID information of the control equipment.
Therefore, the control circuit 100 in this embodiment of the present application automatically selects necessary feedback data for packaging the status feedback data received by the control unit 120 according to the ID information of the control device, so as to avoid the phenomenon that all feedback data are broadcast and sent indifferently, and waste the effective bandwidth. Meanwhile, a level conversion chip is adopted for signal isolation for ID signal transmission, and the function of protecting the control module 122FPGA chip is also achieved. In the method, the data bandwidth can select the FPGA working clock which is the same as the quantum bit reading operation and the control waveform selecting playback operation, so that the feedback data can be updated only by a single operation period, and the processing delay is reduced to the greatest extent.
Meanwhile, in the control circuit 100 of the embodiment of the present application, the state feedback data partially received by the control unit 120 is further processed by converting parallel to high-speed serial in the FPGA and provides a received data training function on the feedback data receiving module (i.e., the feedback equalization sub-module) of the control device, so that the error rate is greatly reduced.
In summary, the control circuit 100 of the embodiment of the present application uses a digital signal driving chip, a receiving chip with pre-emphasis and equalization functions, a signal line connector with 4 pairs of differential signals and a plurality of single-ended signals such as HDMI, displayPort, and a high-speed signal line with HDMI, displayPort to realize high-speed, low-error rate and flexible feedback data transmission on a hardware architecture, thereby providing a new control circuit 100 for low-delay feedback of superconducting qubit manipulation.
Meanwhile, in the control circuit 100 of the embodiment of the present application, for the transmission of the feedback signal, the reading unit 110 and the control unit 120 are configured with corresponding ID information, and the reading unit 110 combines the ID information input after the feedback signal line is inserted with the digital logic in the FPGA chip analysis module 111, so that only the necessary feedback data matched with the ID information can be sent to the corresponding control device, thereby avoiding broadcasting all the qubit state feedback data to all the control devices, and effectively improving the bandwidth utilization rate, further reducing the delay, and improving the overall performance.
In addition, by using the control circuit 100 of the embodiment of the present application, the DAC and ADC working rates used in the superconducting qubit operation are variable, and in different application scenarios, the control device needs to set different working rates, and the superconducting qubit state reading and the touchdown operation need to be performed under the driving of the parallel clocks of the ADC collecting the original data, so that the generated feedback data rate will vary with the ADC sampling rate. Correspondingly, the DAC output qubit control waveform operating rate needs to be linked with the ADC acquisition rate, which also requires that the input feedback data rate be matched.
Meanwhile, the transmission of the training data may be automatically started after the feedback signal line (i.e., the signal line for connecting the reading unit 110 and the control unit 120) detected by the reading unit 110 is accessed and the identification of the control device ID information is accurate. The control device feeds back the data receiving unit (i.e. the control unit 120) to adjust the high-speed differential signal receiving delay and perform data verification, so as to ensure that the data is continuously and stably received correctly, and then enters the normal working mode through the feedback signal transmitting module (i.e. the reading unit 110). By training the reading unit 110, the feedback data transmission error rate can at least ensure that the error rate is 10e-15 under the working condition of 5Gbps total bandwidth.
Correspondingly, based on the control circuit, the application also provides a superconducting qubit low-delay feedback control method. The superconducting qubit low-delay feedback control method is realized by adopting any one of the superconducting qubit low-delay feedback control circuits, and the principle of the control method is the same as or similar to the working principle of any one of the control circuits, so that repeated parts are not repeated.
Referring to fig. 2, the superconducting qubit low-delay feedback control method provided in the embodiment of the present application includes: and step S100, reading radio frequency signals released by the superconducting quantum chip, and processing the radio frequency signals to obtain state feedback data. Here, it is understood by those skilled in the art that the radio frequency signal released by the superconducting quantum chip is a microwave signal released under the driving of a feedback signal transmitted from the control device to the superconducting quantum chip. Step S200, receiving the state feedback data and carrying out equalization processing on the state feedback data. And step S300, selecting needed feedback data from the state feedback data after the equalization processing, and outputting the selected feedback data to the superconducting quantum chip.
In one possible implementation manner, step S200, when processing the radio frequency signal to obtain the state feedback data, includes: step S210, performing operation processing on the radio frequency signals to obtain the quantum bit state of the superconducting quantum chip. Step S220, matching the quantum bit state with the ID information of the preset target control equipment, and obtaining corresponding state feedback data according to the matching result.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (9)
1. A superconducting qubit low-delay feedback control circuit, comprising:
a reading unit and a control unit;
the reading unit comprises an analysis module and a feedback driving module which are sequentially connected;
the analysis module is configured to read the radio frequency signal released by the superconducting quantum chip, process the radio frequency signal to obtain state feedback data, and output the state feedback data to the feedback driving module;
the feedback driving module is configured to receive the state feedback data and output the state feedback data to the control unit;
the control unit comprises a feedback equalization module and a control module which are sequentially connected;
the feedback equalization module is configured to receive the state feedback data, perform equalization processing on the state feedback data and output the state feedback data to the control module;
the control module is configured to receive the state feedback data after the equalization processing, select needed feedback data from the received state feedback data, and output the selected feedback data to the superconducting quantum chip;
wherein, the analysis module and the control module are realized by FPGA chips;
the feedback driving module comprises a feedback driving sub-module and a first ID conversion sub-module;
the input end of the first ID conversion sub-module is electrically connected with the feedback equalization module and is configured to acquire ID information of the control equipment by the feedback equalization module;
the output end of the first ID conversion sub-module is electrically connected with the analysis module and is configured to send the acquired ID information of the control equipment to the analysis module;
the input end of the feedback driving sub-module is electrically connected with the analysis module and is configured to receive state feedback data output by the analysis module;
the output end of the feedback driving sub-module is electrically connected with the feedback equalization module and is configured to output the received state feedback data to the feedback equalization module.
2. The control circuit of claim 1, wherein the feedback drive module is electrically connected to the feedback equalization module by a signal line.
3. The control circuit of claim 1, further comprising a signal sampling module and a signal output module;
the signal sampling module is electrically connected between the superconducting quantum chip and the analysis module and is configured to collect radio frequency signals released by the superconducting quantum chip and send the radio frequency signals to the analysis module;
the signal output module is electrically connected between the control module and the superconducting quantum chip, and is configured to receive feedback data output by the control module and input the feedback data to the superconducting quantum chip.
4. The control circuit of claim 1, further comprising a first filter module and a second filter module;
the first filtering module is suitable for being electrically connected between the superconducting quantum chip and the analysis module and is used for filtering the radio frequency signal released by the superconducting quantum chip;
the second filtering module is suitable for being electrically connected between the control module and the superconducting quantum chip and used for filtering the output feedback data and then inputting the feedback data into the superconducting quantum chip.
5. The control circuit of any one of claims 1 to 4, wherein the parsing module comprises a qubit state acquisition sub-module, a qubit matching sub-module, and a first conversion sub-module;
the qubit state acquisition submodule is configured to perform operation processing on the radio frequency signal to obtain a qubit state of the superconducting quantum chip;
the qubit matching sub-module is configured to match the qubit state with ID information of a preset target control device, and obtain corresponding state feedback data according to a matching result;
the first conversion sub-module is configured to convert the state feedback data from a parallel signal to a serial signal and then output the state feedback data converted to a serial signal format to the feedback driving module.
6. The control circuit of claim 5, wherein the control module comprises a second conversion sub-module and a data selection sub-module;
the second conversion sub-module is configured to convert the state feedback data output by the feedback equalization module into a parallel signal format from a serial signal format to obtain state feedback data in a parallel format;
the data selecting sub-module is configured to select feedback data currently needed from the parallel state feedback data according to the ID information of the control equipment.
7. The control circuit of claim 6, wherein the feedback equalization module comprises a feedback equalization sub-module and a second ID conversion sub-module;
the input end of the second ID conversion sub-module is electrically connected with the control module and is configured to acquire the ID information of preset control equipment through the control module;
the output end of the second ID conversion sub-module is electrically connected with the feedback driving module and is configured to transmit the acquired ID information of the control equipment to the feedback driving module;
the input end of the feedback equalization sub-module is electrically connected with the feedback driving module and is configured to receive state feedback data output by the feedback driving module;
the output end of the feedback equalization sub-module is electrically connected with the control module and is configured to perform equalization on the received state feedback data and then transmit the state feedback data to the control module.
8. A superconducting qubit low-delay feedback control method, characterized by being performed based on the superconducting qubit low-delay feedback control circuit according to any one of claims 1 to 7, comprising:
reading a radio frequency signal released by the superconducting quantum chip, and processing the radio frequency signal to obtain state feedback data;
receiving the state feedback data and carrying out equalization processing on the state feedback data;
and selecting needed feedback data from the state feedback data after the equalization processing, and outputting the selected feedback data to the superconducting quantum chip.
9. The control method according to claim 8, wherein when the radio frequency signal is processed to obtain the status feedback data, the method comprises:
performing operation processing on the radio frequency signals to obtain the quantum bit state of the superconducting quantum chip;
and matching the quantum bit state with ID information of preset target control equipment, and obtaining corresponding state feedback data according to a matching result.
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