CN106533533A - Signal demodulation processing plate for satellite communication gateway station - Google Patents
Signal demodulation processing plate for satellite communication gateway station Download PDFInfo
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- CN106533533A CN106533533A CN201610899599.6A CN201610899599A CN106533533A CN 106533533 A CN106533533 A CN 106533533A CN 201610899599 A CN201610899599 A CN 201610899599A CN 106533533 A CN106533533 A CN 106533533A
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- fpga unit
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- ddc
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/1853—Satellite systems for providing telephony service to a mobile station, i.e. mobile satellite service
- H04B7/18532—Arrangements for managing transmission, i.e. for transporting data or a signalling message
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Astronomy & Astrophysics (AREA)
- Aviation & Aerospace Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Radio Relay Systems (AREA)
Abstract
The invention discloses a signal demodulation processing plate for a satellite communication gateway station, including an intermediate frequency signal receiver. The intermediate frequency signal receiver is connected with at least two A/D converters, one A/D converter is directly connected with an FPGA unit, and the rest A/D converters are all connected with a DDC. The DDC is connected with the FPGA unit. The FPGA unit is connected with a DSP unit and a communication interface. The FPGA unit comprises a numerical control oscillation module. The numerical control oscillation module is connected with a cascaded integrator comb filter module. The cascaded integrator comb filter module is connected with a halfband filter module. The halfband filter module is connected with a channelization poly-phase filterbank module. The signal demodulation processing plate for the satellite communication gateway station utilizes the FPGA to achieve the DDC function, and the FPGA unit is internally provided with a channelization poly-phase filterbank, thereby achieving multi-channel signal simultaneous processing on the basis of not increasing the processing plate structure.
Description
Technical field
The present invention relates to satellite mobile communication signal exchange technical field, more particularly to a kind of satellite communication gateway station signal
Demodulation process plate.
Background technology
Satellite mobile communication be exactly on the earth between the radio communication station on (in including ground and lower atmosphere layer) using defending
The communication that star is carried out as in then.Satellite plays relay station in the air, after the electromagnetic wave put forward by earth station amplifies
It is counter again to send another earth station back to.Gateway station is then the link that satellite system is formed, and the effect of gateway station is mainly to provide satellite shifting
Dynamic communication system and ground fixed communication network, the interface of land mobile communication net, realize interconnection；Control satellite mobile terminal is accessed
Satellite communication system, and ensure that its signal in communication process does not interrupt.
Satellite communication gateway station signal demodulation process plate is the important component part of satellite mobile communication system, satellite communication
Gateway station signal demodulation process plate is demodulated, is processed to the intermediate-freuqncy signal of satellite launch, is then exported.With satellite communication
Constantly develop, the signal demodulation process information of gateway station is improved constantly, and image, voice-and-data information are constantly improved, and is needed
The image of gateway station signal demodulation process plate process, voice-and-data information also constantly increase, and message transmission rate is improved constantly.
Digital down converter (DDC), with functions such as Digital Down Convert, data pick-ups, is satellite communication gateway station signal demodulation process
One of important components and parts of plate.Traditional DDC digital down converters do not account for the filtering extraction of bandwidth signal, and process bandwidth is not
The multichannel requirement in broadband can be reached, satellite communication gateway station can only be caused with limited combination configuration wave filter and withdrawal device
The hardened structure increase of signal demodulation process.Additionally, the structure of special purpose DDC chip is fixed, bandwidth can not meet high-speed data (such as larger than
The requirement for 400Mbps) demodulating.
The content of the invention
It is an object of the invention to provide a kind of satellite communication gateway station signal demodulation process plate, the signal demodulation process plate
Digital Down Convert is completed using FPGA, multi-channel signal processing is realized, and is not increased process plate structure.
In order to realize foregoing invention purpose, the invention provides technical scheme below：A kind of satellite communication gateway station signal
Demodulation process plate, including intermediate-freuqncy signal receiver, the intermediate-freuqncy signal receiver is connected with least two A/D converters, wherein
One A/D converter is directly connected to FPGA unit, and remaining A/D converter is all connected with DDC digital down converters, and the DDC is digital
Low-converter connects FPGA unit, FPGA unit connection DSP unit and communication interface, and FPGA unit includes numerical control oscillation module,
The numerical control oscillation module connects cascaded integrator-comb filtration module, and the cascaded integrator-comb filtration module connects semi-band filtering
Module, the semi-band filtering module connecting channel multiphase filter group module.
The A/D converter is used for completing the numeral conversion of analog intermediate frequency signal；The DDC digital down converters are used for filtering
Ripple, signal adjustment and down-converted；The data signal that on the one hand FPGA unit will be processed through DDC digital down converters
Enter row format conversion, semi-band filtering, demodulation and decoding, on the other hand directly by the data signal after A/D converter is changed
Down-converted is carried out, then is filtered and is demodulated；The DSP unit carries out configuring calculating process to the signal for receiving, and processes
Information afterwards is exported by communication interface.
Preferably, the communication interface is VPX interfaces.VPX interfaces have more I/O ports, support the number of high speed
According to transmission, it is adapted to the timely process of high-speed digital signal, disposal ability is expansible, external interface is replaceable, anti-seismic performance is high.
Compared with prior art, beneficial effects of the present invention：Satellite communication gateway station signal demodulation process plate of the present invention, profit
Realize in DDC digital down converter functions, and FPGA unit, arranging channelizing multiphase filter group with FPGA, do not increasing process
Multi channel signals are realized on the basis of hardened structure while processing.And, constitute in FPGA unit the lower change of DDC numerals by configuring
The functional module of frequency device, the data for being capable of achieving transfer rate more than 400Mbps are demodulated.
Description of the drawings：
Fig. 1 is satellite communication system signal transmission, process flow block diagram；
Fig. 2 is signal demodulation process plate structured flowchart of the present invention；
Fig. 3 is intermediate-freuqncy signal receiver and A/D converter catenation principle block diagram；
Fig. 4 is DDC digital down converters and FPGA unit catenation principle block diagram；
Fig. 5 is to realize the theory diagram of multi channel signals down-converted in FPGA unit；
Fig. 6 is FPGA unit and DSP unit catenation principle block diagram；
Fig. 7 is A/D converter and FPGA unit catenation principle block diagram；
Fig. 8 is FPGA unit and VPX interface catenation principle block diagrams.
Specific embodiment
With reference to test example and specific embodiment, the present invention is described in further detail.But this should not be understood
Scope for above-mentioned theme of the invention is only limitted to below example, and all technologies realized based on present invention belong to this
The scope of invention.
As shown in figure 1, satellite sends signal, ground-plane antenna is by signal Jing downlink transmissions to earth station；Earth station
The small-signal for receiving is transmitted to low-noise amplifier unit, to ensure to receive the quality of signal；The amplified signal
Frequency transformation is carried out through low-converter again, signal is amplified again, export the intermediate-freuqncy signal of different frequency；Further amplify
The demodulated device signal-processing board of the intermediate-freuqncy signal is demodulated, encode after obtain corresponding information, and export the information.
With reference to Fig. 2, Fig. 5, the satellite communication gateway station signal demodulation process plate that the present embodiment is enumerated includes that intermediate-freuqncy signal connects
Receive device, at least two A/D converters, DDC digital down converters, FPGA unit, DSP unit and VPX interfaces, wherein, it is described in
Frequency signal receiver connects A/D converter, and one of A/D converter is directly connected with FPGA unit, and FPGA unit includes number
Control oscillation module, numerical control oscillation module connection cascaded integrator-comb filtration module (CIC), the cascaded integrator-comb filtering
Module connection semi-band filtering module (HB), the semi-band filtering module connecting channel multiphase filter group module, remaining A/D
Converter connects DDC digital down converters, and the DDC digital down converters connect FPGA unit, FPGA unit connection DSP unit
With VPX interfaces.Numerical control oscillation module, cascaded integrator-comb filtration module, semi-band filtering module and channelizing in FPGA unit
Multiphase filter group module is by programming the graphical device for generating.
Numerical control oscillation module, cascaded integrator-comb filtration module in FPGA unit, semi-band filtering module realize tradition DDC
The down-converted function of digital down converter, with reference to channelizing multiphase filter group module, is capable of achieving multi-channel signal processing.
Realize being familiar with frequency down-conversion function using FPGA, reduce the usage amount of DDC digital down converters, reduces cost, while also reducing
The structure of process plate；Multi-channel signal processing is realized, processing cost is on the one hand reduced, on the other hand be also avoid because of channelizing
The use of multiphase filter group and caused process plate structure increases.
The workflow of satellite communication gateway station signal demodulation process plate of the present invention is：Intermediate-freuqncy signal receiving unit will be received
Analog intermediate frequency signal transmit to A/D converter, analog intermediate frequency signal is converted to data signal by A/D converter, then one
The digital data transmission of subchannel (is provided with multiple DDC Digital Down Converts to each DDC digital down converter in usual process plate
Device, a DDC digital down converter carry out down-converted to the data signal of a passage), each DDC digital down converter
The data signal is filtered, signal is adjusted and down-converted, is then transmit to FPGA unit, FPGA unit is under process
The data signal of frequency-conversion processing enters row format conversion, semi-band filtering, demodulation, decoding；The data signal of another part passage is direct
Transmit to FPGA unit：The sheet that digital controlled oscillator from the digital intermediate frequency signal and FPGA unit of A/D converter output is produced
Shake signal multiplication, and the digital intermediate frequency signal is down-converted to zero intermediate frequency signals, and the zero intermediate frequency signals sequentially pass through cascade integral comb again
Shape wave filter, half-band filter and channelizing multiphase filter group, carry out filtering extraction, if while broadband signal is uniformly divided into
The output of dry sub-band signal, completes DDC digital down converters module to the down coversion of intermediate-freuqncy signal, filtering, signal adjustment process,
It is then transmit to DSP unit.DSP unit carries out configuring calculating process, digital demodulation process to the data signal for receiving, after process
Signal return again to FPGA unit, the signal after process is exported by VPX interfaces Jing after FPGA unit filtering, VPX interfaces company
Computer and disk array is connected to, the information is stored in computer disk array by RAID array card, facilitates researcher
Research.
Each component units of satellite communication gateway station signal demodulation process plate of the present invention and each unit annexation are specifically retouched
State as follows.
With reference to Fig. 3, intermediate-freuqncy signal receiving unit includes tuner, and analog intermediate frequency signal is received by tuner, then through resistance
Resistance is transmitted to A/D converter after changing.The input clock of A/D converter can be input into by external clock, it is also possible to by common crystalline substance
Shake or constant-temperature crystal oscillator is provided, the input clock of A/D converter is provided by constant-temperature crystal oscillator in the present embodiment.When A/D converter is sampled
Clock requires that quality is high, and phase noise is low, if clock signal jitter is larger, signal to noise ratio easily deteriorates, it is difficult to ensure that effectively adopting
The precision of sample digit.In order to optimize performance, the clock input of A/D converter is input into using the clock of difference low jitter, will input
Clock is processed as LVPECL signals, by being ac-coupled to A/D converter.
One DDC digital down converter can connect 4 A/D converters, and each A/D converter takes DDC Digital Down Converts
One data channel of device.A/D converter, the output level of DDC digital down converters are 3.3V, using dc-couple mode
Connection.A/D converter output data bit width is 14, and DDC digital down converter data inputs bit width is 17.A/D turns
Parallel operation is output as TWOS complement formats, due to data bit width misalignment, so by A/D converter and DDC digital down converters
Data align according to highest order, the unnecessary low level of DDC digital down converters is drop-down.
With reference to Fig. 4, a FPGA unit can connect 4 DDC digital down converters.DDC digital down converters are mono- with FPGA
The interconnection of unit includes the input control interconnection of DDC digital down converters, output signal is interconnected, control signal is interconnected.
DDC digital down converters include that four inputs enable pin and carry out input control interconnection, every DDC with FPGA unit
Digital down converter takes 4 3.3V I/O pins of FPGA unit altogether.
In the present embodiment, the output data passage divided data enable of DDC digital down converters, frame synchronization are enabled, output makes
Can three classes.The output signal of DDC digital down converters also provides VGA/ adjustable attenuations output channel all the way and two output clocks
Pin, the signal that DDC digital down converters are connected in FPGA unit include tetra- output data passages of A, B, C, D and two it is defeated
Go out clock pins.
DDC digital down converters include hardware controls and MPI control with the control signal interconnection of FPGA unit
Two classes.Hardware controls have synchronous input, synchronism output, reset three kinds of signals, take 4 3.3V I/O pipes of FPGA unit altogether
Pin.MPI control takes 23 3.3V I/O pins of FPGA unit altogether.
With reference to Fig. 6, FPGA unit is mutual by way of the EMIFA of DSP is with dc-couple with the data channel of DSP unit
Even.DSP unit controls have reset (RESET) signal, non-maskable interrupts (NMI) signal, reset state output with status signal
(RESETSTAT) signal, electrification reset (POR) signal, GPIO [3：0] signal, TIMER1 signals, TIMER2 signals, IIC letters
Number.The AECLKIN signal pins and AECLKOUT signal pins of DSP unit are connected to the clock pins of FPGA unit.DSP unit
Two-way McBSP in the form of multi-channel synchronous serial ports with FPGA unit interconnect.
With reference to Fig. 7, the interconnection between A/D converter and FPGA unit is needed through backplane connector, A/D converter with
Control between FPGA unit is connected by two pins of OVR and RDY with condition line.
With reference to Fig. 8, VPX interfaces complete the communication of FPGA unit and host computer, make local bus be quickly transferred to VPX buses
On.Pass through 3.3V LVTTL (Low Voltage Transistor-Transistor between FPGA and VPX EBIs
Logic) connect, FPGA and VPX has 8 single-ended LVTTL pins direct interconnections, also two single-ended LVTTL pins and serial ports control
Coremaking piece MAX3232 interconnection realizes that two-way serial ports is connected to VPX.
Claims (3)
1. a kind of satellite communication gateway station signal demodulation process plate, including intermediate-freuqncy signal receiver, the intermediate-freuqncy signal receiver
It is connected with least two A/D converters, it is characterised in that one of A/D converter is directly connected to FPGA unit, remaining A/D
Converter is all connected with DDC digital down converters, and the DDC digital down converters connect FPGA unit, and connection DSP is mono- for FPGA unit
Unit and communication interface, FPGA unit include numerical control oscillation module, the numerical control oscillation module connection cascaded integrator-comb filtering mould
Block, the cascaded integrator-comb filtration module connect semi-band filtering module, the semi-band filtering module connecting channel multiphase filter
Ripple device group module.
2. the satellite communication gateway station signal demodulation process plate based on PCI-E interface according to claim 1, its feature exist
In the A/D converter completes the numeral conversion of analog intermediate frequency signal；The DDC digital down converters are for filtering, signal is adjusted
Whole and down-converted；On the one hand the data signal processed through DDC digital down converters is entered row format by the FPGA unit
On the other hand data signal after A/D converter is changed directly is carried out lower change by conversion, semi-band filtering, demodulation and decoding
Frequency is processed, then is filtered and is demodulated；The DSP unit carries out configuring calculating process, the information after process to the signal for receiving
Exported by communication interface.
3. the satellite communication gateway station signal demodulation process plate based on PCI-E interface according to claim 1 and 2, which is special
Levy and be, the communication interface is VPX interfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610899599.6A CN106533533A (en) | 2016-10-12 | 2016-10-12 | Signal demodulation processing plate for satellite communication gateway station |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610899599.6A CN106533533A (en) | 2016-10-12 | 2016-10-12 | Signal demodulation processing plate for satellite communication gateway station |
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| Publication Number | Publication Date |
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| CN106533533A true CN106533533A (en) | 2017-03-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610899599.6A Pending CN106533533A (en) | 2016-10-12 | 2016-10-12 | Signal demodulation processing plate for satellite communication gateway station |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112564763A (en) * | 2020-11-23 | 2021-03-26 | 中国人民解放军国防科技大学 | Universal digital satellite load hardware platform |
-
2016
- 2016-10-12 CN CN201610899599.6A patent/CN106533533A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112564763A (en) * | 2020-11-23 | 2021-03-26 | 中国人民解放军国防科技大学 | Universal digital satellite load hardware platform |
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Application publication date: 20170322 |
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| WD01 | Invention patent application deemed withdrawn after publication |