CN209184591U - A kind of global function Digital IF Processing platform - Google Patents
A kind of global function Digital IF Processing platform Download PDFInfo
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- CN209184591U CN209184591U CN201822133309.4U CN201822133309U CN209184591U CN 209184591 U CN209184591 U CN 209184591U CN 201822133309 U CN201822133309 U CN 201822133309U CN 209184591 U CN209184591 U CN 209184591U
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Abstract
A kind of global function Digital IF Processing platform of the utility model, comprising: AGC amplifier, A/D conversion module, D/A conversion module, power amplifier, numerical-control attenuator, filter module, FPGA module and outer input interface, the external output interface being set on support plate.If the platform identical and independent analog signal input channel including main line, and each analog signal input channel is input from the outside interface, filter module, AGC amplifier, A/D conversion module and is in turn connected to form；And if the identical and independent analog signal output channel including main line, and each analog signal output channel is in turn connected to form by D/A conversion module, bandlimiting filter, programmable attenuator；To sum up, the utility model uses a variety of external data interfaces, can satisfy a variety of processing speed demands, realizes modulation and demodulation integrated design, has highly compatible, configurability and scalability.
Description
Technical field
The utility model belongs to digital information processing system technical field, and it is flat to be related to a kind of global function Digital IF Processing
Platform.
Background technique
In recent years, being increasing with the development of satellite technology and in-orbit quantity, satellite application has become satellite technology
The Main way of development.Wherein the reception and processing of satellite data are the development priority in satellite application field, Digital Signal Processing
System mainly realizes the IF signal processing of satellite data.
The image resolution ratio of remote sensing satellite is promoted and data volume increases, so that existing number biography X frequency range has been unable to meet and answers
With demand, the main number for becoming subsequent remote sensing satellite is passed frequency range by Ka frequency range, to the sample frequency and processing of data receiving system
More stringent requirements are proposed for ability, currently used digital information processing system be passed according to the frequency range of satellite and number bit rate into
Row customization is usually made of signal pre-processing circuit, intermediate frequency data processing board and industrial control computer mainboard etc..At digital signal
The important component of reason system, intermediate frequency data processing board is the key that the performance for promoting digital information processing system.
The intermediate frequency data processing board of current practice is all special equipment, and existing disadvantage is as follows: 1) poor compatibility,
The different types of intermediate frequency data of design of satellites to pass frequency range or bit rate for different numbers handles board；2) it has a single function, mesh
It is preceding to be directed to two kinds of functions of modulation and demodulation in satellite data processing, it needs to design different medium frequency processing equipments according to uplink and downlink；
(3) poor expandability, product function is relatively fixed, and not having can open and additional extension function.
Summary of the invention
Problems to be solved by the invention are to solve that existing intermediate frequency data processing board card compatibility is poor, has a single function, is expansible
Property difference problem, the present invention proposes a kind of global function Digital IF Processing platform, can satisfy a variety of processing speed demands.
Technological means for solving project is that the utility model proposes a kind of global function Digital IF Processing platform, packets
It includes: AGC amplifier, A/D conversion module, D/A conversion module, power amplifier, the numerical-control attenuator, filtering being set on support plate
Device module, FPGA module and outer input interface, external output interface；
Wherein, if the platform includes that main line is identical and independent analog signal input channel, and each analog signal is defeated
Enter channel and be input from the outside interface, filter module, AGC amplifier, A/D conversion module to be in turn connected to form；The filter
Module for the intermediate-freuqncy signal by reception outer input interface input and realizes filtering；The AGC amplifier, for filter
The intermediate-freuqncy signal amplification of wave device module output and automatic growth control；The A/D conversion module, it is defeated for realizing AGC amplifier
Intermediate-freuqncy signal out is converted into digital medium-frequency signal, and inputs FPGA module；
The FPGA module, for connecting the A/D conversion module in each analog signal input channel, the number after receiving conversion
Baseband digital signal is generated after word intermediate-freuqncy signal and data processing, by exporting the D/ into each output digit signals output channel
A conversion module；
If the platform identical and independent analog signal output channel including main line, and each analog signal output channel
It is in turn connected to form by D/A conversion module, bandlimiting filter, programmable attenuator；The D/A conversion module, for FPGA mould
The baseband digital signal of block output is converted into base-band analog signal；The bandlimiting filter, for what is converted to D/A conversion module
Base-band analog signal band limiting filtering；The programmable attenuator, for the base-band analog signal after bandlimiting filter band limiting filtering
Attenuation control, and other boards are output this to by external output interface.
Further, as a kind of optimal technical scheme of the utility model, each analog signal output channel is also
Including FIR interpolation filter and upconverter, the FIR interpolation filter is used for the baseband digital signal exported to FPGA module
Carry out filtering interpolation；The upconverter, for being inputted after the filtered baseband digital signal up-conversion of FIR interpolation filter
D/A conversion module.
Further, as a kind of optimal technical scheme of the utility model, the outer input interface and external output
Interface includes at least one of RS422 interface, LVTTL interface, TLL interface, network interface or a variety of.
Further, as a kind of optimal technical scheme of the utility model, the RS422 interface, LVTTL interface, TLL
Interface, network interface correspond to different application scenarios configuration different rates, the interface of different bit wides carries out data exchange.
Further, as a kind of optimal technical scheme of the utility model, the FPGA module further includes a configuration
Independent PROM, and FPGA module and PROM are connected in the same JTAG daisy chain.
Further, as a kind of optimal technical scheme of the utility model, the FPGA module using XC7K325T or
XC7K410T type.
Further, as a kind of optimal technical scheme of the utility model, the FPGA module further includes 8 tunnels drawn
GTX high-speed transceiver, wherein 4 tunnels are for the interconnection between FPGA module, in addition 4 tunnels are used for external expansion.
Invention effect are as follows:
A kind of global function Digital IF Processing platform of the utility model is integrated large-scale F PGA, high-speed a/d, high speed
The global function Digital IF Processing platform that D/A, baseband I/O, filtering and gain control.For solving existing intermediate frequency data processing
Board poor compatibility, have a single function, poor expandability the problem of, can with high frequency or intermediate-frequency circuit direct interface, and at it
Required various communication process algorithms are realized in upper programming, and being provided simultaneously with sufficiently can open and sophisticated software and routine branch
It holds, user can develop other application on it.
Compared with prior art, the present invention advantage is: (1) using a variety of external data interfaces, meet a variety of processing speed
Rate demand has highly compatible.(2) it can be provided simultaneously with digital-to-analogue conversion, analog-to-digital conversion and Up/Down Conversion function, realize satellite
The modulation and demodulation integrated design of base band data.(3) have configurability and scalability, user can develop it on it
It applies and supports a variety of data-interfaces.
Detailed description of the invention
Fig. 1 is the composition schematic diagram of this hair utility model function digit IF process platform.
Specific embodiment
In order to which the purpose of this utility model, technical solution and innovative point is more clearly understood, below in conjunction with attached drawing and reality
Example is applied, the utility model is described in further detail.It should be understood that specific embodiment described herein is only used for explaining
The utility model is not used to limit the utility model.
The utility model is elaborated with reference to the accompanying drawing.
As shown in Figure 1, the present invention proposes a kind of global function Digital IF Processing platform, and it is 6U standard plate formats, the pass on plate
Key unit circuit can install independent shielding case additional to prevent from interfering.The platform specifically includes that the AGC being set on support plate amplifies
Device, A/D conversion module, D/A conversion module, power amplifier, numerical-control attenuator, filter module, FPGA module and outside are defeated
Incoming interface, external output interface；
Wherein, the platform includes that 4 tunnels are identical and independent analog signal input channel, and the input of each analog signal is logical
Road is input from the outside interface, filter module BPF, AGC amplifier, A/D conversion module and is in turn connected to form；The filter mould
Block BPF for the intermediate-freuqncy signal by reception outer input interface input and realizes filtering；The AGC amplifier, for filter
The intermediate-freuqncy signal amplification of wave device module output and automatic growth control；The A/D conversion module, it is defeated for realizing AGC amplifier
Intermediate-freuqncy signal out is converted into digital medium-frequency signal, and inputs FPGA module；It is originally, the radio frequency that inputted by SMA interface or
Person's intermediate-freuqncy signal injection A/D conversion module after AGC amplification and anti-aliasing filter is converted to continuous Serial No., input letter
Number maximum frequency be 500MHz, i.e. 500MHz intermediate frequency below or radiofrequency signal can be fed directly into.The intermediate frequency of input is believed
When number intensity changes in about -80~+0dBm range, AGC amplifier can be amplified on the voltage of suitable A/D range,
The sample rate of A/D conversion module is adjustable, and filter module can replace different parameters according to specific system parameter.
The FPGA module, for connecting the A/D conversion module in each analog signal input channel, the number after receiving conversion
Baseband digital signal is generated after word intermediate-freuqncy signal and data processing, by exporting the D/ into each output digit signals output channel
A conversion module；
The platform includes that 4 tunnels are identical and independent analog signal output channel, and each analog signal output channel by
D/A conversion module, bandlimiting filter AMP, programmable attenuator ATT are in turn connected to form, can also include FIR interpolation filter and
Upconverter；The baseband digital signal that the FIR interpolation filter is used to export FPGA module carries out filtering interpolation；On described
Frequency converter, for input D/A conversion module after the filtered baseband digital signal up-conversion of FIR interpolation filter；The D/A
Conversion module is converted into base-band analog signal for the baseband digital signal to FPGA module；The bandlimiting filter AMP is used
In the base-band analog signal band limiting filtering converted to D/A conversion module；The programmable attenuator ATT, for bandlimiting filter
The attenuation of base-band analog signal after band limiting filtering controls, and outputs this to other boards by external output interface.
Its principle is, the base-band digital stream generated in FPGA module passes through this channel, can be converted directly into intermediate frequency or
Radiofrequency signal output.Wherein, interpolation and up-conversion are optional, i.e., D/A mould conversion block can also work in pass-through state.By
Analog output signal after D/A conversion is sent into bandlimiting filter AMP, is sent into numerical-control attenuator ATT after band limiting filtering, finally exists
The output of SMA interface.Wherein the attenuation of numerical-control attenuator is adjustable, is controlled by FPGA module.
The plug-in DDR3SDRAM memory of each FPGA module to extend its storage capacity, can draw RS422 or
TTL signal and the port GTX.Each FPGA module has pci bus interface, and computer can directly exchange data with them.
FPGA module has instant allocative abilities, and the computer program of user can replace FPGA module by software interface function at any time
The program of interior operation, program, which can also solidify, to be automatically configured in PROM onboard when powering on.
The present embodiment preferably, the FPGA module can plug-in independent a configuration PROM, FPGA and PROM be connected on
In the same JTAG daisy chain；Further, the FPGA module can also draw 8 road GTX high-speed transceivers, wherein 4 tunnels are used for
Interconnection between FPGA module, in addition 4 tunnels are used for external expansion.
Also, the FPGA module has a set of programmable pll clock network, by an external clock input interface, one
High stable crystal oscillator, a programmable PLL and a set of clock distribution circuit are constituted.Clock system can be to all A/D moulds
The element circuits such as block, D/A module and FPGA module provide clock signal.In addition to above-mentioned multi-source global clock network, gone back on plate
There is the auxiliary clock of a 40MHz, can be used as control and data transmission is used.
The outer input interface and external output interface, it is main complete between different external boards and server
Data exchange, input/output interface mode is settable, be suitable for application scenarios including at least RS422 interface, LVTTL interface,
One of TLL interface, network interface are a variety of.Also, the RS422 interface, LVTTL interface, TLL interface, network interface
The interface progress data exchange of corresponding different application scenarios configuration different rates, different bit wides；The driving chip of all signals
Power supply can hardware exchange 3.3V or 5V driving voltage.It is recommended to use default 3.3V voltage, because in such a mode, output electricity
It is flat to be all compatible with TTL, LVTTL and RS422.If certain group signal goes for the sufficiently high driving electricity as being more than 3.3V
It is flat, then can cut be changed to 5V power supply.
Each FPGA module is attached to a multichannel and assists A/D conversion module, and the content that can be measured includes: AGC's
Gain-controlled voltage, 5V main power voltage, 12V analog power voltage assist connecting between A/D and FPGA using SPI serial ports.Often
A FPGA module is also accompanied with 3 road low speed D/A conversion modules, can export -10 to+10V analog voltages, can be used for watching outside
The control of dress system.It can receive the B code Shi Tongxin of TTL or analog-modulated waveform positioned at an independent SMA interface of front panel
Number.
And the Xilinx Kintex 7 of FPGA internal interface the ripening degree of selection and advanced relatively balance, it is corresponding
FPGA concrete model can select XC7K325T and XC7K410T type two according to the actual situation.
To sum up, the platform of the utility model can satisfy a variety of processing speed demands using a variety of external data interfaces,
It realizes modulation and demodulation integrated design, has highly compatible, configurability and scalability.
The example that above-described embodiment gives a limited range the utility model is described in detail, and it cannot be said that
The embodiments of the present invention is only limitted to this, all for the utility model person of an ordinary skill in the technical field
Any simple modification and equivalent structure transformation or modification, belong to the utility model according to made by the spirit of the present invention essence
The protection scope that the claims submitted determine.
Claims (7)
1. a kind of global function Digital IF Processing platform characterized by comprising AGC amplifier, the A/D being set on support plate
Conversion module, D/A conversion module, power amplifier, numerical-control attenuator, filter module, FPGA module and outer input interface,
External output interface；
Wherein, if the platform includes that main line is identical and independent analog signal input channel, and the input of each analog signal is logical
Road is input from the outside interface, filter module, AGC amplifier, A/D conversion module and is in turn connected to form；The filter module,
For the intermediate-freuqncy signal by reception outer input interface input and realize filtering；The AGC amplifier, for filter mould
The intermediate-freuqncy signal amplification of block output and automatic growth control；The A/D conversion module, for realizing in AGC amplifier output
Frequency signal is converted into digital medium-frequency signal, and inputs FPGA module；
The FPGA module, for connecting the A/D conversion module in each analog signal input channel, in the number after receiving conversion
Baseband digital signal is generated after frequency signal and data processing, is turned by the D/A exported into each output digit signals output channel
Change the mold block；
If the platform identical and independent analog signal output channel including main line, and each analog signal output channel is by D/
A conversion module, bandlimiting filter, programmable attenuator are in turn connected to form；The D/A conversion module, for defeated to FPGA module
Baseband digital signal out is converted into base-band analog signal；The bandlimiting filter, the base band for being converted to D/A conversion module
Analog signal band limiting filtering；The programmable attenuator, for declining to the base-band analog signal after bandlimiting filter band limiting filtering
Decrement control, and other boards are output this to by external output interface.
2. global function Digital IF Processing platform according to claim 1, which is characterized in that each analog signal output
Channel further includes FIR interpolation filter and upconverter, and the FIR interpolation filter is used for the base band number exported to FPGA module
Word signal carries out filtering interpolation；The upconverter, for the filtered baseband digital signal up-conversion of FIR interpolation filter
D/A conversion module is inputted afterwards.
3. global function Digital IF Processing platform according to claim 1, which is characterized in that the outer input interface and outer
Portion's output interface includes at least one of RS422 interface, LVTTL interface, TLL interface, network interface or a variety of.
4. global function Digital IF Processing platform according to claim 3, which is characterized in that the RS422 interface, LVTTL
Interface, TLL interface, network interface correspond to different application scenarios configuration different rates, the interface of different bit wides carries out data friendship
It changes.
5. global function Digital IF Processing platform according to claim 1, which is characterized in that the FPGA module further includes one
A independent PROM of configuration, and FPGA module and PROM are connected in the same JTAG daisy chain.
6. global function Digital IF Processing platform according to claim 1, which is characterized in that the FPGA module uses
XC7K325T or XC7K410T type.
7. global function Digital IF Processing platform according to claim 1, which is characterized in that the FPGA module further includes drawing
8 road GTX high-speed transceivers out, wherein 4 tunnels are for the interconnection between FPGA module, in addition 4 tunnels are used for external expansion.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201822133309.4U CN209184591U (en) | 2018-12-19 | 2018-12-19 | A kind of global function Digital IF Processing platform |
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| CN201822133309.4U CN209184591U (en) | 2018-12-19 | 2018-12-19 | A kind of global function Digital IF Processing platform |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112398581A (en) * | 2020-07-30 | 2021-02-23 | 上海航天测控通信研究所 | All-digital modulation satellite-borne code modulation system and method |
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2018
- 2018-12-19 CN CN201822133309.4U patent/CN209184591U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112398581A (en) * | 2020-07-30 | 2021-02-23 | 上海航天测控通信研究所 | All-digital modulation satellite-borne code modulation system and method |
| CN112398581B (en) * | 2020-07-30 | 2021-06-04 | 上海航天测控通信研究所 | All-digital modulation satellite-borne code modulation system and method |
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