CN102368689B - Multi-point data transmission system based on wireless spread spectrum communication - Google Patents
Multi-point data transmission system based on wireless spread spectrum communication Download PDFInfo
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Abstract
The invention discloses a multi-point data transmission system based on wireless spread spectrum communication. Both a transmitting terminal and a receiving terminal employ modular software and hardware designs, main signal processing work of the system is realized in a programmable logic device, a hardware structure is simplified, and system power consumption and volume are reduced. Simultaneously, the receiving terminal employs digital intermediate frequency reception technology to sample a signal at intermediate frequency, instant processing signal bandwidth in the digital intermediate frequency reception technology is substantially increased, a dynamic range is large, expandability is good, flexibility is high, simultaneously since a simulation link is reduced in a receiver, noise introduced from a front end is reduced, signal distortion is lessened, and a circuit is more concise. The receiving terminal employs a mode of carrying out parallel processing on received data, modularization of a software processing process is realized, and to different transmitting terminals, accurate reception can be realized only modifying a plurality of parameters. Simultaneously, a system capacity expanding method is simple, when quantity of the sending terminals is increased, and correspondingly increasing receiving terminal software modules is enough.
Description
Technical field
The present invention relates to a kind of Multi-point data transmission system based on radio spread spectrum communication, system mainly adopts Direct Sequence Spread Spectrum Communication technology, and for the secure data transfer carrying out between multiple transmitting terminals and receiving terminal simultaneously, system is easy to expansion, flexible configuration.
Background technology
Existing spread spectrum data transmission system ubiquity hardware configuration complexity, the defects such as data transmission bauds is low, conventional data transmission system receiving terminal generally adopts the mode of time-division communication in the time receiving the data of multiple transmitting terminals in addition, cannot receive the data of multiple transmitting terminals, this has just greatly reduced the data transmission efficiency of system simultaneously.
The invention provides and a kind ofly can carry out that multiple spot high speed transmission data and antijamming capability are strong, the spread spectrum data transmission system of good confidentiality simultaneously.
Summary of the invention
The object of the invention is to, utilize radio spread spectrum communication technology that a kind of system that can simultaneously carry out multiple spot high speed data transfer is provided.System data transmission rate is 20-80kbps, and the bandwidth of spread-spectrum signal is 5MHz, and IF spot is 70MHz, and radio communication frequency is 400MHz.Spreading code length is 31 to 127, and simultaneity factor has adopted multiuser detection to disturb with the multiple access of removing system in baseband digital signal is processed.
The present invention adopts following technological means to realize:
The invention is characterized in, contain: at least one user's transmitting terminal, and the receiving terminal of a transmitted signal of a reception, wherein:
Each user's transmitting terminal, contains: the first programmable logic device, Direct Digital Frequency Synthesizers DDS, the first local oscillator, simulation up-converter circuit, the first band pass filter, the first low noise amplifier, the second band pass filter, power supply, and transmitting antenna, wherein:
The first programmable logic device, is provided with: user data input interface, software configuration interface, supply module (71), described Direct Digital Frequency Synthesizers DDS(is hereinafter to be referred as DDS) and the initialization module of described the first local oscillator, wherein:
Described user data input interface, for inputting information source data;
Described software configuration interface, for the configuration file of down load application program, and deposits in flash memory;
In described the first programmable logic device, be also provided with:: data processing module, comprise: differential coding and be input as the direct sequence spread spectrum module of PN1 code, wherein: the input of described differential coding module is connected with described user data input interface, described direct sequence spread spectrum module to from the differential coding data acquisition of described differential coding module input with being sent to described DDS Direct-Spread direct sequence spread spectrum, adopt 31 spread spectrum code sequences and 127 GOLD code frequency expansion sequences, described data processing module is inputted the output information of two initialization modules described above.
DDS produces the information source data of local carrier signal after to spread spectrum and carries out two-phase phase shift BPSK modulation, then the information source data after modulation are sent into described simulation up-converter circuit under programmable logic device control;
Simulation up-converter circuit, from described the first local oscillator input local oscillation signal, information source data after the modulation of input are upconverted to rf frequency 400MHz, after the first band pass filter, the first low noise amplifier, the second band pass filter, send through transmitting antenna successively;
Receiving terminal, is a multi-user shared information source data receiver, is provided with: a front end simulation process part, a data buffer and second programmable logic device;
Described front end simulation process part, contains: the analog down treatment circuit of radiofrequency signal, controllable gain amplifier, A/D converter, and clock distributor, wherein:
The analog down circuit of radiofrequency signal, by a reception antenna, the 3rd band pass filter, the second low noise amplifier, the analog down circuit that input is connected with the second local oscillator output, and four-tape bandpass filter is connected in series successively and forms, reception antenna is given the second low noise amplifier the each user's radiofrequency signal sequentially receiving and is done simulation amplification processing after the 3rd band pass filter carries out front-end filtering processing, by analog down circuit, described radiofrequency signal is converted to 70MHz analog intermediate frequency signal again, after four-tape bandpass filter, deliver to described controllable gain amplifier, controllable gain before sampling amplifies,
Controllable gain amplifier is amplified to the amplitude of filtered described 70MHz analog intermediate frequency signal between scope [1,1], then delivers to described A/D converter and sample under described the second programmable logic device control;
A/D converter, be that the clock distribution signal that described clock distributor is set is sampled to described analog intermediate frequency signal with the given 80MHz sample rate of described the second programmable logic device by described the second programmable logic device, as sampling output, deliver to described data buffer buffer memory at the digital intermediate frequency signal that obtains 10MHz after a down-converted;
The second programmable logic device, be provided with: the multiple user data output interfaces (1211-121n) that equate with number of users, n is total number of users, software configuration interface, supply module (72), initialization module, described initialization output: D/A switch signal (18), clock distribution signal (19), local oscillation signal (17) and controllable gain amplifier initializing signal (20), described the second programmable logic device (12) is to control word and the low-power consumption mode control signal of described controllable gain amplifier (101) output multiplication factor, described the second programmable logic device (12) is inputted by the 10MHz digital intermediate frequency signal of described data buffer (9) output and is also inputted the 70MHz analog intermediate frequency signal by four-tape bandpass filter (54) output, in described the second programmable logic device (12), be also provided with:
A data processing module, be connected in series respectively and form Ge road information source data output circuit and form by the synchronous despreading module of a 10MHz digital signal down variable frequency module and each code, carrier frequency synchronization demodulation module and differential decoding module, export each user data, described digital intermediate frequency signal down conversion module input is that the output of 10MHz digital intermediate frequency signal is 2.5MHz baseband signal, is sent to described each base band signal process and the user of each user's apportion by several outputs; Data output circuit, and an automatic gain control module, contain: signal level detection module, comparator and the loop filter of series connection successively, the desired value output module that also has output to be connected with described comparator input terminal, wherein:
Signal level detection module, input is described 70MHz digital intermediate frequency signal, output is the amplitude of the digital intermediate frequency signal on continuous setting quantity sampled point;
Comparator, input is the minimum value by the described digital intermediate frequency signal amplitude of the prior setting of described desired value output module output, in the time that the amplitude of the digital intermediate frequency signal on continuous described setting quantity sampled point is less than described desired value, produce id signal " 1 ", corresponding to the maximum amplification of setting, after described loop filter filtering, be sent to described control word output interface, control the multiplication factor of described controllable gain amplifier, if be greater than described desired value, produce id signal " 0 ", corresponding to other multiplication factors of setting, after described loop filter, be sent to described control word output and carry out controllable gain amplification.
A kind of Multi-point data transmission system based on radio spread spectrum communication of the present invention, compared with prior art, has following obvious advantage and beneficial effect:
Transmitting terminal and receiving terminal have all adopted modularization design of hardware and software, and signal work for the treatment of main system is placed in programmable logic device and is realized, and have simplified hardware configuration, have reduced system power dissipation and volume.Receiving terminal adopts digital intermediate frequency reception technique at intermediate frequency, signal to be sampled simultaneously, the instantaneous processing signals bandwidth of digital intermediate frequency reception technique increases greatly, dynamic range is larger, extensibility is better, flexibility is higher, simultaneously owing to having reduced simulation link in receiver, make noise that front end introduces still less, distorted signals is less, circuit is more succinct.
Receiving terminal adopts parallel processing to receive the mode of data, and software processing procedure modular implementation, only need revise several parameters for different transmitting terminals and can realize accurate reception.Simultaneity factor expansion method is simple, the corresponding receiving terminal software module that increases when transmitting terminal quantity increases.
Brief description of the drawings
Fig. 1 is system fundamental block diagram of the present invention;
Fig. 2 (a) is transmitting terminal hardware module figure of the present invention;
Fig. 2 (b) is transmitting terminal programmable logic device inner function module block diagram;
Fig. 3 (a) is receiving terminal hardware module figure of the present invention;
Fig. 3 (b) is receiving terminal programmable logic device inner function module block diagram;
Fig. 4 is automatic gain control structure figure;
Fig. 5 is system configuration schematic diagram of the present invention.
Wherein:
10 analog down circuit; 11 first programmable logic devices; 12 second programmable logic devices; 101 controllable gain amplifiers; 102 A/D converters; 103 clock distributors; 111 user data input interfaces; 112 software configuration interfaces; Many user data output interfaces of 1211-121n; 122 software configuration interfaces; 2 Direct Digital Frequency Synthesizers DDS; 31 first local oscillators; 32 second local oscillators; 4 simulation up-converter circuits; 51 first band pass filters; 52 second band pass filters; 53 the 3rd band pass filters; 54 four-tape bandpass filters; 61 first low noise amplifiers; 62 second low noise amplifiers; 71 first supply modules; 72 second supply modules; ; 81 transmitting antennas; 82 reception antennas; 9 data buffers.
Embodiment
Below in conjunction with Figure of description, embodiments of the invention are described further:
System fundamental block diagram of the present invention is Fig. 1, and native system can be realized one to one and many-to-one spread spectrum radio transfer of data macroscopic view.User data completes direct sequence spread spectrum and BPSK (Binary Phase Shift Keying at transmitting terminal, two-phase PSK) up-conversion wireless transmission is gone out after modulation, carry out recovering initial data after down-conversion and synchronous despreading and synchronous demodulation at receiving terminal.When system is during for transfer of data one to one, can adopt 31 spreading codes, now the transmission speed of system is 80kbps; In the time that system is many-one transmission, adopt 127 spreading codes, now system transmission speed is 20kbps.
Fig. 2 a is depicted as transmitting terminal hardware module figure of the present invention, and transmitting terminal software program is downloaded in flash memory by software configuration interface 112, and after transmitting terminal powers on and starts working, programmable logic device 11 is written into program and configuration file to start working from flash memory.The task of the programmable logic device 11 of transmitting terminal is that user data is carried out to information source coding, spread spectrum coding; Be configured by control pair Direct Digital Frequency Synthesizers 2, the local oscillator in simulation up-converter circuit 4 is configured.The built-in function logic of programmable logic device 11 as shown in Figure 2 b.Spread spectrum coding part adopts direct sequence spread spectrum, and 31 spreading codes are m sequence, and 127 frequency expansion sequences are GOLD code sequence (a kind of code sequence of Robert S.Gold invention).Digital signal after spread spectrum is converted to analog signal through Direct Digital Frequency Synthesizers 2 by digital signal, deliver to afterwards simulation up-converter circuit 4 and upconvert to rf frequency 400MHz, and then through the first band pass filter 51, signal is carried out to filtering processing, the first low noise amplifier 61 carries out corresponding power amplification to radiofrequency signal, finally sends by antenna 81.
Fig. 3 a is receiving terminal hardware module figure of the present invention, the design of similar transmitting terminal, and receiving terminal software program is also downloaded in flash memory by software configuration interface, and after powering on, programmable logic device 12 is written into program and configuration file to start working from flash memory.The task of the programmable logic device 12 of receiving terminal is that the digital intermediate frequency signal that analog to digital converter 102 is exported carries out Digital Down Convert, the synchronous despreading of code, carrier synchronization demodulation, differential decoding; And carry out corresponding initialization and control operation by the local oscillator in control pair analog to digital converter 102, clock distributor 103, analog down circuit 10, controllable gain amplifier 101.No matter system adopts one to one or many-one structure, front end simulation process part is all done same treatment, be antenna 82 radiofrequency signal receiving is given after the 3rd band pass filter 53 carries out front-end filtering processing the second low noise amplifier 62 do simulation amplify process, carry out analog down by analog down circuit 10 again radiofrequency signal is converted to 70MHz, then the controllable gain of giving before controllable gain amplifier 101 is sampled through four-tape bandpass filter 54 amplifies, the amplitude of analog intermediate frequency signal is amplified between scope [1,1].Delivering to analog to digital converter 102 through the analog intermediate frequency signal of controlled amplification samples, introducing bandwidth Sampling techniques herein samples analog intermediate frequency signal and a down-converted with 80MHz sample rate, obtain the digital signal of 10MHz as sampling output, and give programmable logic device 12 by this digital signal via data buffer 9.The built-in function logic of programmable logic device 12 as shown in Figure 3 b.It is 10MHz that Digital Down Converter Module receives the rear digital signal of sampling, arrives 2.5MHz through Digital Down Convert.The operations such as the synchronous despreading of the digital filtering after Digital Down Convert and code, carrier synchronization demodulation and differential decoding are all to carry out for this 2.5MHz baseband digital signal.
Figure 4 shows that automatic gain control structure figure, this part object is by between the controlled analog if signal amplitude amplitude range [1,1] that is amplified to analog to digital converter 102 defineds.Programmable logic device 12 carries out corresponding control operation by control pair controllable gain amplifier 101, and wherein control line comprises 1 power consumption mode control line and 5 gain control lines.When power consumption mode control line is that controllable gain amplifier 101 is operated in low-power consumption mode below 0.8V time.Article 5, gain control line is used for transmitting the control word signal that programmable logic device 12 produces, altogether corresponding 25 kinds of multiplication factors.In the process consideration actual conditions that control word produces, may occur signal gets too small or interruption situation, now amplify and all can not fall in desired range of values in any case, this can cause overflowing of loop filter, does not have the effect of automatic gain control.Therefore in programming, add an identification module, in the time that continuous multiple signal amplitudes are less than setting minimum value, id signal sign can be made as to ' 1 ', multiplication factor is made as to maximum simultaneously; If during signal amplitude be greater than this thresholding, id signal sign is made as to ' 0 ', and carries out controlled amplification.
Figure 5 shows that system configuration schematic diagram of the present invention, send the structure of receiving terminal parallel receive herein with n transmitting terminal simultaneously.Each user sends the transmission data of oneself to programmable logic device 11 by user data interface 121 respectively, completes herein differential coding, direct sequence spread spectrum to user data.Spread spectrum process is selected respectively the spreading code distributing, and can select 31 m sequences or 127 GOLD code sequences herein for number of users and transmission speed.Signal after spread spectrum completes BPSK modulation under the control of programmable logic device 11, obtains analog intermediate frequency signal.Analog intermediate frequency signal sends by antenna 81 after operating by simulation up-conversion, filtering, power amplification.Receiving terminal simulation part divisional processing completes power amplification, analog down and filtering and controllable gain and amplifies and give analog to digital converter 102 after processing and sample, after sampling, obtain 10MHz digital signal, this digital signal is delivered to the baseband digital signal that carries out Digital Down Convert processing in programmable logic device 12 and obtain 2.5MHz, adopt respectively different user spreading code to carry out the synchronous despreading of code to this baseband digital signal, remove each other and disturb simultaneously, carry out afterwards carrier synchronization demodulation, finally carry out differential decoding and obtain each user data.Said process parallel processing is synchronously carried out, and when realizing multichannel user data, receives.
Claims (1)
1. the Multi-point data transmission system based on radio spread spectrum communication, is characterized in that, contains: at least one user's transmitting terminal, and a receiving terminal that at least receives a transmitted signal, wherein:
Each user's transmitting terminal, contain: the first programmable logic device (11), Direct Digital Frequency Synthesizers DDS (2), the first local oscillator (31), simulation up-converter circuit (4), the first band pass filter (51), the first low noise amplifier (61), the second band pass filter (52), power supply (7) and transmitting antenna (81), wherein:
The first programmable logic device (11), be provided with: user data input interface (111), software configuration interface (112), supply module (71), described Direct Digital Frequency Synthesizers DDS's (2) and described the first local oscillator (31) initialization module, wherein:
Described user data input interface, for inputting information source data;
Described software configuration interface (112), for the configuration file of down load application program, and deposits in flash memory;
In described the first programmable logic device (11), be also provided with: data processing module, comprise: differential coding module and be input as the direct sequence spread spectrum module of PN1 code, wherein: the input of described differential coding module is connected with described user data input interface (111), described direct sequence spread spectrum module to from the differential coding data acquisition of described differential coding module input with being sent to described DDS (2) Direct-Spread direct sequence spread spectrum, adopt 31 spread spectrum code sequences and 127 GOLD spread spectrum code sequences, described data processing module is inputted the initialization information of differential coding module as above and direct sequence spread spectrum module,
DDS (2), control the lower information source data of local carrier signal after to spread spectrum that produce at programmable logic device (11) and carry out two-phase phase shift BPSK modulation, then the information source data after modulating are sent into described simulation up-converter circuit (4);
Simulation up-converter circuit (4), from described the first local oscillator (31) input local oscillation signal, information source data after the modulation of input are upconverted to rf frequency 400MHz, send by transmitting antenna (81) through the first band pass filter (51), the first low noise amplifier (61), the second band pass filter (52) successively;
Receiving terminal, is a multi-user shared information source data receiver, is provided with: front end simulation process part, a data buffer (9) and second programmable logic device (12);
Described front end simulation process part, contains: the analog down treatment circuit of radiofrequency signal, controllable gain amplifier (101), A/D converter (102), and clock distributor (103), wherein:
The analog down treatment circuit of radiofrequency signal, by a reception antenna (82), the 3rd band pass filter (53), the second low noise amplifier (62), the analog down circuit (10) that input is connected with the second local oscillator (32) output, and four-tape bandpass filter (54) is connected in series and forms successively, reception antenna (82) is given the each user's radiofrequency signal sequentially receiving the second low noise amplifier (62) and is done simulation amplification processing after the 3rd band pass filter (53) carries out front-end filtering processing, by analog down treatment circuit (10), described radiofrequency signal is converted to 70MHz analog intermediate frequency signal again, after four-tape bandpass filter (54), deliver to described controllable gain amplifier (101), controllable gain before sampling amplifies,
Controllable gain amplifier (101), the amplitude of filtered described 70MHz analog intermediate frequency signal under controlling, described the second programmable logic device (12) is amplified to scope [1,1] between, then deliver to described A/D converter (102) and sample;
A/D converter (102), the clock distribution signal of setting for described clock distributor (103) by described the second programmable logic device (12) is sampled to described analog intermediate frequency signal with the given 80MHz sample rate of described the second programmable logic device (12), as sampling output, deliver to described data buffer (9) buffer memory at the digital intermediate frequency signal that obtains 10MHz after a down-converted;
The second programmable logic device (12), be provided with: the multiple user data output interfaces (1211-121n) that equate with number of users, n is total number of users, software configuration interface (122), supply module (72), initialization module, described initialization output: D/A switch signal (18), clock distribution signal (19), local oscillation signal (17) and controllable gain amplifier initializing signal (20), described the second programmable logic device (12) is to control word and the low-power consumption mode control signal of described controllable gain amplifier (101) output multiplication factor, described the second programmable logic device (12) is inputted by the 10MHz digital intermediate frequency signal of described data buffer (9) output and is also inputted the 70MHz analog intermediate frequency signal by four-tape bandpass filter (54) output, in described the second programmable logic device (12), be also provided with:
A data processing module, by a 10MHz digital signal down variable frequency module and the synchronous despreading module of each code, carrier frequency synchronization demodulation module and differential decoding module are connected in series respectively and form Ge road information source data output circuit composition, export each user data, described digital intermediate frequency signal down conversion module input is that the output of 10MHz digital intermediate frequency signal is 2.5MHz baseband signal, be sent to each base band signal process and the user data output circuit of each user's apportion by several outputs, secondly also has an automatic gain control module, contain: the signal level detection module of series connection successively, comparator and loop filter, the desired value output module that also has output to be connected with described comparator input terminal, wherein:
Signal level detection module, input is described 70MHz digital intermediate frequency signal, output is the amplitude of the digital intermediate frequency signal on continuous setting quantity sampled point;
Comparator, input is the minimum value by the described digital intermediate frequency signal amplitude of the prior setting of described desired value output module output, in the time that the amplitude of the digital intermediate frequency signal on continuous described setting quantity sampled point is less than described desired value, produce id signal " 1 ", corresponding to the maximum amplification of setting, after described loop filter filtering, be sent to described control word output interface, control the multiplication factor of described controllable gain amplifier (101), if be greater than described desired value, produce id signal " 0 ", corresponding to other multiplication factors of setting, after described loop filter, be sent to described control word output and carry out controllable gain amplification.
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| CN103580721B (en) * | 2013-11-04 | 2015-12-02 | 复旦大学 | Multi-antenna iteration multi-user detection and device in a kind of complicated time-variant multipath channel |
| KR101624739B1 (en) * | 2014-10-15 | 2016-05-26 | 윌커슨벤자민 | Low Power Wideband Non-Coherent BPSK Demodulator to Align the Phase of Sideband Differential Output Comparators for Reducing Jitter, using 1st Order Sideband Filters with Phase 180 Degree Alignment |
| CN104917556B (en) * | 2015-04-16 | 2017-12-08 | 北京理工大学 | A kind of synchronous multibeam signals generation method based on ultrahigh speed DAC |
| CN105577237B (en) * | 2015-12-18 | 2019-03-12 | 国网河南省电力公司安阳供电公司 | A kind of modulation-demo-demodulation method and chip for low-voltage power line carrier communication system |
| US10545561B2 (en) * | 2016-08-10 | 2020-01-28 | Cirrus Logic, Inc. | Multi-path digitation based on input signal fidelity and output requirements |
| CN109243414A (en) * | 2018-09-05 | 2019-01-18 | 厦门轻唱科技有限公司 | K sings system, wireless microphone and its signal transmitting apparatus |
| CN111123814B (en) * | 2018-10-31 | 2021-08-17 | 北京瑞航同达科技有限公司 | Programmable encoder for pulse code modulation frame structure |
| CN109245828A (en) * | 2018-11-22 | 2019-01-18 | 中国工程物理研究院电子工程研究所 | A kind of Terahertz wireless transceiver system for blackout range telemetry communication |
| CN112217520B (en) * | 2020-09-30 | 2023-11-14 | 广州市埃特斯通讯设备有限公司 | Method and system for decoding FM0 encoded data of ETC |
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