CN110768682A - PXIe bus vector signal real-time transceiving module device and method - Google Patents
PXIe bus vector signal real-time transceiving module device and method Download PDFInfo
- Publication number
- CN110768682A CN110768682A CN201911046372.7A CN201911046372A CN110768682A CN 110768682 A CN110768682 A CN 110768682A CN 201911046372 A CN201911046372 A CN 201911046372A CN 110768682 A CN110768682 A CN 110768682A
- Authority
- CN
- China
- Prior art keywords
- signal
- switch
- coupler
- unit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
- H04B1/0053—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band
- H04B1/006—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band using switches for selecting the desired band
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0028—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage
- H04B1/0032—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage with analogue quadrature frequency conversion to and from the baseband
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0028—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage
- H04B1/0042—Digital filtering
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/403—Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
- H04B1/406—Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency with more than one transmission mode, e.g. analog and digital modes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
- H04L25/03834—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using pulse shaping
- H04L25/03853—Shaping by digital methods other than look up tables or up/down converters
Abstract
The utility model provides a PXIe bus vector signal real-time transceiving module device and a method, comprising a signal frequency conversion receiving unit, a signal direct up-conversion unit and a digital processing unit, wherein the signal frequency conversion receiving unit is configured to directly amplify, attenuate and condition a radio frequency signal input by a first port, then directly down-convert the radio frequency signal to a zero intermediate frequency signal, and transmit the radio frequency signal to the digital processing unit; the digital processing unit is configured to generate two orthogonal paths of digital baseband signals in a pseudo-random sequence generation and interpolation filtering mode, generate two orthogonal paths of baseband signals and output two orthogonal paths of analog baseband signals to the direct up-conversion unit; the signal direct up-conversion unit is configured to directly up-convert the two paths of signals orthogonal to the baseband into radio frequency signals and output the radio frequency signals through a second port; the signal frequency conversion receiving unit and the signal direct up-conversion unit realize a double-port test function through a multi-stage routing switching coupling mode.
Description
Technical Field
The disclosure belongs to the technical field of vector signal processing, and particularly relates to a PXIe bus vector signal real-time transceiving module device and method.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
According to the inventor, when the traditional PXIe bus vector signal real-time transceiving module signal occurs, a quadrature modulation direct up-conversion mode is adopted, the digital processing unit generates baseband I path and Q path baseband signals through pseudo-random sequence generation, interpolation filtering and the like, then IQ two path signals are subjected to direct up-conversion on the local oscillation signals of the signal direct up-conversion unit and the local oscillation synthesis circuit, and finally the signals are output after conditioning such as filtering amplification and the like. The superheterodyne structure is sampled during signal analysis, and the frequency spectrum of the input signal is shifted in a frequency conversion mode of a multistage mixer, and is converted to an intermediate frequency for subsequent processing, as shown in fig. 1. An ideal mixer only produces sum and difference frequencies of the radio frequency signal and the local oscillator signal at the intermediate frequency port, but in actual mixing, fundamental and subharmonic signals of the local oscillator and the radio frequency also appear at the intermediate frequency port. When the local oscillator frequency is the same as or close to the intermediate frequency, the local oscillator leakage signal is coupled in the intermediate frequency signal through the intermediate frequency filter, and the local oscillator leakage signal cannot be eliminated by the intermediate frequency filter.
In summary, when a PXIe bus vector signal real-time transceiving module analyzes a signal, a superheterodyne mode is adopted for down-conversion, a multi-stage frequency conversion mode is required, an additional zero-frequency suppression circuit is required, the circuit design is complex, the size is large, the number of grooves is large, the power consumption is high, the cost is high, and the building requirement of a miniaturized automatic test system cannot be met; meanwhile, the function is relatively simple, the vector network analysis function is not available, the network parameter test cannot be carried out, and the multifunctional parameter requirement cannot be met.
Disclosure of Invention
The PXIe bus vector signal real-time transceiving method based on the double direct frequency conversion modulation mode adopts a transceiving sharing FPGA mode to realize the real-time interaction of signal generation and receiving, a receiving channel and a sending channel realize a network parameter testing function through a multi-level routing switching mode, and the functions of vector signal analysis, vector network analysis and the like are highly integrated in a small volume.
According to some embodiments, the following technical scheme is adopted in the disclosure:
a PXIe bus vector signal real-time transceiving module device comprises a signal frequency conversion receiving unit, a signal direct up-conversion unit and a digital processing unit, wherein:
the signal frequency conversion receiving unit is configured to directly amplify, attenuate and condition the radio-frequency signal input by the first port, and then directly down-convert the radio-frequency signal to a zero intermediate-frequency signal, and transmit the signal to the digital processing unit;
the digital processing unit is configured to generate two orthogonal paths of digital baseband signals in a pseudo-random sequence generation and interpolation filtering mode, generate two orthogonal paths of baseband signals and output two orthogonal paths of analog baseband signals to the direct up-conversion unit;
the signal direct up-conversion unit is configured to directly up-convert two paths of baseband orthogonal signals into radio frequency signals and output the radio frequency signals through a second port;
and the signal frequency conversion receiving unit and the signal direct up-conversion unit realize a double-port test function through a multi-stage routing switching coupling mode.
As a further limitation, the signal frequency conversion receiving unit includes a local oscillator synthesis circuit, a first coupler, a multi-stage switch switching circuit, and a filtering and amplifying circuit, where one end of the local oscillator synthesis circuit is connected to the digital processing unit, the other end of the local oscillator synthesis circuit is connected to the multi-stage switch switching circuit through the filtering and amplifying circuit, and the multi-stage switch switching circuit is connected to the first port through the first coupler.
As a further limitation, the signal direct up-conversion unit includes a local oscillator synthesis circuit, a filtering and amplifying circuit, a coupler circuit and a multi-stage switch switching circuit, where one end of the local oscillator synthesis circuit is connected to the output end of the digital processing unit, the other end of the local oscillator synthesis circuit is connected to the filtering and amplifying circuit, the filtering and amplifying circuit is connected to the coupler circuit, and the coupler circuit is connected to the first port and the second port.
As a further limitation, the multi-stage switch switching circuit includes a first switch, a second switch, a third switch and a fourth switch, the first switch, the second switch and the third switch are located in the signal frequency conversion receiving unit and are sequentially connected in series, the first switch is connected with the coupler, and the third switch is connected with the filtering and amplifying circuit; the fourth change-over switch and the second change-over switch share a control end.
By way of further limitation, the coupler circuit includes a third coupler and a second coupler, the third coupler and the second coupler are connected through a fourth switch, the second coupler is connected to the second port, and the third coupler is connected to the filtering and amplifying circuit.
As a further limitation, the digital processing unit includes an ADC acquisition unit, an ADC generation unit, a shared FPGA unit, and a filtering conditioning circuit, wherein one end of the ADC acquisition unit is connected to the local oscillation synthesis circuit of the signal variable frequency receiving unit through the filtering conditioning circuit, the other end of the ADC acquisition unit is connected to the shared FPGA unit, one end of the ADC generation unit is connected to the shared FPGA unit, and the other end of the ADC generation unit is connected to the local oscillation synthesis circuit of the signal direct up-conversion unit through the filtering conditioning circuit.
The working method based on the device comprises the following modes:
(1) vector signal generation:
the digital processing unit generates two orthogonal paths of digital baseband signals in a pseudo-random sequence generation and interpolation filtering mode, the generated two orthogonal paths of baseband signals are filtered and conditioned and then output two orthogonal paths of analog baseband signals to the direct up-conversion unit, the direct up-conversion unit of the signals directly carries out direct orthogonal modulation on the two orthogonal paths of analog baseband signals to directly generate radio frequency modulation signals, and then the radio frequency modulation signals are output by a second port after band-pass filtering and amplification conditioning;
(2) vector signal analysis:
the input signal is filtered, amplified and conditioned in a signal frequency conversion receiving unit, then is subjected to direct down-conversion with a local oscillator synthesis circuit to generate zero intermediate frequency orthogonal two paths of baseband signals, and then is sent to a digital processing unit to generate two paths of digital baseband signals, then the two paths of digital baseband signals are respectively subjected to extraction filtering, and finally signal analysis is carried out;
(3) analyzing network parameters:
the input signal enters through the first port or the second port, and the dual-port test function is realized through a multi-stage routing switching coupling mode.
As a further limitation, in the network parameter analysis mode, when the signal source is at the first port, the radio frequency channel and the baseband processing unit for sharing the vector signal generation are multiplexed first, the signal source outputs the first port through the third coupler, the fourth switch, the second switch, the first switch and the first coupler, and the incident signal for network parameter analysis is generated through the third coupler and the third switch; generating a reflected signal of network parameter analysis through the first coupler and the third selector switch; generating a transmission signal for network parameter analysis through the second coupler, the first change-over switch, the second change-over switch and the third change-over switch; the incident signal, the reflected signal and the transmission signal are finally the receiving part of the shared vector signal analysis, and are converted into two paths of orthogonal baseband signals through direct down-conversion to be sent to the digital processing unit for digital network parameter analysis.
As a further limitation, in the network parameter analysis mode, when the signal source is at the second port, the signal source is generated directly through vector signal generation, and an incident signal for network parameter analysis is generated through the third coupler and the third switch; the second coupler is directly connected to the third selector switch to generate a reflected signal for analyzing the network parameters; generating a transmission signal for network parameter analysis through the first coupler, the first change-over switch, the second change-over switch and the third change-over switch; the incident signal, the reflected signal and the transmission signal are finally the receiving part of the shared vector signal analysis, and are converted into two paths of orthogonal baseband signals through direct down-conversion to be sent to the digital processing unit for digital network parameter analysis.
Compared with the prior art, the beneficial effect of this disclosure is:
the dual-direct-frequency-conversion modulation mode is adopted in the method, the direct up-conversion or down-conversion mode is adopted for signal receiving and signal generation, an additional frequency conversion circuit and a zero-frequency suppression circuit are not needed, the circuit cost, particularly the total power consumption of the circuit, is reduced, and the circuit size is greatly reduced.
The system adopts a multi-stage route coupling mode and a multiplexing radio frequency transceiving channel mode, and not only realizes the functions of vector signal generation and vector signal analysis, but also realizes the function of multiplexing network parameter analysis by signal coupling and switch routing, receiving channel multiplexing and generating channel multiplexing, thereby greatly expanding the application field of the module.
The method adopts a sharing FPGA mode, and the receiving channel and the generating channel share the FPGA to realize the real-time interaction of vector signal receiving and vector signal generating.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and are not to limit the disclosure.
FIG. 1 is a basic block diagram of a prior art signal analyzer of the present disclosure;
FIG. 2 is a schematic structural diagram of the present disclosure;
the specific implementation mode is as follows:
the present disclosure is further described with reference to the following drawings and examples.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
In the present disclosure, terms such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "side", "bottom", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only relational terms determined for convenience in describing structural relationships of the parts or elements of the present disclosure, and do not refer to any parts or elements of the present disclosure, and are not to be construed as limiting the present disclosure.
In the present disclosure, terms such as "fixedly connected", "connected", and the like are to be understood in a broad sense, and mean either a fixed connection or an integrally connected or detachable connection; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present disclosure can be determined on a case-by-case basis by persons skilled in the relevant art or technicians, and are not to be construed as limitations of the present disclosure.
As described in the background art, when a PXIe bus vector signal real-time transceiving module analyzes a signal, a superheterodyne mode is adopted for down-conversion, a multi-stage frequency conversion mode is required, an additional zero-frequency suppression circuit is required, the circuit design is complex, the size is large, the number of slots is large, the power consumption is high, the cost is high, and the building requirement of a miniaturized automatic test system cannot be met;
in addition, the module only integrates the functions of vector signal generation and vector signal analysis, has relatively simple functions, does not have the function of vector network analysis, cannot test network parameters, and cannot meet the requirements of multifunctional parameters.
The embodiment provides a PXIe bus vector signal real-time transceiving method based on a dual-direct frequency conversion modulation mode, aiming at the problems that an existing PXIe vector signal transceiving module needs multi-stage frequency conversion and an additional zero-frequency suppression circuit in a superheterodyne mode to cause large size, large power consumption and the like, only has vector signal generation and vector analysis functions, does not have a network parameter testing function, is relatively simple in function, cannot meet the multifunctional parameter testing requirement and the like, the real-time interaction of signal generation and signal reception is realized in a transceiving sharing FPGA mode, the network parameter testing function is realized by a receiving channel and a sending channel in a multi-stage route switching mode, and functions of vector signal analysis, vector network analysis and the like are highly integrated in a small size. As described in detail below.
The overall implementation block diagram of this embodiment is shown in fig. 2, and mainly includes a digital processing unit, a signal frequency conversion receiving unit, a signal direct up-conversion unit, and the like, and functions such as vector signal generation, vector signal analysis, network parameter test, and the like are implemented in a channel multiplexing mode, a shared FPGA, and a multi-stage routing coupling mode. The digital processing unit comprises an ADC acquisition unit, an ADC generation unit, a shared FPGA unit, a filtering conditioning unit and the like, and the shared FPGA unit is used for realizing baseband signal generation and baseband signal receiving and can realize real-time interaction in receiving and sending; the signal frequency conversion receiving unit comprises a local oscillation synthesis circuit, a direct down-conversion circuit, a filtering conditioning circuit, a coupler circuit, a multi-stage switch switching circuit and the like, and directly amplifies, attenuates and conditions an input radio frequency signal and then directly down-converts the signal to a zero intermediate frequency signal; the signal direct up-conversion unit comprises a local oscillator synthesis circuit, a direct up-conversion circuit, a filtering amplifier, a coupler circuit, a multi-stage switch switching circuit and the like, and directly up-converts two paths of signals of the baseband quadrature into radio frequency signals and outputs the radio frequency signals.
When the vector signal occurs: the shared FPGA unit generates two orthogonal paths of digital baseband signals through pseudo-random sequence generation, interpolation filtering and the like, generates two orthogonal paths of baseband signals, generates filtering through an ADC (analog-to-digital converter), and outputs two orthogonal paths of analog baseband signals to the direct up-conversion unit. In the signal direct up-conversion unit, two orthogonal analog baseband signals and a local oscillator synthesis circuit are subjected to direct orthogonal modulation and then subjected to band-pass filtering, and then output to a multi-level routing switching for direct output.
When vector signals are analyzed, input signals are directly input into a band-pass filter for filtering through a port 1 through multi-stage route switching, then direct orthogonal down-conversion is carried out on the input signals and a local oscillator synthesis circuit, and carrier components are removed to produce two orthogonal zero intermediate frequency baseband signals. And the two paths of zero intermediate frequency baseband signals are subjected to low-pass filtering, then ADC acquisition is carried out to produce two orthogonal paths of baseband digital signals, and finally the two orthogonal paths of baseband digital signals are subjected to extraction filtering for subsequent processing.
When the vector network parameter is tested, the port 1 and the port 2 can be used as input or output, and a dual-port test function is realized in a multi-stage routing switching coupling mode. When a signal source is at a port 1, namely a signal source port 1 is connected through a coupler 3, a switch 4, a switch 2, a switch 1 and a coupler 1, an incident signal for analyzing network parameters is generated through the coupler 3 and the switch 3; generating a reflection signal for analyzing the network parameters through the coupler 1 and the switch 3; the transmission signal for network parameter analysis is generated by the coupling 2, the switch 1, the switch 2 and the switch 3. When the signal source is at the port 2, an incident signal for analyzing the network parameters is generated through the coupler 3 and the switch 3; the reflected signal of the network parameter analysis is generated by directly connecting the coupler 2 to the switch 3; the transmission signal for network parameter analysis is generated by the coupler 1, the switch 2 and the switch 3.
The specific implementation method is described in detail as follows:
(1) vector signal generation
1) A shared FPGA unit in a digital processing unit generates two orthogonal paths of digital baseband signals in the modes of pseudo-random sequence generation, interpolation filtering and the like, and the generated two orthogonal paths of baseband signals are filtered and conditioned by an ADC (analog-to-digital converter) and then output two orthogonal paths of analog baseband signals to a direct up-conversion unit.
2) In the signal direct up-conversion unit, direct quadrature modulation is carried out on two orthogonal analog baseband signals and a local oscillator synthesis circuit to directly generate radio frequency modulation signals, then the radio frequency modulation signals are output to a coupler 3 after being subjected to band-pass filtering, amplification and conditioning, and then the radio frequency modulation signals are output to a port 2 after being amplified, attenuated and conditioned and then directly communicated through a switch 4 and the coupler 2.
(2) Vector signal analysis
1) The input signal is directly transmitted to the switch 1, the switch 2 and the switch 3 through the coupler 1 in the signal frequency conversion receiving unit, then is conditioned by filtering amplification and the like, and then is directly down-converted with the local oscillator synthesis circuit to generate zero intermediate frequency orthogonal two paths of baseband signals, and then is transmitted to the digital processing unit.
2) The zero intermediate frequency orthogonal two paths of baseband signals are firstly filtered by the digital processing unit and then acquired by the ADC to generate two paths of digital baseband signals, then the two paths of digital baseband signals are respectively extracted and filtered, and finally software signal analysis is carried out.
(3) Network parameter analysis
1) When a signal source is at a port 1, firstly multiplexing a radio frequency channel and a baseband processing unit for sharing vector signal generation, and generating an incident signal for network parameter analysis through a coupler 3 and a switch 3 from a coupler 3, a switch 4, a switch 2, a switch 1 and the coupler 1 to a signal source output port 1; generating a reflection signal for analyzing the network parameters through the coupler 1 and the switch 3; the transmission signal for network parameter analysis is generated by the coupling 2, the switch 1, the switch 2 and the switch 3. The incident signal, the reflected signal and the transmission signal are finally the receiving part of the shared vector signal analysis, and are converted into two paths of orthogonal baseband signals through direct down-conversion to be sent to the digital processing unit for digital network parameter analysis.
2) When the signal source is at the port 2, the signal source is directly generated through vector signal generation, and an incident signal for network parameter analysis is generated through the coupler 3 and the switch 3; the reflected signal of the network parameter analysis is generated by directly connecting the coupler 2 to the switch 3; the transmission signal for network parameter analysis is generated by the coupler 1, the switch 2 and the switch 3. The incident signal, the reflected signal and the transmission signal are finally the receiving part of the shared vector signal analysis, and are converted into two paths of orthogonal baseband signals through direct down-conversion to be sent to the digital processing unit for digital network parameter analysis.
The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Although the present disclosure has been described with reference to specific embodiments, it should be understood that the scope of the present disclosure is not limited thereto, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present disclosure.
Claims (10)
1. A PXIe bus vector signal real-time transceiving module device is characterized in that: including signal frequency conversion receiving element, the direct up-conversion unit of signal and digital processing unit, wherein:
the signal frequency conversion receiving unit is configured to directly amplify, attenuate and condition the radio-frequency signal input by the first port, and then directly down-convert the radio-frequency signal to a zero intermediate-frequency signal, and transmit the signal to the digital processing unit;
the digital processing unit is configured to generate two orthogonal paths of digital baseband signals in a pseudo-random sequence generation and interpolation filtering mode, generate two orthogonal paths of baseband signals and output two orthogonal paths of analog baseband signals to the direct up-conversion unit;
the signal direct up-conversion unit is configured to directly up-convert two paths of baseband orthogonal signals into radio frequency signals and output the radio frequency signals through a second port;
and the signal frequency conversion receiving unit and the signal direct up-conversion unit realize a double-port test function through a multi-stage routing switching coupling mode.
2. The PXIe bus vector signal real-time transceiving module apparatus of claim 1, wherein: the signal frequency conversion receiving unit comprises a local oscillator synthesis circuit, a first coupler, a multi-stage switch switching circuit and a filtering amplification circuit, wherein one end of the local oscillator synthesis circuit is connected with the digital processing unit, the other end of the local oscillator synthesis circuit is connected with the multi-stage switch switching circuit through the filtering amplification circuit, and the multi-stage switch switching circuit is connected with a first port through the first coupler.
3. The PXIe bus vector signal real-time transceiving module apparatus of claim 1, wherein: the direct signal up-conversion unit comprises a local oscillator synthesis circuit, a filtering amplification circuit, a coupler circuit and a multi-stage switch switching circuit, wherein one end of the local oscillator synthesis circuit is connected with the output end of the digital processing unit, the other end of the local oscillator synthesis circuit is connected with the filtering amplification circuit, the filtering amplification circuit is connected with the coupler circuit, and the coupler circuit is connected with the first port and the second port.
4. The PXIe bus vector signal real-time transceiving module device of claim 2 or 3, wherein: the multi-stage switch switching circuit comprises a first switch, a second switch, a third switch and a fourth switch, the first switch, the second switch and the third switch are positioned in the signal frequency conversion receiving unit and are sequentially connected in series, the first switch is connected with the coupler, and the third switch is connected with the filtering amplification circuit; the fourth change-over switch and the second change-over switch share a control end.
5. The device as claimed in claim 3, wherein the PXIe bus vector signal real-time transceiving module device is characterized in that: the coupler circuit comprises a third coupler and a second coupler, the third coupler and the second coupler are connected through a fourth selector switch, the second coupler is connected with the second port, and the third coupler is connected with the filtering amplification circuit.
6. The PXIe bus vector signal real-time transceiving module apparatus of claim 1, wherein: the digital processing unit comprises an ADC acquisition unit, an ADC generation unit, a shared FPGA unit and a filtering conditioning circuit, wherein one end of the ADC acquisition unit is connected with a local oscillation synthesis circuit of the signal frequency conversion receiving unit through the filtering conditioning circuit, the other end of the ADC acquisition unit is connected with the shared FPGA unit, one end of the ADC generation unit is connected with the shared FPGA unit, and the other end of the ADC generation unit is connected with a local oscillation synthesis circuit of the signal direct up-conversion unit through the filtering conditioning circuit.
7. Method of operation of a device according to any of claims 1-6, characterized in that: when the digital signal processing unit works in a vector signal generation mode, the digital processing unit generates two orthogonal paths of digital baseband signals in a pseudo-random sequence generation and interpolation filtering mode, the generated two orthogonal paths of baseband signals are filtered and conditioned and then output two orthogonal paths of analog baseband signals to the direct up-conversion unit, the signal direct up-conversion unit carries out direct orthogonal modulation on the two orthogonal paths of analog baseband signals to directly generate radio frequency modulation signals, and then the radio frequency modulation signals are output by the second port after being subjected to band-pass filtering, amplification and conditioning.
8. Method of operation of a device according to any of claims 1-6, characterized in that: when the digital baseband processing unit works in a vector signal analysis mode, an input signal is filtered, amplified and conditioned in the signal frequency conversion receiving unit and then directly down-converted with the local oscillator synthesis circuit to generate zero intermediate frequency orthogonal two paths of baseband signals, the baseband signals are sent to the digital processing unit to generate two paths of digital baseband signals, then the two paths of digital baseband signals are respectively extracted and filtered, and finally signal analysis is carried out.
9. Method of operation of a device according to any of claims 1-6, characterized in that: in a network parameter analysis mode, when a signal source is at a first port, firstly multiplexing a radio frequency channel and a baseband processing unit for sharing a vector signal, outputting a first port to the signal source through a third coupler, a fourth switch, a second switch, a first switch and a first coupler, and generating an incident signal for network parameter analysis through the third coupler and a third switch; generating a reflected signal of network parameter analysis through the first coupler and the third selector switch; generating a transmission signal for network parameter analysis through the second coupler, the first change-over switch, the second change-over switch and the third change-over switch; the incident signal, the reflected signal and the transmission signal are finally the receiving part of the shared vector signal analysis, and are converted into two paths of orthogonal baseband signals through direct down-conversion to be sent to the digital processing unit for digital network parameter analysis.
10. Method of operation of a device according to any of claims 1-6, characterized in that: in the network parameter analysis mode, when a signal source is at a second port, the signal source is directly generated through vector signal generation, and an incident signal for network parameter analysis is generated through a third coupler and a third selector switch; the second coupler is directly connected to the third selector switch to generate a reflected signal for analyzing the network parameters; generating a transmission signal for network parameter analysis through the first coupler, the first change-over switch, the second change-over switch and the third change-over switch; the incident signal, the reflected signal and the transmission signal are finally the receiving part of the shared vector signal analysis, and are converted into two paths of orthogonal baseband signals through direct down-conversion to be sent to the digital processing unit for digital network parameter analysis.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911046372.7A CN110768682B (en) | 2019-10-30 | 2019-10-30 | PXIe bus vector signal real-time transceiving module device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911046372.7A CN110768682B (en) | 2019-10-30 | 2019-10-30 | PXIe bus vector signal real-time transceiving module device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110768682A true CN110768682A (en) | 2020-02-07 |
| CN110768682B CN110768682B (en) | 2022-01-04 |
Family
ID=69334730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911046372.7A Active CN110768682B (en) | 2019-10-30 | 2019-10-30 | PXIe bus vector signal real-time transceiving module device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110768682B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114531207A (en) * | 2022-03-23 | 2022-05-24 | 电子科技大学 | Multifunctional radio frequency test system |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101207592A (en) * | 2007-12-14 | 2008-06-25 | 北京北方烽火科技有限公司 | Wireless signal receiving and transmitting device in wireless communication system and implementing method thereof |
| CN102497237A (en) * | 2011-12-01 | 2012-06-13 | 北京航天测控技术有限公司 | Radio frequency and microwave synthetic instrument based on PXIe (PCI Extensions for Instrumentation) synthetic instrument architecture |
| CN104320207A (en) * | 2014-10-17 | 2015-01-28 | 中国电子科技集团公司第四十一研究所 | Vector signal analysis device and method |
| CN107196673A (en) * | 2017-06-05 | 2017-09-22 | 中国电子科技集团公司第四十研究所 | A kind of signal analysis device and method based on any variable number intermediate frequency |
| CN108649993A (en) * | 2018-04-11 | 2018-10-12 | 北京航天长征飞行器研究所 | Whether there is or not communication signal transmissions delay measurement systems when plasma for one kind |
| CN109061581A (en) * | 2018-06-04 | 2018-12-21 | 中国电子科技集团公司第四十研究所 | A kind of radar target of linear FM signal is apart from accurate simulator and method |
| CN109884603A (en) * | 2019-03-14 | 2019-06-14 | 中国人民解放军海军航空大学青岛校区 | Radar target simulation system and method based on PXI cabinet |
-
2019
- 2019-10-30 CN CN201911046372.7A patent/CN110768682B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101207592A (en) * | 2007-12-14 | 2008-06-25 | 北京北方烽火科技有限公司 | Wireless signal receiving and transmitting device in wireless communication system and implementing method thereof |
| CN102497237A (en) * | 2011-12-01 | 2012-06-13 | 北京航天测控技术有限公司 | Radio frequency and microwave synthetic instrument based on PXIe (PCI Extensions for Instrumentation) synthetic instrument architecture |
| CN104320207A (en) * | 2014-10-17 | 2015-01-28 | 中国电子科技集团公司第四十一研究所 | Vector signal analysis device and method |
| CN107196673A (en) * | 2017-06-05 | 2017-09-22 | 中国电子科技集团公司第四十研究所 | A kind of signal analysis device and method based on any variable number intermediate frequency |
| CN108649993A (en) * | 2018-04-11 | 2018-10-12 | 北京航天长征飞行器研究所 | Whether there is or not communication signal transmissions delay measurement systems when plasma for one kind |
| CN109061581A (en) * | 2018-06-04 | 2018-12-21 | 中国电子科技集团公司第四十研究所 | A kind of radar target of linear FM signal is apart from accurate simulator and method |
| CN109884603A (en) * | 2019-03-14 | 2019-06-14 | 中国人民解放军海军航空大学青岛校区 | Radar target simulation system and method based on PXI cabinet |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114531207A (en) * | 2022-03-23 | 2022-05-24 | 电子科技大学 | Multifunctional radio frequency test system |
| CN114531207B (en) * | 2022-03-23 | 2022-11-22 | 电子科技大学 | Multifunctional radio frequency test system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110768682B (en) | 2022-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109743069A (en) | A kind of down-conversion device and method receiving analysis instrument for superheterodyne signal | |
| CN104506205A (en) | Radio frequency system of software-defined radio receiver | |
| CN109975772B (en) | Multi-system radar interference performance detection system | |
| CN102437859A (en) | Radio frequency front end anti-interference circuit of wireless communication receiver | |
| CN109462414A (en) | A kind of 18-30GHz front end receiver component | |
| CN210327507U (en) | Frequency conversion assembly for receiving frequency converter | |
| CN110768682B (en) | PXIe bus vector signal real-time transceiving module device and method | |
| CN105577294B (en) | Multifunctional handheld passive intermodulation analyzer | |
| CN111711457A (en) | Method for improving demodulation broadband through multi-channel parallel segmented demodulation mode | |
| CN104092473A (en) | 3-mm waveband receiver and application thereof | |
| CN210444257U (en) | Two-channel S-band down converter | |
| CN103684330A (en) | Medium frequency filter simultaneously applied to wireless receiver and transmitter | |
| CN110365364B (en) | Radio frequency channel device and satellite transponder comprising same | |
| CN208836123U (en) | A kind of 18-30GHz front end receiver component | |
| CN214707702U (en) | Satellite beacon receiver | |
| CN213461730U (en) | Miniaturized low-power consumption receiver | |
| CN110708126B (en) | Broadband integrated vector signal modulation device and method | |
| CN111697977B (en) | Ultra-wideband frequency spectrum monitoring system and method | |
| WO2021234929A1 (en) | Frequency range conversion apparatus | |
| CN102545933A (en) | Two-stage frequency conversion broadband receiver | |
| CN101998459B (en) | Method and device for measuring single-tone field strength | |
| CN210578431U (en) | Down-conversion component for S-band down converter | |
| CN218679063U (en) | X-waveband double-channel transceiving component | |
| CN201387485Y (en) | Compass navigation satellite system receiver module | |
| CN113922882B (en) | High-integration transceiver module based on microwave photons and working method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |