CN113568558B - High-precision multichannel synchronous receiving processing system and method - Google Patents
High-precision multichannel synchronous receiving processing system and method Download PDFInfo
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Abstract
The application provides a high-precision multichannel synchronous receiving processing system and a method thereof, wherein a synchronous source is used for receiving the control of an MCU control module, realizing the switching between a working signal and a synchronous signal, and simultaneously, the system also has a clock power division network for providing a sampling clock for the system; the intermediate frequency data acquisition module is used for sampling the multichannel synchronous signals to obtain a multichannel digital sequence and transmitting the multichannel digital sequence to the intermediate frequency data receiving module in the FPGA; the data caching module is used for caching the sampled data, the caching depth is controlled by the MCU control module, and the delay of the sampling period of integer times is completed; the fractional delay filtering module is used for carrying out fractional time delay on the data sequence which is subjected to integral time delay of the sampling period; the MCU control module is used for completing system control and calculating delay time required by synchronization of each channel, and finally obtaining a high-precision multichannel synchronization sequence. The application realizes multichannel synchronous receiving processing, has high synchronous precision, simple algorithm and flexible design.
Description
Technical Field
The application relates to a multichannel signal processing technology, in particular to a high-precision multichannel synchronous receiving processing system and method.
Background
In modern war, electronic battle occupies a central position, which is a key factor for determining win or lose, and the multichannel synchronous receiving and processing system has wide application in electronic battle. With the rapid development of electronic technology, the electromagnetic environment becomes more and more complex, and a greater challenge is presented to the multichannel synchronous receiving processing system, meanwhile, with the rapid development of semiconductor technology, the continuous progress of manufacturing technology, and various automatic design tools are also developed towards the direction of intelligence. While various automated hardware design tools are available to ensure consistency among channels in designing multichannel synchronous reception processing system hardware. After the hardware design is completed, the simulation tool can also be used for carrying out signal integrity simulation analysis, so that design defects can be found as early as possible, the development efficiency is improved, and the development cost is saved. The improvement of the manufacturing process can also greatly reduce the difference brought in the processing process, and further improve the consistency among channels. However, the multichannel synchronous receiving processing system usually needs to work together under the cooperation of the microwave front end, the stability of the analog device is greatly affected by environmental factors, and in addition, the reference clocks of all channels of the multichannel synchronous receiving processing system may also have jitter, so that the consistency among the channels is difficult to ensure only through hardware design, and the multichannel synchronous receiving processing technology is still a key technology especially important in the receiving processing system with high synchronous precision requirement.
In the field of multichannel synchronous receiving signal processing, in order to ensure complete synchronization among channels, when hardware design is needed, the complete consistency among the channels is ensured, for example, a reference clock line and a signal line need to be designed in equal length. At present, a multichannel synchronous receiving processing system generally synchronizes through the following two methods, namely, inputting standard signals into each channel respectively, and manually delaying and adjusting phase differences among the channels so as to realize synchronization among the channels; 2. the time delay difference of the synchronous clocks of all channels is measured by a high-precision time measuring instrument, and then the synchronous deviation of the data of all channels is regulated by the time delay difference. The two synchronous methods have complex debugging process, low automation degree and high requirements on debugging personnel, and can be completed by skilled technicians with related experience, and the synchronous precision cannot be ensured, so that the two methods are not widely applied.
Disclosure of Invention
The application aims to provide a high-precision multichannel synchronous receiving processing system and a method.
The technical solution for realizing the purpose of the application is as follows: the high-precision multichannel synchronous receiving and processing system comprises a synchronous source, an intermediate frequency data acquisition module and an FPGA, wherein:
the synchronous source is used for outputting a multichannel synchronous signal and a clock signal, the multichannel synchronous signal is output to the multichannel high-speed intermediate frequency data acquisition module, and the clock signal provides a sampling clock for the multichannel high-speed intermediate frequency data acquisition module;
the intermediate frequency data acquisition module is used for sampling the multichannel synchronous signals to obtain a multichannel digital sequence and sending the multichannel digital sequence to the FPGA;
the FPGA comprises an intermediate frequency data receiving module, a data caching module, a fractional delay filtering module and an MCU control module, wherein the intermediate frequency data receiving module is used for receiving sampling data; the data caching module is used for caching the sampling data and is controlled by the MCU control module to finish the delay of the sampling period of integer times; the fractional delay filtering module is used for carrying out fractional time delay on the data sequence which is subjected to integer time delay of the sampling period; the MCU control module is used for controlling the system and calculating delay time required by synchronization of each channel; and obtaining a high-precision multichannel synchronous sequence.
Further, the fractional delay filter is selectedFor delay stepping, a Chebyshev window is adopted for windowing design, and the formed filter coefficients are stored in SDRAM of the FPGA.
Furthermore, the intermediate frequency data acquisition module adopts a high-speed data serial transmission protocol JESD204B to send sampling data to the FPGA; the intermediate frequency data receiving module receives the sampled data by adopting a high-speed data serial protocol JESD 204B.
Further, the specific parameter selection process of the delay of the integer multiple sampling period and the delay of the fractional multiple sampling period is as follows:
1) FPGA receives sampling data x i (N) performing N-point 'radix 2-FFT' operation according to formula (1), and calculating I (in-phase) and Q (quadrature) data I by simultaneous formulas (2), (3) and (4) i [n]And Q i [n]；
Wherein X is i (m) represents the result of the i-th channel N-point FFT operation;
in which x is i (n) represents an i-th channel sample data sequence;
in e -j2πnm/N Is a rotation operator for calculating the FFT;
wherein N represents FFT point number;
FFT calculation is carried out by adopting 'radix 2-FFT', N point data sequences are divided into an odd sequence and an even sequence of N/2 points, a formula (1) is converted into a formula (2), and W is defined N ＝e -j2π/N Representing complex phase angle factors, transforming equation (2) into equation (3), deriving equation (4), i.e., X, from the properties of the twiddle factor i (m+N/2) deriving a post-N/2 term FFT result from the pre-N/2 term FFT result, I i [n]And Q i [n]Respectively X i (m) real and imaginary parts;
1) Based on the obtained I/Q data I i [n]And Q i [n]Extracting the phase of each channel by using cordic algorithmComparing the phases of the channels by adopting an bubbling method, selecting the channel with the largest phase value as a reference channel, and calculating the phase difference between the channels and the reference channel according to the formula (5)>Obtaining the delay difference tau between each channel and the reference channel according to the formula (6) i K is calculated according to the formula (7) i 、P i And M i ；
In the middle ofPhase differences of each channel and a reference channel;
in the middle ofRepresenting the phase of the reference channel;
in the middle ofRepresenting the phase of the i-th channel;
wherein i represents the number of channels;
wherein f represents the frequency of the synchronous signal output by the synchronous source;
τ in i Representing the delay of the ith channel and the reference channel;
k in i Representing an integer multiple of the sampling period;
p in the formula i The fractional multiple of the sampling period is represented, and the value range is 0 and 1;
m in the formula i Representing the delay times of the fractional delay filter;
t in s Representing the sampling period.
A high-precision multichannel synchronous receiving processing method is based on the high-precision multichannel synchronous receiving processing system, and realizes high-precision multichannel synchronous receiving processing.
Compared with the prior art, the application has the remarkable advantages that: (1) The method for multi-channel synchronous receiving processing used by the application has high synchronous precision and simple algorithm, and only needs to carry out the movement of integer times of one sampling period and M timesA shift of a fractional multiple of the sampling period; (2) The method for high-precision multichannel synchronous receiving and processing used by the application has the advantages that the FPGA resource consumption is low, only one fractional delay filter is needed to be designed, the automation degree is high, and the complex manual debugging process is overcome; (3) The application has flexible design, and can design the fractional delay filter according to the synchronous precision requirement of the multichannel high-speed data acquisition and processing system, thereby achieving the aim of high-precision synchronization.
Drawings
FIG. 1 is a block diagram of an implementation of a high precision multi-channel synchronous reception processing system of the present application.
Fig. 2 is a flow chart of the N-point "radix 2-FFT" algorithm of the present application.
FIG. 3 is a flow chart of the inverted sequence of data according to the present application.
Fig. 4 is a flow chart of a high-precision multichannel synchronous receiving processing method of the application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The application discloses a high-precision multichannel synchronous receiving and processing system, which is realized by a block diagram shown in figure 1 and comprises a synchronous source, an intermediate frequency data acquisition module and an FPGA, wherein:
the synchronous source is used for outputting a multichannel synchronous signal and a clock signal, the multichannel synchronous signal is output to the multichannel high-speed intermediate frequency data acquisition module, and the clock signal provides a sampling clock for the multichannel high-speed intermediate frequency data acquisition module;
the intermediate frequency data acquisition module is used for sampling the multichannel synchronous signals to obtain a multichannel digital sequence, and transmitting the sampled data to the FPGA by adopting a high-speed data serial transmission protocol JESD 204B;
the FPGA comprises an intermediate frequency data receiving module, a data caching module and a fractional delay filtering module, wherein the intermediate frequency data receiving module receives sampling data by adopting a high-speed data serial protocol JESD 204B; the data caching module is used for caching the sampling data and is controlled by the MCU control module to finish the time delay of integer times of the sampling period; the fractional delay filtering module is used for carrying out fractional time delay on the data sequence which is subjected to integer time delay of the sampling period; the MCU control module is used for controlling the system and calculating delay time required by synchronization of each channel; and obtaining a high-precision multichannel synchronous sequence.
The specific implementation mode is as follows:
the first step, selecting according to the synchronous precision requirement of a high-precision multichannel synchronous receiving processing systemFor the step of the fractional delay filter, the fractional delay filter is designed according to the design principle of the fractional delay filter, wherein T is as follows s The sampling period is represented, D is a constant, and the value of the D is determined by the synchronization precision. The application adopts Chebyshev window to carry out windowing treatment to design a fractional delay filter, thus obtaining a causally stable fractional delay filterAnd the wave device stores the fractional delay filter coefficients into SDRAM of the FPGA.
Secondly, after the high-precision multichannel synchronous receiving processing system is started, the MCU control module controls the working state to be in a synchronous training mode, and the synchronous source switches the radio frequency switch to the synchronous source, as shown by SF in figure 1 1 、SF 2 …SF i The access, the synchronous source produces multichannel synchronizing signal and clock signal, multichannel synchronizing signal output multichannel high-speed intermediate frequency data acquisition module, the clock signal provides sampling clock for it.
Thirdly, initializing and setting an intermediate frequency data acquisition module by the MCU control module, and sampling the multichannel synchronous signals to obtain a multichannel digital sequence x i (n) the intermediate frequency data acquisition module adopts a high-speed data serial transmission protocol JESD204B to send the sampling data to the FPGA.
Fourth, the FPGA adopts a high-speed data serial protocol JESD204B to receive the sampling data x i And (n) caching the sampled data through a data caching module, wherein the data delay time is controlled by the MCU control module.
Fifth, the MCU control module obtains sampling data x according to the fourth step i (N) performing N-point 'radix 2-FFT' operation according to formula (1), and calculating I (in-phase) and Q (quadrature) data I by simultaneous formulas (2), (3) and (4) i [n]And Q i [n]。
Wherein X is i (m) represents the result of the i-th channel N-point FFT operation;
in which x is i (n) represents an i-th channel sample data sequence;
in e -j2πnm/N Is a rotation operator for calculating the FFT;
wherein N represents FFT point number;
the application adopts 'radix 2-FFT' to carry out FFT calculation, divides N-point data sequence into an odd sequence and an even sequence of N/2 points, and the formula (1) can be converted into the formula (2) to define W N ＝e -j2π/N Representing complex phase angle factors, transforming equation (2) into equation (3), from the nature of the twiddle factor, equation (4), i.e. X, can be derived i (m+N/2) the FFT result of the post-N/2 term can be deduced from the FFT result of the previous N/2 term, the operation resource can be saved, I i [n]And Q i [n]Respectively X i The real and imaginary parts of (m), the "radix-2-FFT" algorithm flow chart is shown in FIG. 2, and the data sequence inverted sequence flow chart is shown in FIG. 3.
Sixth, MCU control module according to the I/Q data I obtained in fifth step i [n]And Q i [n]Extracting the phase of each channel by using cordic algorithmComparing the phases of the channels by adopting an bubbling method, selecting the channel with the largest phase value as a reference channel, and calculating the phase difference between the channels and the reference channel according to the formula (5)>Obtaining the delay difference tau between each channel and the reference channel according to the formula (6) i K is calculated according to the formula (7) i 、P i And M i 。
In the middle ofPhase differences of each channel and a reference channel;
in the middle ofRepresenting the phase of the reference channel;
in the middle ofRepresenting the phase of the i-th channel;
wherein i represents the number of channels;
wherein f represents the frequency of the synchronous signal output by the synchronous source;
τ in i Representing the delay of the ith channel and the reference channel;
k in i Representing an integer multiple of the sampling period;
p in the formula i The fractional multiple of the sampling period is represented, and the value range is 0 and 1;
m in the formula i Representing the delay times of the fractional delay filter;
t in s Representing a sampling period;
seventh step, K is obtained according to the sixth step i The MCU control module controls K corresponding to movement of each channel data buffer module i Point, the point number of integer times of the sampling period is moved, and a moved data sequence x is obtained i (n-k i )。
Eighth step, P obtained in the sixth step i WhereinThe MCU control module controls the seventh step to be sampled every weekDelayed data sequence x with integer times of period i (n-k i ) Proceeding with M i Second->The time delay of the fractional multiple sampling period is completed, and the movement of the fractional multiple sampling period is completed, so that a data sequence +.>
Ninth, after the synchronous sequence is carried out on the sampling data through the steps, the data sequence of each channel is obtainedNamely a high-precision multichannel synchronous sequence, judging whether the synchronous data sequence meets the synchronous precision, IF so, the MCU control module controls the synchronous source to switch to a working state, such as the IF in figure 1 1 、IF 2 …IF i A passage; otherwise, the step 5 is carried out again, if the number of times of synchronization exceeds a certain number of times, the synchronization is still not satisfied, and the synchronization is failed.
A flow chart of a high-precision multichannel synchronous receiving processing system and method is shown in FIG. 4.
Thus, the process of the high-precision multichannel synchronous receiving processing system and method is completed.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (5)
1. The high-precision multichannel synchronous receiving and processing system is characterized by comprising a synchronous source, an intermediate frequency data acquisition module and an FPGA, wherein:
the synchronous source is used for outputting a multichannel synchronous signal and a clock signal, the multichannel synchronous signal is output to the multichannel high-speed intermediate frequency data acquisition module, and the clock signal provides a sampling clock for the multichannel high-speed intermediate frequency data acquisition module;
the intermediate frequency data acquisition module is used for sampling the multichannel synchronous signals to obtain a multichannel digital sequence and sending the multichannel digital sequence to the FPGA;
the FPGA comprises an intermediate frequency data receiving module, a data caching module, a fractional delay filtering module and an MCU control module, wherein the intermediate frequency data receiving module is used for receiving sampling data; the data caching module is used for caching the sampling data and is controlled by the MCU control module to finish the delay of the sampling period of integer times; the fractional delay filtering module is used for carrying out fractional time delay on the data sequence which is subjected to integer time delay of the sampling period; the MCU control module is used for controlling the system and calculating delay time required by synchronization of each channel to obtain a high-precision multichannel synchronization sequence.
2. The high-precision multichannel synchronous receiving processing system according to claim 1, wherein the fractional delay filtering module selectsFor delay stepping, a Chebyshev window windowing design is adopted, and the formed filter coefficients are stored in SDRAM of the FPGA.
3. The high-precision multichannel synchronous receiving processing system according to claim 1, wherein the intermediate frequency data acquisition module adopts a high-speed data serial transmission protocol JESD204B to send sampling data to the FPGA; the intermediate frequency data receiving module receives the sampled data by adopting a high-speed data serial protocol JESD 204B.
4. The high-precision multichannel synchronous receiving processing system according to claim 1, wherein the delay of the integer multiple sampling period and the delay of the fractional multiple sampling period have the following specific parameter selection processes:
1) FPGA receives sampling data x i (N) performing N-point "radix 2-FFT" operation according to formula (1), and calculating I, Q data I by simultaneous equations (2), (3) and (4) i [n]And Q i [n]；
Wherein X is i (m) represents the result of the i-th channel N-point FFT operation;
in which x is i (n) represents an i-th channel sample data sequence;
in e -j2πnm/N Is a rotation operator for calculating the FFT;
wherein N represents FFT point number;
FFT calculation is carried out by adopting 'radix 2-FFT', N point data sequences are divided into an odd sequence and an even sequence of N/2 points, a formula (1) is converted into a formula (2), and W is defined N ＝e -j2π/N Representing complex phase angle factors, transforming equation (2) into equation (3), deriving equation (4), i.e., X, from the properties of the twiddle factor i (m+N/2) deriving a post-N/2 term FFT result from the pre-N/2 term FFT result, I i [n]And Q i [n]Respectively X i (m) real and imaginary parts;
1) Based on the obtained I/Q data I i [n]And Q i [n]Extracting the phase of each channel by using cordic algorithmComparing the phases of the channels by adopting an bubbling method, selecting the channel with the largest phase value as a reference channel, and calculating the phase difference between the channels and the reference channel according to the formula (5)>Obtaining the delay difference tau between each channel and the reference channel according to the formula (6) i K is calculated according to the formula (7) i 、P i And M i ；
In the middle ofPhase differences of each channel and a reference channel;
in the middle ofRepresenting the phase of the reference channel;
in the middle ofRepresenting the phase of the i-th channel;
wherein i represents the number of channels;
wherein f represents the frequency of the synchronous signal output by the synchronous source;
τ in i Representing the delay of the ith channel and the reference channel;
k in i Representing an integer multiple of the sampling period;
p in the formula i The fractional multiple of the sampling period is represented, and the value range is 0 and 1;
m in the formula i Representing the delay times of the fractional delay filtering module;
t in s Representing the sampling period.
5. A high-precision multichannel synchronous receiving processing method, which is characterized in that the high-precision multichannel synchronous receiving processing is realized based on the high-precision multichannel synchronous receiving processing system according to any one of claims 1-4.
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