CN114675790B - Self-correcting method for synchronous data storage of multichannel parallel sampling system - Google Patents
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Abstract
The invention discloses a self-correcting method for synchronous data storage of a multichannel parallel sampling system, and belongs to the technical field of signal processing. Compared with the existing storage synchronization method, the method has the advantages that the sequential increasing state monitoring bits are added before the sampling data are synchronously received, so that the synchronous storage of the multi-channel sampling data is realized, and the test data generated by the ADC is not required to be relied on. The ADC can work in a sampling mode, the difference of the arrival time of the write control instruction between channels is determined by comparing the state monitoring bit of the first read data of each path of correction FIFO with a reference channel, and the synchronous storage effect of the data is finally realized by combining real-time correction of a delay correction module. The working mode of the parallel sampling system is controlled to be switched back and forth between the correction mode and the storage mode by customizing the time interval of the timer, so that the delay module is automatically adjusted according to the change of external environmental factors such as temperature and humidity, aging deformation of the board card and the like, and the effect of automatically correcting write enable synchronization is finally realized.
Description
Technical Field
The invention belongs to the technical field of signal processing, and particularly relates to a self-correcting method for synchronous storage of data of a multichannel parallel sampling system.
Background
With the rapid development of electronic technology, the frequency band and complexity of signals to be processed in a circuit system are continuously improved, and a parallel sampling architecture (shown in fig. 1) of an ADC sampling card, a slave FPGA memory card and a master FPGA control card is concerned in the fields of high-speed signal processing and the like. The multiplied increase of data transmission channels and data storage capacity puts more severe requirements on the sampling speed, precision and processing real-time performance of the sampling system. In order to realize stable system operation under multiple channels, ensure sequential transmission and splicing recombination of sampling data and reduce storage pressure, synchronous data storage becomes an urgent problem to be solved. In the multichannel parallel sampling system, data are synchronously acquired and sent by an ADC (analog to digital converter) sampling card, a storage control instruction is sent to a slave FPGA through a master control FPGA, and the data are correctly received and stored in the slave FPGA. However, since the sampled data and the enable signal for controlling the storage are transmitted across the LVDS interface type FMC connection daughter board, it is inevitable that data storage between channels is asynchronous due to routing delay and signal metastable state. Meanwhile, the temperature, the humidity, the vibration and the like in the external environment are also important influence factors of board card deformation, so that the storage starting points of all paths are not unified, and the subsequent data cannot be correctly spliced in the main control FPGA.
At present, two types of correction methods for realizing synchronous storage of multi-channel parallel data are mainly used, one is based on comparison of storage results of test data among channels in an ADC (analog to digital converter) test mode, and an optimal delay value for synchronizing write enable of each channel is calculated, so that synchronous storage correction among the channels is realized; the other is an indirect mode of directly putting the key on the last data splicing link, discarding the data which are stored asynchronously during subsequent splicing and only keeping the corresponding synchronous data bits for splicing. Both methods require the ADC to operate in a test mode, and complete synchronous storage and calibration using custom test data values or by using the characteristics of the test data, such as periodicity. However, the number of ADC chips capable of generating test data is small, and the delay obtained from the test data cannot be automatically adjusted according to the change of environmental factors such as temperature and vibration, and the real-time performance is poor. The second method does not fundamentally solve the problem of unsynchronization of the storage control enable signal, and with the increase of the number of channels, unnecessary waste of storage resources inside the FPGA and increase of storage time are caused. Therefore, in the multi-channel parallel sampling system, the correction technology of storage synchronization is the key for realizing the stable coordination work of the system and reducing the final data splicing error rate. An automatic calibration method for synchronous storage between channels is one of the key points to be researched urgently at present.
Disclosure of Invention
Aiming at the defects and improvement requirements of the prior art, the invention provides a self-correcting method for synchronous data storage of a multichannel parallel sampling system based on a parallel sampling system of an ADC (analog to digital converter) sampling card, a slave FPGA storage card and a master FPGA control card framework on the premise that analog signals to be sampled are synchronously sampled by the ADC and synchronously received by a slave FPGA board card, and aims to solve the technical problem that the time for reaching each channel of a slave FPGA is not synchronous due to factors such as PCB (printed circuit board) cross-board transmission, path routing delay under different channels and the like of a write control instruction sent by the master FPGA.
In order to achieve the above object, the present invention provides a self-calibration method for synchronous data storage of a multichannel parallel sampling system, which is applied to a parallel sampling system constructed by an ADC sampling card, a slave FPGA memory card, and a master FPGA control card, wherein the master FPGA sends an asynchronous write control instruction to each channel of the slave FPGA to instruct the slave FPGA to start storing the sampling data sent by the ADC, and the method is characterized by comprising the following steps: s1, configuring the ADC to work in a sampling mode, and completing synchronous sampling of each channel and synchronous receiving of sampled data through the slave FPGA; s2, setting the same initial delay of the opening of the write control enable for each channel, and adding state monitoring bits with increasing sequence before synchronously received sampling data as a new data format of the correction FIFO; s3, selecting any channel as a reference channel, and the rest channels as channels to be corrected, and updating the delay of the write control enable opening of the channel to be corrected according to the state monitoring bit difference of the first read data of the correction FIFO of the channel to be corrected and the reference channel; and S4, after all channels to be corrected complete the delay updating of the opening of the write control enable, opening the storage FIFO write enable after the asynchronous write control command sent by the main FPGA carries out corresponding delay through each channel, and realizing the synchronous storage of the sampling data of each channel of the slave FPGA.
Further, the method further comprises: s5, after the preset time, jumping to S3.
Further, in S5, the setting of the preset time is implemented by customizing a time interval of the timer according to the intensity of the external environment change.
Further, in the S3, the channel to be correctediTime delay for write control enable on after updatet i = t 0 +△S i *t u Wherein, in the step (A),t 0 for initial delay, ΔS i For the channel to be correctediAnd the status monitor bit of the first read data of the calibration FIFO of the reference channel,t u is a unit of time.
Furthermore, the storage depth and the input/output data bit width of each path of correction FIFO are the same, and the data reading conditions are consistent; the storage depth and the input and output data bit width of each path of storage FIFO are the same, and the data reading conditions are consistent.
Further, in S3, the master FPGA is selected to send the write control instruction to the longest channel of the slave FPGA transmission line as the reference channel.
In another aspect of the present invention, a self-calibration system for synchronously storing data of a multi-channel parallel sampling system is provided, which is applied to a parallel sampling system configured by an ADC sampling card, a slave FPGA memory card, and a master FPGA control card, where the master FPGA sends an asynchronous write control instruction to each channel of the slave FPGA to instruct the slave FPGA to start storing the sampling data sent by the ADC, and the self-calibration system is characterized by comprising: a computer-readable storage medium and a processor; the computer-readable storage medium is used for storing executable instructions; the processor is used for reading the executable instructions stored in the computer readable storage medium and executing the self-correcting method for synchronously storing the data of the multi-channel parallel sampling system.
Generally, by the above technical solution conceived by the present invention, the following beneficial effects can be obtained:
(1) compared with the existing storage synchronization method, the method has the advantages that the sequential increasing state monitoring bits are added before the sampling data are synchronously received, so that the synchronous storage of the multi-channel sampling data is realized, and the test data generated by the ADC is not required to be relied on. The ADC can work in a sampling mode, the difference of the arrival time of the write control instruction between channels is determined by comparing the state monitoring bit of the first read data of each path of correction FIFO with a reference channel, and the synchronous storage effect of the data is finally realized by combining real-time correction of a delay correction module.
(2) Compared with other storage synchronization methods, the method can track the complex situation of the environment in real time and correct the write enable in a self-adaptive manner. The working mode of the parallel sampling system is controlled to be switched back and forth between the correction mode and the storage mode through the time interval of the self-defined timer, so that the delay module is automatically adjusted according to the change of external environment factors such as temperature and humidity, aging deformation of the board card and the like, and the effect of automatically correcting, writing and enabling synchronization is finally achieved.
(3) Compared with other storage synchronization methods, the method does not introduce other redundant control bits into the sampled data in the storage mode, improves the utilization rate of the storage space of the storage FIFO, and facilitates the correct splicing of the sampled data. The self-defined state monitoring bit is redundant to the sampling data, and after the system finishes write enable correction, the state monitoring bit can not be introduced any more, and finally the effect that the storage FIFO is effective sampling data is achieved.
Drawings
Fig. 1 is a general technical scheme diagram of a self-correcting method for synchronous storage of data of a multi-channel parallel sampling system.
FIG. 2 is a schematic diagram of data storage errors of channels under asynchronous control of write control instructions of the main control FPGA.
Fig. 3 is a schematic flow chart of a self-calibration method for synchronous storage of data in a multi-channel parallel sampling system according to the present invention.
Fig. 4 is a second schematic flow chart of the self-calibration method for synchronous data storage of a multi-channel parallel sampling system according to the present invention.
Fig. 5 is a schematic block diagram of synchronous storage of a parallel sampling system according to an embodiment of the present invention.
FIG. 6 shows the second embodiment of the present inventioniA schematic diagram of a state monitoring bit is introduced before way sampling data.
Fig. 7 is a schematic diagram of correct data storage of each channel after the write control instruction of the main control FPGA is corrected.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a general technical scheme diagram of a self-calibration method for synchronous storage of data in a multi-channel parallel sampling system is shown. The method comprises the steps of firstly selecting a channel 1 as a reference channel, automatically adjusting a delay module with synchronous write control instructions of other channels by introducing a status bit and continuously switching working modes by using a timer until the real-time adjustment of the stored data dislocation caused by the asynchronous write control instructions provided by a main control FPGA to an FIFO is completed, thereby finally realizing the correct splicing and recombination of the data of a sampling system and improving the stability of the system.
In this embodiment, the ADC is of the type ADC12DL3200, the slave FPGA memory card is of the KINTEX 7 series FPGA, and the master FPGA control card is of the Virtex 7 series FPGA. And the sampling data synchronously obtained by each ADC chip is synchronously received and stored by one FPGA under the limitation of the IO resources and the device cost of the FPGA. However, since the storage FPGAs are independent from each other and the write control signal sent by the main control FPGA is transmitted across boards, the phenomenon that the data storage starting points between the channels are not synchronized as shown in fig. 2 is inevitable. In order to realize that the sampled data can be correctly spliced and recombined in the main control FPGA, the storage starting points of all channels of the FPGA need to be the same, namely, the storage control signals provided by the main control FPGA need to be synchronously corrected.
Referring to fig. 3, in combination with fig. 4 and fig. 5, the present invention provides a self-calibration method for synchronous data storage of a multi-channel parallel sampling system, including the following steps:
and S1, configuring the ADC to work in a sampling mode, and completing synchronous sampling of each channel and synchronous receiving of sampled data through the slave FPGA.
In this embodiment, the USB interface is used to configure the ADC to operate in the sampling mode, and synchronous sampling of each channel and synchronous reception of sampled data are completed through the slave FPGA. After analog-to-digital conversion of the analog signal by the ADC acquisition card, 12-bit sampling differential DATA DATA [11:0] +/-, and a differential channel associated clock DCLK +/-, which is used for synchronously receiving and storing DATA from the FPGA, can be obtained.
S2, setting the same initial delay of the write control enable on for each channel, and adding sequentially increasing status monitoring bits before the synchronously received sample data as a new data format of the correction FIFO.
In this embodiment, in order to avoid the negative value after the delay updating, the initial delay is set for the delay correction modules of M channels of the slave FPGAt 0 . After receiving an asynchronous write control signal FIFO _ wr _ rdy =1 from the FPGA board, the slave FPGA storage FIFO can be opened only by delaying through the delay correction module due to asynchronous receiving time.
As shown in FIG. 6, in the second placeiSampled DATA received synchronouslyj i [11:0]Add the status monitoring bit S with 4bit sequence increasing before +/-Sj i [3:0]+/- (i.e. S0 i =0000B、S1 i =0001B、S2 i =0002B, …), constituting a new data format R stored in a correction FIFOj i [15:0]。DATAj i Denotes the firstiRoad firstjA sample data, Sj i Is shown asiRoad firstjIndividual state monitoring bit, Rj i Is shown asiRoad firstjAnd (6) new data.
And S3, selecting any channel as a reference channel, using the other channels as channels to be corrected, and updating the delay of the write control enabling opening of the channel to be corrected by using the state monitoring bit difference of the first read data of the correction FIFO of the channel to be corrected and the reference channel.
In this embodiment, since the storage depths of the correction FIFOs of the channels are the same, any channel is selected as the reference channel, for example, the channel 1 is used as the reference channel, and whether the state monitoring bits of the first read data of the correction FIFOs of the other channels and the reference channel are equal is determined by comparing, so as to determine whether the write control signal of the channel is synchronous with the reference channel. The status monitoring bits are unequal, the output signal FIFO _ rd _ rdy =0, and the difference delta between the status bits of the two channels is obtainedS i = S i - S 1 ，S i Indicating a channeliThe status monitor bit of the first read data of the correction FIFO,S 1 a state monitoring bit of the first read data of the correction FIFO representing the reference channel; otherwise, the status bits are equal, and the output signal FIFO _ rd _ rdy =1, which indicates that the channel has communicated the write control signal to the referenceThe tracks are synchronized.
Difference Δ of state monitoring bitsS i Real-time feedback to the delay correction module, and updating the delay of the channel write control signal tot i = t 0 +△S i * t u Wherein, in the step (A),t 0 in order to be the initial delay time,t u the unit of time is the output signal FIFO rd rdy =1, which indicates that the channel write control command is synchronized and a memory synchronization self-correction is completed.
And S4, after all channels to be corrected complete the delay updating of the opening of the write control enable, opening the storage FIFO write enable after the asynchronous write control command sent by the main FPGA carries out corresponding delay through each channel, and realizing the synchronous storage of the sampling data of each channel of the slave FPGA.
In this embodiment, after all the M channels output FIFO _ rd _ rdy =1, the system is operated in the storage mode by using the operating mode switching module. And the write control instruction sent by the main control FPGA passes through the updated delay correction module, and the storage FIFO write enable is opened. Because the storage depth of each path of storage FIFO is the same as the bit width conversion of the input and output data, the synchronous storage of the sampling data can be realized under the same read-write control condition. The effect of storing the sampled data in the storage mode is shown in fig. 7.
Further, in order to track the write enable of the adaptive correction of the complex situation of the environment in real time, the self-correction method for the synchronous storage of the data of the multi-channel parallel sampling system provided by the invention further comprises the following steps:
s5, after the preset time, jumping to S3.
In this embodiment, the timer is used to control the system to continuously switch from the storage mode to the calibration mode, track the environmental change, and implement the periodic self-calibration. The time interval of the timer is customized according to the change condition of the influence factors in the external environment so as to adapt to the condition that the write control signals are not synchronous caused by the influence factors such as temperature and humidity, vibration, board card deformation and the like in the environment.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A self-correcting method for synchronous storage of data of a multichannel parallel sampling system is applied to a parallel sampling system which is constructed by an ADC (analog to digital converter) sampling card, a slave FPGA (field programmable gate array) storage card and a master FPGA control card, wherein the master FPGA sends asynchronous write control instructions to channels of the slave FPGA to instruct the slave FPGA to start to store the sampling data sent by the ADC, and the self-correcting method is characterized by comprising the following steps of:
s1, configuring the ADC to work in a sampling mode, and completing synchronous sampling of each channel and synchronous receiving of sampling data through the slave FPGA;
s2, setting the same initial delay of the write control enable opening for each channel, and adding a state monitoring bit with ascending sequence before synchronously received sampling data as a new data format of the correction FIFO;
s3, selecting any channel as a reference channel, and the rest channels as channels to be corrected, and updating the delay of the write control enable opening of the channel to be corrected according to the state monitoring bit difference of the first read data of the correction FIFO of the channel to be corrected and the reference channel; wherein the channel to be correctediTime delay for write control enable on after updatet i = t 0 +△S i *t u Wherein, in the step (A),t 0 for initial delay, ΔS i For the passage to be correctediAnd the status monitor bit of the first read data of the calibration FIFO of the reference channel,t u is a unit of time;
and S4, after all channels to be corrected complete the delay updating of the opening of the write control enable, opening the storage FIFO write enable after the asynchronous write control command sent by the main FPGA carries out corresponding delay through each channel, and realizing the synchronous storage of the sampling data of each channel of the slave FPGA.
2. The self-correcting method for synchronous storage of data in a multi-channel parallel sampling system according to claim 1, further comprising:
s5, after the preset time, jumping to S3.
3. The self-calibration method for synchronous data storage in a multichannel parallel sampling system according to claim 2, wherein in S5, the setting of the preset time is implemented by customizing the time interval of the timer according to the intensity of the external environment change.
4. The self-correcting method for synchronous data storage of a multichannel parallel sampling system according to claim 1, characterized in that the storage depth and the input/output data bit width of each path of correction FIFO are the same, and the data reading conditions are consistent; the storage depth and the input/output data bit width of each path of storage FIFO are the same, and the data reading conditions are consistent.
5. The self-correcting method for the synchronous storage of the data of the multi-channel parallel sampling system according to claim 1, wherein in the step S3, the channel with the longest transmission line is selected as a reference channel for the master FPGA to send the write control command to the slave FPGA.
6. The utility model provides a self-correcting system of multichannel parallel sampling system data synchronous storage, is applied to ADC sampling card + from the parallel sampling system of FPGA storage card + main FPGA control card framework, and the asynchronous control instruction that writes is sent to each passageway of follow FPGA to main FPGA, and the order begins from FPGA to store the sampling data that the ADC sent, its characterized in that includes: a computer-readable storage medium and a processor;
the computer readable storage medium is used for storing executable instructions;
the processor is used for reading executable instructions stored in the computer readable storage medium and executing the self-correcting method for synchronous data storage of the multichannel parallel sampling system according to any one of claims 1 to 5.
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