CN110572294A - SSM information processing time delay testing method - Google Patents
SSM information processing time delay testing method Download PDFInfo
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- CN110572294A CN110572294A CN201810583752.3A CN201810583752A CN110572294A CN 110572294 A CN110572294 A CN 110572294A CN 201810583752 A CN201810583752 A CN 201810583752A CN 110572294 A CN110572294 A CN 110572294A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0852—Delays
Abstract
the application provides a method for testing SSM information processing time delay, which comprises the following steps: the first test equipment simultaneously sends synchronous Ethernet signals on the first port and the second port according to the configured SSM values of the first time to the fourth time; when the tested device receives the synchronous Ethernet signal sent by the first test device through the third port and the fourth port, the tested device responds to the synchronous Ethernet message to the first test device through the fourth port according to the configured response rule; the first test equipment calculates the corresponding time delay by recording the switching delay time, the non-switching delay time and the holding delay time; and determining whether the recorded time difference is in a numerical range corresponding to the expected time delay value to determine whether the corresponding time delay meets the time delay regulation. The method can improve the testing efficiency and reduce human errors.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a method for testing information processing time delay of Synchronous Status Message (SSM).
Background
SSM is a code used by synchronous networks to represent the quality level of a clock. Currently, ITU-T specifies that four bits, namely the Synchronization Status Message Byte (SSMB), are used for encoding.
Table 1 shows the SSM codes and their usage priorities, defined by ITU-T, applicable to our country for distinguishing different clock quality level information.
TABLE 1
in a BITS device, the SSM is transmitted over a certain bit of the first time slot (TS0) of a 2Mb/s clock signal; in an SDH transport network, SSM is transported by the lower four bits of S1 bytes in the SDH section overhead; in synchronous Ethernet, SSM is transmitted via specialized slow protocol Messaging Channel (ESMC) messages. The transmitting device will decide the clock distribution and tracking path according to the SSM information it receives at different clock ports and the preset priority of the ports, and prevent the timing loop from occurring.
YD/T2551-2013 technical requirement of frequency synchronization network based on packet network has the following requirements on SSM information processing time delay of transmission equipment.
(1) And information holding delay THM
When the SEC/EEC (SDH Equipment Clock/Ethernet Equipment Clock) loses the input timing reference and no other available timing reference exists, the SEC/EEC enters a holding state, the SSM quality grade output after a delay is changed into holding code, and the delay time T isHM500-.
(2) Non-switching information delay TNSM
When the SSM quality grade selected by SEC/EEC changes and does not cause reference switching, the SSM quality grade output after a delay tracks the change, and the delay time TNSMIs 0-200 ms.
(3) Time delay T for switching informationSM
When SEC/EEC selects new fixedWhen time reference is carried out, the SSM quality grade output after a time delay is changed into the SSM quality grade of the newly selected timing reference, and the time delay T isSMIs 180-500 ms.
(4) and the timing switching time delay of the chain network with 20 SEC/EEC network elements is less than 15.6 s.
YD/T2551 and 2013 technical requirement of a frequency synchronization network based on a packet network only provide index requirements for SSM information processing delay of transmission equipment, a test method is not specified, and no other standard is specified at present.
In actual test, a tester can flexibly set up different test environments according to personal understanding and the conditions of instrument capability, equipment and instrument interfaces, and test the retention information delay, non-switching information delay and switching information delay of a single network element one by one without a uniform test method. The typical chain network with 20 SEC/EEC network elements is not easy to be provided, so the timing switching delay under this condition is less to test.
The existing manual testing method has the following defects:
1. The corresponding requirements are tested one by one, different test environments need to be built for many times, the instrument is set for many times, the setting is complex, the time difference between manual measurement and calculation is poor, and errors are easy to occur.
2. Each test result needs a tester to manually interpret according to the data returned by the instrument and the tested device, and the tester must have rich test experience.
3. because it is not easy to have a typical chain network with 20 SEC/EEC network elements, the timing switch delay under this condition is rarely tested, and there is no alternative.
disclosure of Invention
In view of this, the present application provides a method for testing SSM information processing delay, which can improve testing efficiency and reduce human errors.
In order to solve the technical problem, the technical scheme of the application is realized as follows:
A testing method for SSM information processing time delay comprises the following steps:
Configuring first configuration information: when the synchronous Ethernet signal is sent for the first time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; when the synchronous Ethernet signal is sent for the second time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; when the synchronous Ethernet signal is sent for the third time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; when the synchronous Ethernet signal is sent for the fourth time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; desired TNSM、TSMAnd THMThe value of (d) corresponds to a numerical range;
the first test equipment simultaneously sends synchronous Ethernet signals on the first port and the second port according to the configured SSM values of the first time to the fourth time;
When the tested device receives the synchronous Ethernet signal sent by the first test device through the third port and the fourth port, the tested device responds to the synchronous Ethernet message to the first test device through the fourth port according to the configured response rule;
When the first test equipment sends the synchronous signal through the first port for the second time, the sending time is recorded as T21when the synchronous signal is transmitted through the first port for the third time, the transmission time is recorded as T31(ii) a When the synchronous signal is transmitted through the second port for the fourth time, the transmission time is recorded as T42(ii) a When the synchronous signal sent by the tested device is received through the second port for the second time, the sending time is recorded as T23(ii) a When the synchronous signal sent by the tested device is received through the second port for the third time, the sending time is recorded as T33(ii) a When the synchronous signal sent by the tested device is received through the second port for the fourth time, the sending time is recorded as T43；
The first test equipment determines T23And T21Whether the difference in (b) is at the desired TNSMIf yes, determining that the non-switching information delay accords with SSM information processing delay regulation; otherwise, determining that the non-switching information delay does not accord with SSM information processing delay regulation, and displaying;
First test equipment determinationT33and T31Whether the difference in (b) is at the desired TSMA numerical range corresponding to the value; if yes, determining that the switching information delay accords with SSM information processing delay regulation; otherwise, determining that the switching information delay does not accord with SSM information processing delay regulation, and displaying;
The first test equipment determines T43And T42Whether the difference in (b) is at the desired THMA numerical range corresponding to the value; if yes, determining that the information delay accords with SSM information processing delay regulation; otherwise, determining that the holding information delay does not accord with SSM information processing delay regulation, and displaying.
according to the above technical scheme, in the present application, a test for keeping whether the information delay, the non-switching information delay, and the switching information delay meet the requirements of the SSM information processing delay is completed through one automatic test. The scheme can improve the testing efficiency and reduce human errors.
Drawings
FIG. 1 is a schematic diagram of SSM information processing latency testing in an embodiment of the present application;
Fig. 2 is a schematic diagram of a testing process of SSM information processing delay in the embodiment of the present application;
fig. 3 is a schematic diagram of a test of the timing switching delay of a chain network having n EEC network elements.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly apparent, the technical solutions of the present invention are described in detail below with reference to the accompanying drawings and examples.
The embodiment of the application provides a method for testing SSM information processing time delay, which completes the test of whether the information time delay, the non-switching information time delay and the switching information time delay meet the requirement of SSM information processing time delay through one-time automatic test. The scheme can improve the testing efficiency and reduce human errors.
The test for maintaining the information delay, the non-switching information delay, and the switching information delay is applicable to one test device and one tested device, and the test device is denoted as a first test device when described below.
Referring to fig. 1, fig. 1 is a schematic diagram of testing the processing delay of the SSM information in the embodiment of the present application. The first test equipment in fig. 1 is provided with 2 isochronous ethernet ports (a first port and a second port). The device under test is provided with two synchronous ethernet ports (a third port and a fourth port).
The ports referred to herein are physical ports, in effect a pair of logical ports of a pair of optical fibers.
Before testing, first configuration information is configured on first testing equipment, and the method specifically comprises the following steps: when the synchronous Ethernet signal is sent for the first time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; when the synchronous Ethernet signal is sent for the second time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; when the synchronous Ethernet signal is sent for the third time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; when the synchronous Ethernet signal is sent for the fourth time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; desired TNSM、TSMAnd THMThe value of (b) corresponds to a numerical range.
Referring to table 2, table 2 is related to the configuration of the first configuration information in the embodiment of the present application. The SSM value corresponding to column 1 is the SSM value of the synchronous ethernet signal sent through the first port (SSM sent by synchronous ethernet signal i); the SSM value corresponding to column 2 is the SSM value of the synchronous ethernet signal transmitted through the second port (SSM of synchronous ethernet signal ii). Namely, the synchronous Ethernet signal sent by the first port is the synchronous Ethernet signal I; the synchronous ethernet signal sent through the second port is the synchronous ethernet signal ii.
as shown in table 2, when the synchronous ethernet signal is sent for the first time, the SSM value corresponding to the first port is 2, and the SSM value corresponding to the second port is 8; when the synchronous Ethernet signal is sent for the second time, the SSM value corresponding to the first port is 4, and the SSM value corresponding to the second port is 8; when the synchronous Ethernet signal is sent for the third time, the SSM value corresponding to the first port is F, and the SSM value corresponding to the second port is 8; and when the synchronous Ethernet signal is sent for the fourth time, the SSM value corresponding to the first port is F, and the SSM value corresponding to the second port is B.
TABLE 2
Tij in Table 2 means the time at which the SSM value changes from a table value (row i-1, column j) to a table value (row i, column j). Example T21 (column 1: 2 → 4) means the specific time at which the SSM value changes from 2 in table (1, 1) to 4 in table (2, 1).
the SSM values for the correct response of the device under test (the SSM expected for the corresponding return synchronous ethernet ii transmission) are given in column 3 of table 2. Column 4 is the time recorded in the test process, and column 5 is the value of hold information delay, non-switching information delay and switching information delay calculated according to the value in column 4.
Desired T of configurationNSM、TSMAnd THMThe numerical ranges corresponding to the values of (a) are specifically:
Expected T of first test equipment configurationNSMcorresponding to a value in the range of 0 to 200ms, the desired TSMcorresponding to a value in the range of 180 to 500ms, the desired THMThe value of (a) corresponds to a value in the range of 500 to 2000 ms.
The following describes in detail a process of implementing a test of SSM information processing latency in an embodiment of the present application with reference to the accompanying drawings.
Referring to fig. 2, fig. 2 is a schematic view of a test flow of SSM information processing delay in the embodiment of the present application. The method comprises the following specific steps:
Step 201, the first test equipment sends synchronous ethernet signals on the first port and the second port simultaneously according to the configured first to fourth SSM values.
Step 202, when the tested device receives the synchronous ethernet signal sent by the first testing device through the third port and the fourth port, the tested device responds to the synchronous ethernet message to the first testing device through the fourth port according to the configured response rule.
Step 203, when the first test equipment sends the synchronous signal through the first port for the second time, recording the sending time as T21Recording the transmission when the synchronization signal is transmitted through the first port for the third timeAt a time T31(ii) a When the synchronous signal is transmitted through the second port for the fourth time, the transmission time is recorded as T42(ii) a When the synchronous signal sent by the tested device is received through the second port for the second time, the sending time is recorded as T23(ii) a When the synchronous signal sent by the tested device is received through the second port for the third time, the sending time is recorded as T33(ii) a When the synchronous signal sent by the tested device is received through the second port for the fourth time, the sending time is recorded as T43。
Step 204, the first test equipment determines T23And T21Whether the difference in (b) is at the desired TNSMIf yes, determining that the non-switching information delay accords with SSM information processing delay regulation; otherwise, determining that the non-switching information delay does not accord with SSM information processing delay regulation, and displaying.
step 205, the first testing device determines T33and T31Whether the difference in (b) is at the desired TSMa numerical range corresponding to the value; if yes, determining that the switching information delay accords with SSM information processing delay regulation; otherwise, determining that the switching information delay does not accord with SSM information processing delay regulation, and displaying.
Step 206, the first test equipment determines T43And T42Whether the difference in (b) is at the desired THMA numerical range corresponding to the value; if yes, determining that the information delay accords with SSM information processing delay regulation; otherwise, determining that the holding information delay does not accord with SSM information processing delay regulation, and displaying.
The execution of steps 204 to 206 is not sequential.
The detailed description of the test process of implementing the SSM information processing delay according to the present application will be described with reference to table 2 and fig. 2, where the device under test selects a clock source according to the principle that "the clock quality level QL takes precedence over the local preset priority" and follows the SSM response rule.
Two paths of synchronous Ethernet clock reference sources are arranged at the third port and the fourth port of the tested device;
The first test equipment is set to simultaneously send synchronous Ethernet signals at a first port and a second port, the sent SSM byte values are respectively the values of the 1 st row in the 1 st column and the 2 nd row in the table 2, at this time, the tested equipment should track the synchronous Ethernet signal I received through a third port, and the SSM value sent by the corresponding return synchronous Ethernet signal II is expected to be 2 through a 4 th port.
As shown in Table 2, line 2, the SSM byte value sent by the first test equipment at port 1 is set to change from 2 to 4, and the meter records the value T at this moment21(column 1: 2 → 4) when the device under test should track the synchronous Ethernet signal I, the SSM value sent by port 2 in anticipation of the corresponding return synchronous Ethernet signal II should also change from 2 to 4, and the meter records this time as T23(column 3: 2 → 4), calculate TNSM＝T23-T21。
as shown in Table 2, line 3, the SSM byte value sent by the first test equipment at port 1 is set to be changed from 4 to F, and the meter records the moment T31(column 1: 4 → F), at this time, the tested device should track the synchronous Ethernet signal II, the SSM value sent by the port 2 expecting the corresponding return synchronous Ethernet signal II should also be changed from 4 to F, and the meter records this time as T33(column 3: 4 → F), calculate TSM＝T33-T31。
As shown in Table 2, line 4, the SSM byte value sent by the first test equipment at port 2 is set to be changed from 8 to F, and the meter records the moment T42(column 2: 8 → F) when the device under test should enter the hold state, the SSM value sent by port 2 in anticipation of the corresponding return synchronous Ethernet signal II should also be changed from F to B, and the time T recorded by the meter is43(column 3: F → B), calculate THM＝T43-T42。
Will be directed to T calculated in lines 2, 3 and 4NSM、TSM、THMIf the value of the time delay is within the expected value range, the corresponding time delay is in accordance with the specification, otherwise, the corresponding time delay is not in accordance with the specification, and an error item is displayed, if the specific implementation is realized, a red or yellow prompt can be used.
The following describes in detail a testing process of the timing switching delay of a chain network having n (n is greater than 1) EEC network elements in the embodiment of the present application.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a test of the timing switching delay of a chain network having n EEC network elements. Fig. 2 includes two test devices, a second test device and a third test device, respectively, and n EEC network elements (NE1 to NEn).
Setting a main synchronous Ethernet clock link and a standby synchronous Ethernet clock link for a chain type network with n EEC network elements, wherein the synchronous Ethernet clock link between the second test equipment and the network elements is a main link; a synchronous Ethernet clock link between the third test equipment and the network element equipment is a standby link; wherein n is an integer greater than 1;
The second test device and the first test device in the embodiment of the application are the same test device or different test devices. That is to say, if the test is carried out in parallel, the whole application needs three tested devices, and if the test is carried out at different times, two tested devices can be used.
The specific test process is as follows:
Step one, the second test equipment sends synchronous Ethernet signal with SSM value of 2 to the network element equipment; sending a synchronous Ethernet signal with an SSM value of F to the network element equipment, and recording the moment when the SSM value of the sent synchronous Ethernet signal is changed from 2 to F as a moment T1; and the main link and the standby link of the synchronous Ethernet clock link are switched.
And step two, the third test equipment sends a synchronous Ethernet signal with an SSM value of 4 to the network element equipment.
in the switching process, the synchronous Ethernet signal SSM byte value correspondingly returned by the second test equipment at the fifth port is changed from F to B, and the third step is executed after the switching of the link type network clock is finished.
Thirdly, when the second testing equipment records the moment when the SSM value carried by the received synchronous Ethernet signal is changed from B to 4 as the moment T2
Step four, the second test equipment determines whether the difference between T2 and T1 is between 0.5+0.18n and 2+0.2(n-2) +0.5n seconds, and if so, determines that the timing switching time delay of the chain type network of the n ECC network elements meets the regulation; otherwise, determining that the timing switching time delay of the chain type network of the n ECC network elements does not meet the regulation.
When the method is specifically implemented, the synchronous test instrument is written in a program mode, so that the purposes of standardizing the test flow, improving the test efficiency and reducing human errors are achieved. Meanwhile, the invention provides an automatic test example of the timing switching time delay of the chain network with n SEC/EEC network elements, which can test the timing switching time delay of the chain network with 20 SEC/EEC network elements specified in the standard and also can provide an alternative test reference scheme when the number of the network elements is insufficient.
in summary, the present application standardizes a testing method for processing time delay of SSM information in a clock synchronization test, and provides a testing method for timing switching time delay of a chain network when the number of network elements is insufficient; the test efficiency is improved and human errors are reduced through an automatic test program; the result is automatically read, so that the test is simpler, and the method is particularly suitable for concentrated comparative tests with tight time, multiple test objects and unified test standards.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (5)
1. A testing method for processing time delay of synchronous status message SSM is characterized in that the method comprises the following steps:
configuring first configuration information: when the synchronous Ethernet signal is sent for the first time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; when the synchronous Ethernet signal is sent for the second time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; when the synchronous Ethernet signal is sent for the third time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; when the synchronous Ethernet signal is sent for the fourth time, the SSM value corresponding to the first port and the SSM value corresponding to the second port are obtained; desired TNSM、TSMAnd THMThe value of (d) corresponds to a numerical range;
the first test equipment simultaneously sends synchronous Ethernet signals on the first port and the second port according to the configured SSM values of the first time to the fourth time;
when the tested device receives the synchronous Ethernet signal sent by the first test device through the third port and the fourth port, the tested device responds to the synchronous Ethernet message to the first test device through the fourth port according to the configured response rule;
When the first test equipment sends the synchronous signal through the first port for the second time, the sending time is recorded as T21When the synchronous signal is transmitted through the first port for the third time, the transmission time is recorded as T31(ii) a When the synchronous signal is transmitted through the second port for the fourth time, the transmission time is recorded as T42(ii) a When the synchronous signal sent by the tested device is received through the second port for the second time, the sending time is recorded as T23(ii) a When the synchronous signal sent by the tested device is received through the second port for the third time, the sending time is recorded as T33(ii) a When the synchronous signal sent by the tested device is received through the second port for the fourth time, the sending time is recorded as T43；
The first test equipment determines T23And T21Whether the difference in (b) is at the desired TNSMIf yes, determining that the non-switching information delay accords with SSM information processing delay regulation; otherwise, determining that the non-switching information delay does not accord with SSM information processing delay regulation, and displaying;
the first test equipment determines T33And T31Whether the difference in (b) is at the desired TSMA numerical range corresponding to the value; if yes, determining that the switching information delay accords with SSM information processing delay regulation; otherwise, determining that the switching information delay does not accord with SSM information processing delay regulation, and displaying;
The first test equipment determines T43And T42Whether the difference in (b) is at the desired THMA numerical range corresponding to the value; if yes, determining that the information delay accords with SSM information processing delay regulation; otherwise, determining that the holding information delay does not accord with SSM information processing delay regulation, and displaying.
2. The method of claim 1,
When the synchronous Ethernet signal is transmitted for the first time, the synchronous Ethernet signal is transmitted at the first portThe corresponding SSM value is 2, the corresponding SSM value at the second port is 8; when the synchronous Ethernet signal is sent for the second time, the SSM value corresponding to the first port is 4, and the SSM value corresponding to the second port is 8; when the synchronous Ethernet signal is sent for the third time, the SSM value corresponding to the first port is F, and the SSM value corresponding to the second port is 8; when the synchronous Ethernet signal is sent for the fourth time, the SSM value corresponding to the first port is F, and the SSM value corresponding to the second port is B; desired TNSMCorresponding to a value in the range of 0 to 200ms, the desired TSMCorresponding to a value in the range of 180 to 500ms, the desired THMThe value of (a) corresponds to a value in the range of 500 to 2000 ms.
3. The method of claim 1, further comprising:
Setting a main synchronous Ethernet clock link and a standby synchronous Ethernet clock link for a chain type network with n EEC network elements, wherein the synchronous Ethernet clock link between the second test equipment and the network elements is a main link; a synchronous Ethernet clock link between the third test equipment and the network element equipment is a standby link; wherein n is an integer greater than 1;
The second testing equipment sends a synchronous Ethernet signal with an SSM value of 2 to the network element equipment; sending a synchronous Ethernet signal with an SSM value of F to the network element equipment, and recording the moment when the SSM value of the sent synchronous Ethernet signal is changed from 2 to F as a moment T1; the main link and the standby link of the synchronous Ethernet clock link are switched;
The third testing equipment sends a synchronous Ethernet signal with an SSM value of 4 to the network element equipment;
When the second testing device records the moment when the SSM value carried by the received synchronous Ethernet signal changes from B to 4 as the moment T2
The second testing equipment determines whether the difference value between T2 and T1 is between 0.5+0.18n and 2+0.2(n-2) +0.5n seconds, and if so, determines that the timing switching time delay of the chain type network of the n ECC network elements meets the regulation; otherwise, determining that the timing switching time delay of the chain type network of the n ECC network elements does not meet the regulation.
4. The method of claim 3,
The second test device and the first test device are the same test device or different test devices.
5. the method according to any one of claims 1 to 4,
The first test device, the second test device, and the third test device may each have a rubidium clock built-in, or may track an external reference clock.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111510346A (en) * | 2020-04-08 | 2020-08-07 | 中国信息通信研究院 | End-to-end network forwarding delay determination method and device |
| CN112448867A (en) * | 2020-11-26 | 2021-03-05 | 海光信息技术股份有限公司 | Signal delay testing method and device, computer readable storage medium and electronic equipment |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004084449A1 (en) * | 2003-03-17 | 2004-09-30 | Fujitsu Limited | Synchronous network |
| CN1759553A (en) * | 2003-01-14 | 2006-04-12 | 霍尼韦尔国际公司 | Method and apparatus for the synchronization of a system time of a communications network with a clock reference |
| US20060164782A1 (en) * | 2005-01-27 | 2006-07-27 | Silvio Colombi | Control system, method and product for uninterruptible power supply |
| CN103248445A (en) * | 2012-02-09 | 2013-08-14 | 中兴通讯股份有限公司 | Clock synchronization method and device |
| CN104103302A (en) * | 2013-04-10 | 2014-10-15 | 纬创资通股份有限公司 | Video and audio synchronous detection device and method |
| CN104980244A (en) * | 2015-07-01 | 2015-10-14 | 大唐电信（成都）信息技术有限公司 | Input line time-delay compensation apparatus and method of time synchronization equipment |
| CN105792236A (en) * | 2014-12-26 | 2016-07-20 | 中兴通讯股份有限公司 | Delay acquisition method and device, baseband unit and communication system |
-
2018
- 2018-06-06 CN CN201810583752.3A patent/CN110572294B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1759553A (en) * | 2003-01-14 | 2006-04-12 | 霍尼韦尔国际公司 | Method and apparatus for the synchronization of a system time of a communications network with a clock reference |
| WO2004084449A1 (en) * | 2003-03-17 | 2004-09-30 | Fujitsu Limited | Synchronous network |
| US20060164782A1 (en) * | 2005-01-27 | 2006-07-27 | Silvio Colombi | Control system, method and product for uninterruptible power supply |
| CN103248445A (en) * | 2012-02-09 | 2013-08-14 | 中兴通讯股份有限公司 | Clock synchronization method and device |
| CN104103302A (en) * | 2013-04-10 | 2014-10-15 | 纬创资通股份有限公司 | Video and audio synchronous detection device and method |
| CN105792236A (en) * | 2014-12-26 | 2016-07-20 | 中兴通讯股份有限公司 | Delay acquisition method and device, baseband unit and communication system |
| CN104980244A (en) * | 2015-07-01 | 2015-10-14 | 大唐电信（成都）信息技术有限公司 | Input line time-delay compensation apparatus and method of time synchronization equipment |
Non-Patent Citations (2)
| Title |
|---|
| LIANHONG ZHOU, XU WANG, CHONGXI FENG: "Synchronization Issues in SDH Networks", 《2000 INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY》 * |
| 秦晓芳，杨大成，张欣: "新的基于SR-SW-HARQ 的低时延视频传输方案", 《通信学报》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111510346A (en) * | 2020-04-08 | 2020-08-07 | 中国信息通信研究院 | End-to-end network forwarding delay determination method and device |
| CN112448867A (en) * | 2020-11-26 | 2021-03-05 | 海光信息技术股份有限公司 | Signal delay testing method and device, computer readable storage medium and electronic equipment |
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