CN105933086B - A method and apparatus to achieve accurate clock protocol medium access control module - Google Patents

A method and apparatus to achieve accurate clock protocol medium access control module Download PDF

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CN105933086B
CN105933086B CN 201610510846 CN201610510846A CN105933086B CN 105933086 B CN105933086 B CN 105933086B CN 201610510846 CN201610510846 CN 201610510846 CN 201610510846 A CN201610510846 A CN 201610510846A CN 105933086 B CN105933086 B CN 105933086B
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郭敏
谢海春
蒋汉柏
廖北平
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湖南恒茂高科股份有限公司
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Abstract

本发明提供一种在媒体访问控制模块中实现精确时钟协议的方法和装置。 The method and apparatus of the present invention provides an accurate clock protocol medium access control module. 所述装置包括:媒体访问控制模块及时戳控制模块。 The apparatus comprising: a medium access control module timestamp and timely control module. 所述媒体访问控制模块包括相互之间依次连接的接口转换子模块、媒体独立接口控制子模块、速率调整子模块及物理编解码子模块。 The media access control module comprises an interface conversion sub-module connected successively to each other, Media Independent Interface control sub-module, and a physical rate adjustment module codec module. 其中,所述时戳控制模块设置于所述速率调整子模块与所述物理编解码子模块之间,所述时戳控制模块用于对所述媒体访问控制模块中的时间戳进行处理,以在所述媒体访问控制模块中实现精确时钟协议。 Wherein the control module is disposed on the timestamp rate adaptation between the module and the physical sub-sub-module of the encoding and decoding, the timestamp of the control means for the medium access control module for processing the time stamp to precise clock in the medium access control protocol module. 上述装置能提高精确时钟协议的时间戳精度。 Said means can improve the accuracy of the timestamp precision time protocol.

Description

在媒体访问控制模块中实现精确时钟协议的方法和装置 A method and apparatus to achieve accurate clock protocol medium access control module

技术领域 FIELD

[0001] 本发明属于芯片设计领域,具体涉及一种在交换机芯片设计中在媒体访问控制(Gigabit Media Access Control,简称GMAC)模块上实现精确时钟协议的方法和装置。 [0001] The present invention belongs to the field of chip design, particularly to a method and apparatus for accurate clock at the switch module protocol chip design a medium access control (Gigabit Media Access Control, abbreviated GMAC),.

背景技术 Background technique

[0002] 目前,分布式系统广泛运用于网络中,而分布式系统,往往需要一个全局的时钟,来确定系统中各事件发生的先后顺序,以及协调事件间传输的信息。 [0002] Currently, the system is widely used in distributed networks and distributed systems, often require a global clock information to determine the sequence of events for each system, as well as coordination between transmission of the event. 这就要求系统中的各个部件有一个统一的时钟,并且能够在各个部件之间传递时间信息。 This requires the various components in the system has a single clock, and is able to transmit the time information between the various components. 如何在网络上提供可靠的时间服务已经成为一个重要的研究课题。 How to provide reliable time service on the network has become an important research topic.

[0003] 精确时钟协议(Precision Time Protocol,简称PTP)是一种对标准以太网终端设备进行时间和频率同步的协议,也称为IEEE 1588协议。 [0003] Precision Time Protocol (Precision Time Protocol, referred to as PTP) is a terminal device on the Ethernet standard time and frequency synchronization protocol, also known as IEEE 1588 protocol. PTP协议能够在不改变现有网络结构的前提下,利用以太网的帧传输时间信息,并且能够保证时间的精度。 PTP protocol is possible without changing the existing network structure provided by the Ethernet frame transmission time, and can ensure the accuracy of the time. 由于PTP协议实现简单,占用的网络和计算资源少等优点使其广泛应用于分布式系统中。 Since the PTP protocol simple, small network and computing resources used, etc. it is widely used in the distributed system.

[0004] PTP协议可以采用软件实现。 [0004] PTP protocol may be implemented in software. 但采用软件实现PTP协议时,由于网络的不平稳性,交换机对数据包的缓存以及操作系统进程的调度的影响,使得网络不能提供很高精度的时间服务,通常软件实现的时间精度只能够达到毫秒级(ms)。 But PTP protocol implemented in software, since the network is not smooth, the impact of the switch on the cached data packets and scheduling of operating system processes, so that the network can not provide a very high-precision time service, the time accuracy is usually implemented in software can be reached only milliseconds (ms). 显然这样的时间精度是无法满足交换机芯片设计的中一些高标准的要求。 Apparently this time precision is not required to meet the high standards of the switch chip design some. 如何提高上述时间精度对本领域技术人员而言是急需要解决的技术问题。 How to improve the accuracy of these hours of skilled personnel is urgently needed technical problem to be solved.

发明内容 SUMMARY

[0005] 有鉴于此,本发明实施例的目的在于提供一种能在媒体访问控制模块中实现PTP协议的方法和装置,以解决现有技术中在媒体访问控制模块中实现PTP协议时间精度不高的技术问题。 [0005] In view of this, object of embodiments of the present invention is to provide a method and apparatus to achieve the PTP protocol medium access control module in the prior art to solve the PTP protocol implemented in a medium access control module precision time high technical problems.

[0006] 就实现PTP协议的装置而言,本发明实施例提供一种在媒体访问控制模块中实现精确时钟协议的装置。 [0006] In terms of apparatus to achieve the PTP protocol, embodiments of the present invention provides an apparatus for precision clock protocol are implemented in a medium access control module. 所述装置包括:媒体访问控制模块及时戳控制模块,所述媒体访问控制模块包括相互之间依次连接的接口转换子模块、媒体独立接口控制子模块、速率调整子模块及物理编解码子模块。 The apparatus comprising: a medium access control module timestamp and timely control module, the medium access control module comprises an interface conversion sub-module connected successively to each other, the media independent interface control sub-module, and a physical rate adjustment module codec module. 其中,所述时戳控制模块设置于所述速率调整子模块与所述物理编解码子模块之间,所述时戳控制模块用于对所述媒体访问控制模块中的时间戳进行处理,以在所述媒体访问控制模块中实现精确时钟协议。 Wherein the control module is disposed on the timestamp rate adaptation between the module and the physical sub-sub-module of the encoding and decoding, the timestamp of the control means for the medium access control module for processing the time stamp to precise clock in the medium access control protocol module.

[0007] 进一步地,所述装置中的所述时戳控制模块包括:发送子模块及接收子模块。 [0007] Further, the control module includes timestamp means when: sending sub-module and the receiving sub-module. 所述发送子模块包括多级流水线处理单元、信息锁存单元、替换控制单元、计数器、时戳调整单元、寄存器及循环冗余码校验单元。 Said sending sub-module comprises a multi-stage pipeline processing unit, the information latch unit replacement control unit, a counter, adjusting stamp unit, and cyclic redundancy check register unit time. 其中,所述信息锁存单元对输入帧的处理信息进行锁存备用。 Wherein said information processing of the information input latch unit latches alternate frames. 所述替换控制单元与所述信息锁存单元、多级流水线处理单元及计时器连接。 The replacement control information unit and the latch unit, and a multi-stage pipeline processing unit connected to a timer. 所述时戳调整单元的一侧输入端输入系统的实时时间,另一侧输入端与所述寄存器连接,所述时戳调整单元的输出端与所述多级流水线处理单元连接。 The real-time time stamp adjustment unit side input terminal of the system, the other side input terminal of said register is connected to the output terminal means to adjust the timestamp of the connection with the multi-stage pipeline processing unit. 所述循环冗余码校验单元与所述多级流水线处理单元连接用于对新的帧内容进行重新计算循环冗余码校验的值。 The loop value is connected to the multi-stage pipeline processing unit for the content of the new frame is recalculated cyclic redundancy check code redundancy check unit. 所述接收子模块包括时戳捕获单元,所述时戳捕获单元用于在接收到一个帧开始时,捕获下当前的系统时间。 The receiving sub-module when capturing unit includes a timestamp, the timestamp when capturing means for receiving a frame starts, capturing the current system time.

[0008] 进一步地,所述装置中的所述时戳控制模块通过媒体独立接口与所述速率调整子模块及物理编解码子模块相连。 [0008] Further, the control module timestamp when the device is connected to the sub-modules and sub-modules by physical codec media independent interface and the rate adjustment. 所述媒体独立接口包括用于发送有效信号的数据线、发送数据信号的数据线及发送错误信号的数据线,所述多级流水线处理单元对所述媒体独立接口输入的数据进行处理后输出。 The media independent interface includes means for transmitting a data valid signal line, a data line transmitting a data signal and a data line transmitting an error signal of the multi-stage pipeline data processing unit to the media independent interface for processing input after output.

[0009] 进一步地,所述装置中的所述多级流水线处理单元为5级流水线处理单元。 [0009] Further, the apparatus of a multi-stage pipeline processing unit is a five-stage pipeline processing unit.

[0010] 进一步地,所述装置中所述寄存器存储有用于进行时间戳校准的校准信号。 [0010] Further, in the said register means stores a calibration signal for calibrating the time stamp. 所述校准信号包括标志位和需要进行校准的时间值,所述时戳调整单元根据所述标志位对所述时间戳进行相应时间值的调整。 The calibration signal comprises a flag bit time value and needs to be calibrated, the timestamp of the time stamp position adjusting means to adjust the time corresponding to the value when said flag.

[0011] 就实现PTP协议的方法而言,本发明实施例提供一种在媒体访问控制模块中实现精确时钟协议的方法,所述媒体访问控制模块包括相互之间依次连接的接口转换子模块、媒体独立接口控制子模块、速率调整子模块及物理编解码子模块,所述方法包括:采用时戳控制模块对所述媒体访问控制模块的时间戳进行处理以实现精确时钟协议,其中所述时戳控制模块设置在所述速率调整子模块与所述物理编解码子模块之间。 [0011] In terms of the PTP protocol implemented method, provides an accurate clock protocol medium access control module in the method of the present invention, the medium access control module comprises an interface converter submodule sequentially connected to each other, the control module timestamp of the media access control module time stamps are processed to achieve accurate clock protocol employed, wherein the: a media independent interface control sub-module, and a physical rate adjustment module codec sub-module, the method comprising timestamp control module is disposed between the module and the sub-rate adjustment physical encoding and decoding sub-module.

[0012] 进一步地,所述方法中的所述时戳控制模块包括:发送子模块及接收子模块。 [0012] Further, the control module includes a timestamp of when the method: sending sub-module and the receiving sub-module. 所述发送子模块包括多级流水线处理单元、信息锁存单元、替换控制单元、计数器、时戳调整单元、寄存器及循环冗余码校验单元。 Said sending sub-module comprises a multi-stage pipeline processing unit, the information latch unit replacement control unit, a counter, adjusting stamp unit, and cyclic redundancy check register unit time. 其中,所述信息锁存单元对输入帧的处理信息进行锁存备用。 Wherein said information processing of the information input latch unit latches alternate frames. 所述替换控制单元与所述信息锁存单元、多级流水线处理单元及计时器连接。 The replacement control information unit and the latch unit, and a multi-stage pipeline processing unit connected to a timer. 所述时戳调整单元的一侧输入端输入系统的实时时间,另一侧输入端与所述寄存器连接,所述时戳调整单元的输出端与所述多级流水线处理单元连接。 The real-time time stamp adjustment unit side input terminal of the system, the other side input terminal of said register is connected to the output terminal means to adjust the timestamp of the connection with the multi-stage pipeline processing unit. 所述循环冗余码校验单元与所述多级流水线处理单元连接用于对新的帧内容进行重新计算循环冗余码校验的值。 The loop value is connected to the multi-stage pipeline processing unit for the content of the new frame is recalculated cyclic redundancy check code redundancy check unit. 所述接收子模块包括时戳捕获单元,所述时戳捕获单元用于在接收到一个帧开始时,捕获下当前的系统时间。 The receiving sub-module when capturing unit includes a timestamp, the timestamp when capturing means for receiving a frame starts, capturing the current system time.

[0013] 进一步地,所述方法中的所述多级流水线处理单元为5级流水线处理单元。 [0013] Further, the method of the multi-stage pipeline processing unit is a five-stage pipeline processing unit.

[0014] 进一步地,所述方法中的所述寄存器存储有用于进行时间戳校准的校准信号。 [0014] Further, the register storing the calibration method for calibrating a time stamp signal. 所述校准信号包括标志位和需要进行校准的时间值,所述时戳调整单元根据所述标志位对所述时间戳进行相应时间值的调整。 The calibration signal comprises a flag bit time value and needs to be calibrated, the timestamp of the time stamp position adjusting means to adjust the time corresponding to the value when said flag.

[0015] 相对于现有技术,本发明提供的在媒体访问控制模块中实现精确时钟协议的方法和装置,将打时间戳的地方设置在交换机芯片中所有的缓存之后的Gmac模块中,相对于采用软件实现的方式可以极大的提高了时间精度。 [0015] with respect to the prior art, a method and apparatus to achieve accurate clock protocol medium access control module of the present invention is provided, where the timestamps provided Gmac switch chip module after all caches with respect to mode is implemented using software can greatly improve the accuracy of the time.

[0016] 为使本发明的上述目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合所附附图,作详细说明如下。 [0016] For the above-described objects, features and advantages of the present invention can be more fully understood by reading the following preferred embodiments, and accompanied with figures are described in detail below.

附图说明 BRIEF DESCRIPTION

[0017] 为了更清楚地说明本发明实施例的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,应当理解,以下附图仅示出了本发明的某些实施例,因此不应被看作是对的限定,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他相关的附图。 [0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings are briefly introduced as required for use in the embodiments describing the embodiments, it should be understood that the appended drawings illustrate only certain embodiments of the present invention. therefore not to be seen as limited to those of ordinary skill in the art is concerned, without creative efforts may still obtain other drawings according to these drawings.

[0018] 图1为本发明实施例提供的媒体访问控制模块的设计架构图。 [0018] FIG. 1 design a medium access control module architecture diagram according to an embodiment of the present invention.

[0019] 图2为本发明实施例提供的在媒体访问控制模块中实现精确时钟协议的装置的设计架构图。 [0019] FIG. 2 apparatus design architecture of FIG accurate clock protocol medium access control module according to an embodiment of the present invention.

[0020] 图3为封装了PTP报文的以太网帧格式。 [0020] FIG. 3 is a PTP packet encapsulates an Ethernet frame format.

[0021] 图4为本发明实施例提供的时戳控制模块的设计架构图。 [0021] FIG 4 FIG stamp design architecture of the control module when according to an embodiment of the present invention.

[0022] 主要元件符号说明 [0022] Main reference numerals DESCRIPTION

[0023] [0023]

Figure CN105933086BD00061

具体实施方式 Detailed ways

[0024] 下面将结合本发明实施例中附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。 [0024] below in conjunction with the present invention illustrated in the drawings embodiments, the technical solutions in the embodiments will be apparent to the present invention, completely described, obviously, the described embodiments are merely part of embodiments of the present invention rather than all embodiments . 通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。 Components of an embodiment of the present invention is generally described herein and illustrated in the drawings can be arranged and designed in a variety of different configurations. 因此,以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的,而是仅仅表示本发明的选定实施例。 Accordingly, the following detailed description of the present invention provides embodiments in the accompanying drawings are not intended to limit the invention, as claimed, but is merely representative of selected embodiments of the present invention. 基于本发明的实施例,本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, all other embodiments of the present art in the art without creative efforts shall fall within the scope of the present invention.

[0025] 请参照图1,图1是本发明实施例提供的媒体访问控制模块100的设计架构图。 [0025] Referring to FIG. 1, FIG. 1 is a medium access control module provided in the design architecture of the embodiment 100 of the present invention, FIG. 所述媒体访问控制模块100包括:接口转换子模块110、媒体独立接口控制子模块120、速率调整子模块130及物理编解码子模块140。 The media access control module 100 includes: an interface conversion sub-module 110, a media independent interface control sub-module 120, a rate adjustment module 130, and a physical sub-module 140 codec. 所述接口转换子模块110、媒体独立接口控制子模块120、速率调整子模块130及物理编解码子模块140依次电性连接。 The interface conversion sub-module 110, a media independent interface control sub-module 120, the rate adjustment sub-module 140 sequentially electrically codec 130 and physical sub-module. 所述接口转换子模块110的主要功能是进行接口位宽转换,并通过异步输入输出缓存(First Input First output,简称FIFO)进行跨时钟域处理。 The primary function of the interface conversion sub-module 110 is the bit width converting interface, inter-clock domain and processed by the asynchronous input and output buffers (First Input First output, referred to as FIFO). 所述媒体独立接口控制子模块120用于将网络报文封装成IEEE802.3协议规定的帧格式和从帧格式中解出网络报文。 The media independent interface control sub-module 120 for network packets are encapsulated into a predetermined protocol IEEE802.3 frame format and frame format is extracted from the packet network. 所述速率调整子模块130用于使用异步FIFO进行不同速率间的调整(比如,10M/100M/1000M)。 The rate adjustment sub-module 130 is adjusted using asynchronous FIFO (for example, 10M / 100M / 1000M) between different rates. 所述物理编解码子模块140用于进行物理编解码。 The physical encoding and decoding sub-module 140 for performing physical codec.

[0026] 根据上面描述可知,所述接口转换子模块110与速率调整子模块130均含有异步输入输出缓存。 [0026] From the above description that, the interface conversion module 110 and the sub-rate adjustment module 130 contain asynchronous input and output buffers. 因此为了保证时间戳的精度,打印时间戳的操作放置在所述速率调整子模块130之后。 Therefore, in order to ensure the accuracy of the time stamps, stamp printing operation is placed after the rate adjustment module 130. 具体地,请参照图2,为实现精确时钟协议的装置10包括媒体访问控制模块100及时戳控制模块200,具体地,时戳控制模块200设置于媒体访问控制模块100的速率调整子模块130与物理编解码子模块140之间,所述时戳控制模块200用于进行时间戳处理。 In particular, referring to FIG 2, is a device for implementing precise time protocol 10 includes a media access control module 100 timely timestamp control module 200, in particular, the time-stamp control module 200 is provided adjustment module 130 to the rate of the media access control module 100 and physical codec between sub-module 140, the time-stamp control module 200 for stamp processing.

[0027] 在本实施中,时间戳(TimeStamp)域为80比特的时戳信息。 When [0027] In the present embodiment, the time stamp (TimeStamp) is a 80-bit time stamp field information. 为了使PTP报文能够在以太网中传输,其必须封装在以太网的帧格式中,请参照图3。 In order to PTP packets are transmitted in the Ethernet, it must be encapsulated in an Ethernet frame format, please refer to FIG. 3. 为了能给PTP帧中打上实时时间戳,需要要知道TimeStamp域在帧中的位置,这个工作是在包处理引擎中解析的。 In order to give real-time stamp stamped PTP frame, you need to know the location of TimeStamp field in the frame of this work is to parse the packet processing engine.

[0028] 请参照图4,图4是所述时戳控制模块200的具体设计功能模块图。 [0028] Referring to FIG. 4, FIG. 4 is a specific design stamp control block diagram when the module 200. 所述时戳控制模块200包括:发送子模块210及接收子模块220。 The timestamp control module 200 includes: a sending and receiving sub-module 210 sub-module 220.

[0029] 所述发送子模块210包括:多级流水线处理单元211、信息锁存单元212、替换控制单元213、计数器214、循环冗余码校验单元215、时戳调整单元216及寄存器217。 [0029] The sending sub-module 210 includes: a multi-stage pipeline processing unit 211, information of a latch unit 212, a replacement control unit 213, a counter 214, a cyclic redundancy check unit 215, the time stamp adjustment unit 216 and the register 217. 其中,所述信息锁存单元212对输入帧的处理信息进行锁存备用。 Wherein the latch unit 212 latches the information on the spare processing information input frame. 所述替换控制单元213与所述信息锁存单元212、多级流水线处理单元211及计数器214连接。 Alternatively the control unit 213 with the information latch unit 212, a multi-stage pipeline processing unit 211 and the counter 214 is connected. 所述时戳调整单元216的一侧输入端输入系统的实时时间,所述时戳调整单元216的另一侧输入端与所述寄存器217连接,所述时戳调整单元216的输出端与所述多级流水线处理单元211连接。 The real time timestamp adjusting unit side input terminal of the system 216, the time stamp adjustment unit 216 side to another input terminal of the register 217 is connected, the output of unit 216 to adjust the time stamp with the time of the said multi-stage pipeline processing unit 211 is connected. 所述循环冗余码校验单元215与所述多级流水线处理单元211连接用于对新的帧内容进行重新计算循环冗余码校验的值。 The loop is connected to the value of the multi-stage pipeline processing unit 211 for a new frame contents recalculated cyclic redundancy check CRC check unit 215.

[0030] 所述接收子模块220包括时戳捕获单元221,用于在接收到一个帧开始时,捕获当前的系统时间。 [0030] The stamp receiving sub-module 220 includes a capture unit 221, for the start of a frame is received, capturing the current system time. 并将所述系统时间给后面的包处理引擎块使用。 And the system time to the back of the packet processing engine block use.

[0031] 在本实施例中,所述时戳控制模块200采用多级流水线(Pipeline)设计,可以节省数据处理时间以满足打印时间戳及重算循环冗余码校验的值所需要的时间。 [0031] In the present embodiment, the control module 200 timestamp multistage pipeline (the Pipeline) the design, the data processing time can be saved to meet the printing stamp and the time value of the cyclic redundancy check required recalculation . 在本实施例中,所述多级流水线处理单元可以为5级流水线处理单元,采用5级流水线对帧数据进行处理。 In the present embodiment, the multi-stage pipeline processing unit may be a 5-stage pipeline processing unit, a 5-stage pipeline processing the frame data.

[0032] 所述时戳控制模块200通过媒体独立接口与所述速率调整子模块130及物理编解码子模块140相连,所述媒体独立接口包括用于发送有效信号(txEn)的数据线、发送数据信号(txd [7 :0])的数据线及发送错误信号(txEr)的数据线,所述多级流水线处理单元211对所述媒体独立接口输入的数据进行处理后输出。 [0032] When the control module is connected timestamp sub-module 130 and a physical sub-codec module 140 through the Media Independent Interface 200 adjusts the rate of the media independent interface includes a transmit active signal (TXEN) data lines, transmission data signal (txd [7: 0]) of the data line and transmits an error signal (TXER) data lines, the data after the multi-stage pipeline processing unit 211 of the media independent interface for processing input output.

[0033] 所述信息锁存单元212对输入的输入帧的处理信息,如msg [7 : 0] ({tsEn,off set[6:0]}),进行锁存备用。 [0033] The information processing unit 212 latch the input frame input information, such as msg [7: 0] ({tsEn, off set [6: 0]}), latched standby. 其中,msg[7:0]中包括了编辑帧所需的信息:tsEn为1表示该帧是PTP报文,需要进行打时间戳操作;off set [6:0]表示时间戳(TimeStamp)域的位置在帧中的偏移。 Wherein, msg [7: 0] is included in the frame information required for editing: tsEn 1 indicates that the frame is a PTP packet, the need for time stamping operation; off set [6: 0] indicates a time stamp (TimeStamp) domain the positional deviation in the frame. 在帧开始的时候启动所述计数器214,当所述计数器214的值等于off set [6:0]时,并且tsEn为1时,进行打时间戳操作,时间戳的位宽为80比特,因此打时间戳的操作要持续10个时钟周期。 The counter 214 starts when the beginning of a frame, when the value of the counter 214 is equal to the off set [6: 0] when, and tsEn is 1, and time stamping operation, timestamp bit width of 80 bits, timestamping operation lasts 10 clock cycles.

[0034]在所述时戳控制模块200中需要输入一个系统的实时时钟(ts [79:0])作为打时间戳的基准时间。 [0034] In the timestamp control module 200 needs to input the real time clock (ts [79: 0]) as a system reference time timestamps. 由于打时间戳的操作放在物理编解码子模块140之前,并不是真正的网络出口,但时戳控制模块200真正的网络出口的延时在设计中是固定的,因此增加了一组校准信号来进行时间戳的校准。 Since timestamping operation on the physical coding sub-module 140 prior to decoding, is not a real network outlet, the outlet timestamp real network delay control module 200 is fixed in the design, thereby increasing a set of calibration signals to calibrate the timestamp. 所述校准信号存储在所述寄存器217中,所述校准信号包括标志位(tsAddSign)和需要进行校准的时间值(tsAddData[15:0]),使所述时戳调整单元216可根据所述标志位对所述时间戳进行相应时间值的调整。 The calibration signal storage time calibrated value (tsAddData [15: 0]) in the register 217, the calibration signal comprises a flag bit (tsAddSign) and the need to make the time stamp adjustment unit 216 according to the flag bit corresponding to the time stamp adjustment time value. 具体地,当tsAddSign为1时,对所述时间戳增加tsAddData [15 :0]的时间值;当tsAddSign为O时,对所述时间戳减小tsAddData[15:0]的时间值。 Specifically, when tsAddSign is 1, the time stamp increase tsAddData [15: 0] of the time value; when tsAddSign is O, reducing the time stamp tsAddData [15: 0] of the time value.

[0035] 所述循环冗余码校验单元215在完成时间戳的打印操作后,根据新的帧的内容重新计算循环冗余校验(Cyclic Redundancy Check,简称CRC)的值,并将其写入帧的校验域(Frame Check Sequence,简称FCS中)〇 [0035] After completion of the stamp printing operation, the contents of the new frame in accordance with the recalculated cyclic redundancy check (Cyclic Redundancy Check, referred to as CRC) value of the cyclic redundancy checking unit 215, and written check field of the frame (frame check Sequence, FCS for short) is square

[0036] 时戳控制模块200的发送子模块210的主要功能就是根据offset的值,通过计数器214找到需要打时间戳的位置,并将80比特的时间戳打到指定的位置。 Control module sends timestamp sub-module 200 of the main function 210 [0036] The value of offset is the time, required by the counter 214 to find the location timestamping, timestamp and 80 bits hit the specified location. 由于打时间戳操作改变了原来帧的内容,因此需要重新计算CRC的值。 Since the time stamping operation changes the contents of the original frame, so the value of the CRC needs to be recalculated.

[0037] 时戳控制模块200的接收子模块220的主要功能是在收到的帧开始的时候,记录帧在网络入口的时间,给后面的包处理引擎模块使用。 Timestamp sub-module 200 receives the control module 220 of the main function of [0037] When a frame is received at the time of start of recording the time frame of the network entry, the packet processing engine to the rear module.

[0038] 与此同时,本实施例还提供一种采用上面描述的装置实现精确时钟协议的方法。 [0038] Meanwhile, the present embodiment also provides an apparatus using the above-described method to achieve accurate clock protocol.

[0039] 所述方法是在媒体访问控制模块100的速率调整子模块130及物理编解码子模块140之间,增加了一个时戳控制模块200来进行PTP协议的时间戳处理。 [0039] The method is a physical adjustment module 130 and the codec rate of the media in the sub-module 100 of the access control module 140 increases the control module 200 stamps stamp processing performed when a PTP protocol.

[0040] 具体地,媒体访问控制模块100的输入为GMII接口信号(txEn,txd[7:0],txEr),将输入的帧进入多级流水线进行处理,输出接口同样为GMII接口(txEnTs,txdTs [7:0],txErTs,其中所述多级流水线为5级流水处理。 [0040] Specifically, a medium access control input module 100 is GMII interface signals (txEn, txd [7: 0], txEr), frame input into a multi-stage pipeline processing, the output interface the same as the GMII interfaces (txEnTs, txdTs [7: 0], txErTs, wherein the multi-stage pipeline is five pipeline processing.

[0041] 将输入帧的处理信息msg[7:0]在帧开始的时候进行锁存备用,msg[7:0]中包含两个信息:tsEn和offset [6:0]。 Processing information msg [0041] The input frame [7: 0] is latched at the time of the standby frame start, msg [7: 0] contains two information: TSEN and offset [6: 0]. tsEn为1表示该帧是PTP报文,需要进行打时间戳操作;off set[6:0]表示TimeStamp域的位置在帧中的偏移。 tsEn 1 indicates that the frame is a PTP packet, the need for time stamping operation; off set [6: 0] indicating the position TimeStamp field offset frame.

[0042] 在帧开始的时候启动一个计数器214,当计数器214的值等于offSet[6:0]时,并且tsEn为1时,进行打时间戳操作,时间戳的位宽为80比特,因此打时间戳的操作要持续10个时钟周期。 [0042] When start of a frame start counter 214, when the value of the counter 214 is equal to offSet [6: 0], the tsEn is 1 and performs time stamping operation, timestamp bit width of 80 bits, thus playing operation to stamp for 10 clock cycles.

[0043] ts [79:0]是系统的实时时间,由于打时间戳的操作放在物理编解码子模块140之前,并不是真正的网络出口,但时戳控制模块200到真正的网络出口的延时在设计中是固定的,因此增加了一组信号(tsAddSign和tsAddData [15:0])来进行时间戳的校准,其中tsAddSign为标志位,1表示加,0表示减;tsAddData [15:0]为需要增加或减小的时间值。 [0043] ts [79: 0] is a real time system, since the time stamping operation on the physical coding sub-module 140 prior to decoding, is not a real network outlet, the outlet timestamp control module 200 to the real network delay is fixed in the design, thereby increasing a set of signals (tsAddSign and tsAddData [15: 0]) to calibrate the timestamp, which is tsAddSign flag indicates plus 1, minus represents 0; tsAddData [15: 0] need to increase or decrease the time value.

[0044] 在完成打时间戳操作后,根据新的帧的内容重新计算CRC的值,并写入帧的FCS域。 [0044] After completion of the operation time stamping, CRC values ​​are recalculated based on the content of the new frame, and writes the FCS field of the frame.

[0045] 时戳控制模块200接收方向收到一个帧的开始时,记录下当前的系统时间,给后面的包处理引擎模块使用。 Control module 200 receives the timestamp direction at the start of a frame is received, the system records the current time [0045], the packet processing engine to the back of the module.

[0046] 综上所述,本实施例提供的在媒体访问控制模块100中实现精确时钟协议的方法及装置。 [0046] In summary, a method and apparatus to achieve accurate clock protocol in a medium access control module 100 according to this embodiment. 在Gmac网口上进行打时间戳的操作,保证了PTP协议时间戳的精度,同时采用流水线设计,不会引入时间戳的抖动。 Gmac performed on the network port time stamping operation, to ensure the accuracy of the PTP protocol time stamp, while the pipelined design, without introducing jitter timestamp. 考虑到打时间戳的操作到真正的网络出口还有一段固定延时,因此增加了一组寄存器217来进行时间戳的校准。 Considering the time stamping operations to the real network as well as an outlet for a fixed time delay, thereby increasing a set of calibration registers 217 to timestamp. 本发明只对PTP报文进行时间戳处理,对网络的其它报文不做任何处理,因此保证了Gmac模块原有功能的正确性。 The present invention is only the PTP stamp processing packets, and other packets to the network without any processing, thus ensuring the correctness Gmac original function modules.

[0047] 以上所述,仅为本发明的具体实施方式,但本发明的保护并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术内,可轻易想到变化或替换,都应涵盖在本发明的保护之内。 [0047] The above are merely specific embodiments of the present invention, but the protection of the present invention is not limited thereto, any skilled in the art in the art in the technology of the present invention is disclosed, variations or replacement that can be easily, It shall fall within the protection of the present invention. 因此,本发明的保护应所述以权利要求的保护为准。 Accordingly, the present invention should be protected to the subject of the claims.

Claims (8)

  1. 1. 一种在媒体访问控制模块中实现精确时钟协议的装置,其特征在于,包括:媒体访问控制模块及时戳控制模块,所述媒体访问控制模块包括相互之间依次连接的接口转换子模块、媒体独立接口控制子模块、速率调整子模块及物理编解码子模块,其中,所述时戳控制模块设置于所述速率调整子模块与所述物理编解码子模块之间,所述时戳控制模块用于对所述媒体访问控制模块中的时间戳进行处理,以在所述媒体访问控制模块中实现精确时钟协议; 所述时戳控制模块包括:发送子模块及接收子模块; 所述发送子模块包括多级流水线处理单元、信息锁存单元、替换控制单元、计数器、时戳调整单元、寄存器及循环冗余码校验单元,其中,所述信息锁存单元对输入帧的处理信息进行锁存备用,所述替换控制单元与所述信息锁存单元、多级流水线处理单元及 1. An apparatus for precise time protocol implemented in a medium access control module, characterized by comprising: a medium access control module timestamp and timely control module, the medium access control sub-module includes an interface conversion module sequentially connected to each other, media independent interface control sub-module, and a physical rate adjustment module codec sub-module, wherein the control module is disposed on the timestamp rate adaptation between the module and the physical sub-sub-module of the codec, the time stamp of the control means for processing the media access control module, a time stamp, to achieve accurate clock in the medium access control protocol module; timestamp when the control module comprises: sending and receiving sub-module sub-module; said transmission sub-module comprises a multi-stage pipeline processing unit, the information latch unit replacement control unit, a counter, adjusting stamp unit, and cyclic redundancy check register unit, wherein said information input latch unit for processing information frames standby latch, the replacement control information unit and the latch unit, and a multi-stage pipeline processing unit 计时器连接,所述时戳调整单元的一侧输入端输入系统的实时时间、另一侧输入端与所述寄存器连接,所述时戳调整单元的输出端与所述多级流水线处理单元连接,所述循环冗余码校验单元与所述多级流水线处理单元连接用于对新的帧内容进行重新计算循环冗余码校验的值; 所述接收子模块包括时戳捕获单元,所述时戳捕获单元用于在接收到一个帧开始时, 捕获当前的系统时间。 A timer connected to the real-time time stamp to adjust input terminal side of the system unit, the other side input terminal connected to said register, said time stamp adjustment means connected to the output of the multi-stage pipeline processing unit the cyclic redundancy check unit of the multi-stage pipeline processing unit is connected to the frame of the new content value recalculated cyclic redundancy check; stamp when the capture unit comprises a receiving sub-module, the when capturing said stamp unit is configured to, when receiving a frame starts capturing the current system time.
  2. 2. 如权利要求1所述的装置,其特征在于,所述时戳控制模块通过媒体独立接口与所述速率调整子模块及物理编解码子模块相连,所述媒体独立接口包括用于发送有效信号的数据线、发送数据信号的数据线及发送错误信号的数据线,所述多级流水线处理单元对所述媒体独立接口输入的数据进行处理后输出。 2. The apparatus according to claim 1, wherein the control module time stamp adjustment module and sub-modules are connected physically through the codec media independent interface and the rate of the time, the media independent interface includes means for transmitting the effective a data signal line, a data line transmitting a data signal transmission line and a data error signal, the multi-stage pipeline processing unit outputs the data input to the media independent interface for processing.
  3. 3. 如权利要求1〜2中任意一项所述的装置,其特征在于:所述多级流水线处理单元为5 级流水线处理单元。 The apparatus of any one of claim 1 to 2, wherein: the multi-stage pipeline processing unit is a five-stage pipeline processing unit.
  4. 4. 如权利要求1所述的装置,其特征在于,所述输入帧的处理信息包括:精确时钟协议标签及时间戳域的位置在帧中的偏移。 The apparatus as claimed in claim 1, wherein said input frame processing information comprising: a precision time protocol label and location stamp field in a frame shift.
  5. 5. 如权利要求1所述的装置,其特征在于,所述寄存器存储有用于进行时间戳校准的校准信号,所述校准信号包括标志位和需要进行校准的时间值,所述时戳调整单元根据所述标志位对所述时间戳进行相应时间值的调整。 5. The apparatus according to claim 1, wherein said register stores a calibration signal for calibrating the time stamp, the calibration signal comprises a flag value and time required for calibration, the time stamp adjustment unit the bit of the flag corresponding to the time stamp adjustment time value.
  6. 6. —种在媒体访问控制模块中实现精确时钟协议的方法,其特征在于,所述媒体访问控制模块包括相互之间依次连接的接口转换子模块、媒体独立接口控制子模块、速率调整子模块及物理编解码子模块,所述方法包括: 采用时戳控制模块对所述媒体访问控制模块的时间戳进行处理以实现精确时钟协议, 其中所述时戳控制模块设置在所述速率调整子模块与所述物理编解码子模块之间; 所述时戳控制模块包括:发送子模块及接收子模块; 所述发送子模块包括多级流水线处理单元、信息锁存单元、替换控制单元、计数器、时戳调整单元、寄存器及循环冗余码校验单元,其中,所述信息锁存单元对输入帧的处理信息进行锁存备用,所述替换控制单元与所述信息锁存单元、多级流水线处理单元及计时器连接,所述时戳调整单元的一侧输入端输入系统的实时 6. - A method to achieve accurate clock kind of medium access control protocol module, wherein said module comprises a media access control sub-module interface converter are sequentially connected to each other, Media Independent Interface control sub-module, the rate adjustment module codec and physical sub-module, the method comprising: a control module timestamp of the media access control module time stamps are processed to achieve accurate clock protocol employed, wherein the timestamp control sub-module is provided in the module when the rate adjustment between said sub-module and the physical codec; timestamp said control module comprises: a sending and receiving sub-module sub-module; said sending sub-module comprises a multi-stage pipeline processing unit, the information latch unit replacement control unit, a counter, adjustment means stamp, and cyclic redundancy check register unit, wherein the information processing the information input latch unit latches spare frame, the replacement control information unit and the latch unit, a multi-stage pipelined real time processing means and connected to a timer, said time stamp adjustment unit input terminal side of the system 间,另一侧输入端与所述寄存器连接,所述述时戳调整单元的输出端与所述多级流水线处理单元连接,所述循环冗余码校验单元与所述多级流水线处理单元连接用于对新的帧内容进行重新计算循环冗余码校验的值; 所述接收子模块包括时戳捕获单元,所述时戳捕获单元用于在接收到一个帧开始时, 捕获当前的系统时间。 Between the other side input terminal connected to the register, the timestamp of said adjusting means when the output of the multi-stage pipeline processing unit is connected, the cyclic redundancy check unit and said multi-stage pipeline processing unit connected to recalculate a value for the cyclic redundancy check on the contents of a new frame; stamp when the capture unit comprises a receiving sub-module, the timestamp when capturing unit is configured to start upon receiving a frame, capture the current system time.
  7. 7. 如权利要求6所述的方法,其特征在于: 所述多级流水线处理单元为5级流水线处理单元。 7. The method according to claim 6, wherein: the multi-stage pipeline processing unit is a five-stage pipeline processing unit.
  8. 8. 如权利要求6所述的方法,其特征在于: 所述寄存器存储有用于进行时间戳校准的校准信号,所述校准信号包括标志位和需要进行校准的时间值,所述时戳调整单元根据所述标志位对所述时间戳进行相应时间值的调整。 8. The method according to claim 6, wherein: said register stores a calibration signal for calibrating the time stamp, the calibration signal comprises a flag value and time required for calibration, the time stamp adjustment unit the bit of the flag corresponding to the time stamp adjustment time value.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011082609A1 (en) * 2010-01-05 2011-07-14 Huawei Technologies Co., Ltd. Network timing distribution and synchronization using virtual network delays
CN102132530A (en) * 2008-08-22 2011-07-20 马维尔国际贸易有限公司 Method and apparatus for integrating precise time protocol and media access control security in network elements
CN102299788A (en) * 2011-09-21 2011-12-28 烽火通信科技股份有限公司 Automatic transmission control method and device protocol packets ieee1588
CN104012025A (en) * 2011-11-07 2014-08-27 维特赛半导体公司 Physical layer processing of timestamps and MAC security

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102132530A (en) * 2008-08-22 2011-07-20 马维尔国际贸易有限公司 Method and apparatus for integrating precise time protocol and media access control security in network elements
WO2011082609A1 (en) * 2010-01-05 2011-07-14 Huawei Technologies Co., Ltd. Network timing distribution and synchronization using virtual network delays
CN102299788A (en) * 2011-09-21 2011-12-28 烽火通信科技股份有限公司 Automatic transmission control method and device protocol packets ieee1588
CN104012025A (en) * 2011-11-07 2014-08-27 维特赛半导体公司 Physical layer processing of timestamps and MAC security

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