CN113162626B - High-precision multichannel synchronous high-speed data acquisition and processing system and method - Google Patents
High-precision multichannel synchronous high-speed data acquisition and processing system and method Download PDFInfo
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Abstract
The invention discloses a high-precision multichannel synchronous high-speed data acquisition and processing system and a method, wherein the system comprises a clock distribution calibration source, an ADC data acquisition module, and four modules of ADC data receiving, FIFO data caching, fractional delay filtering and programmable control in an FPGA (field programmable gate array), wherein the clock distribution calibration source generates multichannel synchronous signals and synchronous clocks, and distributes the multichannel synchronous signals and synchronous clocks to the ADC data acquisition module for sampling, and the sampled data is sent to the FIFO data caching module through the ADC data receiving module; the programmable control module performs FFT operation according to the sampling data, extracts the phase difference between each channel and the reference channel through a CORDIC algorithm, calculates the time delay between each channel and the reference channel, and calculates the integer and fractional multiple of the sampling period; the FIFO data cache module and the fractional delay filter sequentially complete the movement of integral multiple and fractional multiple of the sampling period, and finally the multichannel synchronous sequence is obtained. The invention realizes the acquisition and processing of high-precision multi-channel synchronous high-speed data.
Description
Technical Field
The invention belongs to the technical field of multi-channel signal processing, and particularly relates to a high-precision multi-channel synchronous high-speed data acquisition and processing system and method.
Background
The multichannel signal processing technology has wide application in the fields of radar, electronic countermeasure and the like, and with the maturity of the microwave technology and the signal processing technology and the continuous improvement of the process level of high-speed ADC and FPGA devices, higher requirements are also put forward on the multichannel signal processing technology. For example, the increase of the instantaneous bandwidth inevitably requires a higher sampling rate, and the sampling clock frequency and the data output processing speed also need to be correspondingly increased; the requirement of large dynamic range, as the electromagnetic environment becomes more and more complex, designing the receiver of large dynamic range becomes very important, the dynamic range is an important index for measuring the receiver; the requirement of high sensitivity, the higher the sensitivity, means that the receiver has a stronger ability to receive weak signals and can detect a long distance of a target, the sensitivity is another important index of the receiver, however, the large dynamic range and the high sensitivity are a pair of constraints, because they will put opposite requirements on the rf front end, the two indexes need to be considered in balance in the design process of the receiver.
In the field of electronic countermeasure, a multi-channel signal processing technology has a very mature application, but in a direction-finding system of a phase comparison system or a amplitude comparison system, strict requirements are put on the consistency of channels, so that the guarantee of the amplitude consistency among the channels is a key technology. In a direction-finding system of a phase comparison system, if the phase inconsistency among channels exceeds a certain tolerance, a direction-finding result can jump, and even the direction-finding result is completely wrong; in a direction-finding system with an amplitude-comparison system, if the wave beam amplitudes of all channels are inconsistent, misjudgment of the direction wave beam where the target is located can be caused during signal detection, and the direction-finding precision is greatly reduced.
In the field of array signal processing, aperture effect is generated due to inconsistency among channels, so that beam pointing deviates from the pre-control direction, the gain of the main beam direction is reduced, the beam is widened, the sidelobe level is increased and the like. In order to solve the problem caused by this effect, it is necessary to eliminate the inconsistency between the individual channels or to control the inconsistency between the channels within an acceptable range or the like.
In the field of multi-channel signal processing, in order to ensure complete synchronization among channels, although a reference clock line and a signal line can be designed with equal length in hardware design, the reference clock line and the signal line are limited by the limitations of printed circuit board processing technology and design layout and wiring, and the channels cannot be ensured to be completely consistent. Currently, multichannel data acquisition systems are generally synchronized by several methods: firstly, the phase of the sampling reference clock of each channel is respectively adjusted, so that the sampling synchronization among the channels is realized, and the method can only be applied to certain specific occasions, and can only be adjusted in one clock period because the adjusting range is small; secondly, after the FPGA receives the sampling data of the ADC, the FIFO is used for caching at a certain depth, and the number of the moving points of the data in the FIFO is determined by calculating the phase difference between each channel and the reference channel, so that the synchronization among the channels is realized.
Disclosure of Invention
The invention aims to provide a high-precision multichannel synchronous high-speed data acquisition and processing system and method.
The technical solution for realizing the purpose of the invention is as follows: the utility model provides a synchronous high-speed data acquisition processing system of high accuracy multichannel, includes clock distribution calibration source, ADC data acquisition module and FPGA, FPGA includes ADC data receiving module, FIFO data buffer module, mark time delay filtering module and programmable control module, wherein:
the clock distribution calibration source is used for switching the radio frequency switch to a calibration branch or a working branch, generating a multichannel synchronous signal and a synchronous clock and distributing the multichannel synchronous signal and the synchronous clock to the ADC data acquisition module;
the ADC data acquisition module is used for sampling the multichannel synchronous signals to obtain multichannel acquired digital signals and sending the multichannel acquired digital signals to the ADC data receiving module of the FPGA;
the ADC data receiving module is used for receiving the sampling data sent by the ADC data acquisition module and sending the sampling data to the FIFO data cache module;
the FIFO data cache module caches the sampled data, and the FIFO data delay time is controlled by the programmable control module to finish the movement of integral multiples of the sampling period;
the programmable control module is used for respectively carrying out FFT operation according to the obtained sampling data, extracting the phase difference between each channel and the reference channel through a CORDIC algorithm, and then calculating the delay difference of each channel relative to the reference channel, wherein the delay difference consists of integral multiples and fractional multiples of a sampling period;
and the fractional delay filter finishes the movement of fractional times of a sampling period, and finally the data sequence of each channel, namely the multichannel synchronous sequence is obtained.
A high-precision multichannel synchronous high-speed data acquisition and processing method comprises the following steps:
step 3, sampling the multichannel synchronous signals by the ADC data acquisition module to obtain multichannel acquired digital signals, and sending the multichannel acquired digital signals to the ADC data receiving module of the FPGA;
step 4, the ADC data receiving module receives the sampling data sent by the ADC data acquisition module and sends the sampling data to the FIFO data caching module to cache the sampling data;
step 5, the programmable control module respectively performs FFT operation according to the sampling data obtained in the step 4 to calculate I, Q data;
step 6, extracting the phase of each channel through a CORDIC algorithm according to the I/Q data obtained in the step 5, selecting a first channel as a reference channel, calculating the phase difference between each channel and the reference channel, calculating the time delay between each channel and the reference channel according to the phase difference, and calculating the integer multiple and the fractional multiple of the sampling period by utilizing the relation between the sampling period and the time delay of the system;
step 7, according to integer multiple of sampling period, the programmable control module controls output delay corresponding point of FIFO data buffer module of each channel, completes integer multiple movement, obtains sequence after integer multiple movement;
step 8, sending the sequence after the integral multiple movement to a fractional delay filter, looking up a table to obtain the coefficient of the fractional delay filter according to the fractional multiple of the sampling period, and finishing the movement of the fractional multiple;
and 9, moving the sampling data twice to obtain a data sequence of each channel, namely a multichannel synchronous sequence, controlling a radio frequency switch of a clock distribution calibration source by the programmable control module, switching to a working state, beginning to detect and receive external signals, and moving the sampling sequence respectively by adopting the obtained integer multiple and fraction multiple of the sampling period to obtain the multichannel synchronous sampling data.
Compared with the prior art, the invention has the following remarkable advantages:
(1) The method for acquiring and processing the multi-channel synchronous high-speed data has high synchronization precision, not only realizes the synchronization of integral multiple of the sampling period, but also realizes the synchronization of fractional multiple of the sampling period, and has wide application prospect in a signal processing system with high synchronization requirement;
(2) The method for acquiring and processing the multi-channel synchronous high-speed data has high automation degree, is suitable for engineering, is controlled by a programmable control module, automatically trains after the system is started, and switches to a working state after the training is finished;
(3) The invention has flexible design, can design a corresponding fractional delay filter according to the synchronization precision requirement of a multi-channel high-speed data acquisition and processing system, and achieves the aim of high-precision synchronization.
Drawings
FIG. 1 is a block diagram of an implementation of a high-precision multi-channel synchronous high-speed data acquisition processing system and method according to the present invention.
Fig. 2 is a block diagram of the fast FIR fractional delay filter of the present invention.
Fig. 3 is a flow chart of the FFT algorithm of the N-point real sequence of the present invention.
FIG. 4 is a flow chart of a high-precision multi-channel synchronous high-speed data acquisition and processing system and method of the present invention.
Detailed Description
The invention relates to a high-precision multichannel synchronous high-speed data acquisition and processing system and a method thereof.A proper fractional time delay of a sampling period is selected as a stepping time delay according to the requirement of the system synchronous precision, and a fast-running FIR filter is appliedDesigning a fractional delay filter bank, generating filter coefficients and storing the filter coefficients into SDRAM (synchronous dynamic random access memory) of the FPGA; after the system is started, the control module can be programmed to control the clock distribution calibration source to work in a calibration state, the clock distribution calibration source generates a multi-channel calibration signal, and the ADC sampling module sends sampling data to the FPGA through a high-speed serial transmission protocol JESD204B after completing sampling of the calibration signal; secondly, after receiving the sampling data, the FPGA calculates I, Q data dat _ r through N-point FFT operation i [n]And dat _ i i [n]Extracting phase of each channel by using CORDIC algorithm i [n]Selecting the first channel as the reference channel, calculating the phase difference between each channel and the reference channel
Calculating the time delay tau between each channel and the reference channel according to the phase difference i Using the system sampling period and delay tau i The relation between the sampling periods, and the integer multiple k of the sampling periods i And fractional multiple P i (ii) a Finally, the programmable control module controls the FIFO buffer output delay k i Point, complete the movement of the whole number of points, using P i And looking up the table to obtain the coefficient of the fractional delay filter, and finishing the delay of the fractional time. Data sequence x after two time delays i (n-k i T s -P i T s ) Namely a high-precision multichannel synchronous signal, and the system is switched to a working state after the synchronization is finished.
The invention discloses a high-precision multichannel synchronous high-speed data acquisition and processing system, which comprises a clock distribution calibration source, an ADC data acquisition module and an FPGA, wherein the FPGA comprises an ADC data receiving module, an FIFO data cache module, a fraction delay filtering module and a programmable control module, wherein:
the clock distribution calibration source is used for switching the radio frequency switch to a calibration branch or a working branch, generating a multi-channel synchronous signal and a synchronous clock and distributing the multi-channel synchronous signal and the synchronous clock to the ADC data acquisition module;
the ADC data acquisition module is used for sampling the multichannel synchronous signals to obtain multichannel acquired digital signals and sending the multichannel acquired digital signals to the ADC data receiving module of the FPGA;
the ADC data receiving module is used for receiving the sampling data sent by the ADC data acquisition module and sending the sampling data to the FIFO data cache module;
the FIFO data cache module caches the sampled data, and the FIFO data delay time is controlled by the programmable control module to finish the movement of integral multiples of the sampling period;
the programmable control module is used for respectively carrying out FFT operation according to the obtained sampling data, extracting the phase difference between each channel and the reference channel through a CORDIC algorithm, and then calculating the delay difference of each channel relative to the reference channel, wherein the delay difference consists of integral multiples and fractional multiples of a sampling period;
and the fractional delay filter finishes the movement of fractional times of a sampling period, and finally obtains a data sequence of each channel, namely a multi-channel synchronous sequence.
Further, the ADC data acquisition module sends the sampled data to the ADC data receiving module by using a high-speed data serial transfer protocol JESD 204B.
Further, the fractional delay filter is specifically as follows: adopting a fast FIR filter to realize a fractional delay filtering algorithm, selecting
For stepping of the fractional delay filter, a group of filter banks is designed to meet the requirement that the delay time is (-0.5T) s ,0.5T s ]And storing the coefficient production mapping table of the designed filter bank into the SDRAM of the FPGA.
A high-precision multichannel synchronous high-speed data acquisition and processing method comprises the following steps:
step 3, sampling the multichannel synchronous signals by an ADC data acquisition module to obtain multichannel acquired digital signals, and sending the multichannel acquired digital signals to an ADC data receiving module of the FPGA;
step 4, the ADC data receiving module receives the sampling data sent by the ADC data acquisition module and sends the sampling data to the FIFO data caching module to cache the sampling data;
step 5, the programmable control module respectively performs FFT operation according to the sampling data obtained in the step 4 to calculate I, Q data;
step 6, extracting the phase of each channel through a CORDIC algorithm according to the I/Q data obtained in the step 5, selecting a first channel as a reference channel, calculating the phase difference between each channel and the reference channel, calculating the time delay between each channel and the reference channel according to the phase difference, and calculating the integer multiple and the fractional multiple of the sampling period by utilizing the relation between the sampling period and the time delay of the system;
step 7, according to integer multiple of sampling period, the programmable control module controls output delay corresponding point of FIFO data buffer module of each channel, completes integer multiple movement, obtains sequence after integer multiple movement;
step 8, sending the sequence after the integral multiple movement to a fractional delay filter, looking up a table to obtain the coefficient of the fractional delay filter according to the fractional multiple of the sampling period, and finishing the movement of the fractional multiple;
and 9, moving the sampling data twice to obtain a data sequence of each channel, namely a multichannel synchronous sequence, controlling a radio frequency switch of a clock distribution calibration source by the programmable control module, switching to a working state, beginning to detect and receive external signals, and moving the sampling sequences respectively by adopting the integer multiple and the fractional multiple of the sampling period to obtain multichannel synchronous sampling data.
Further, in step 1, according to the synchronization precision requirement and the design principle of the fractional delay filter, a fractional-multiple sampling period step is selected, a group of fractional delay filter banks is designed, and a mapping table is generated for the coefficients of the designed filter banks and stored in the SDRAM of the FPGA, specifically as follows:
adopting a fast FIR filter to realize a fractional delay filtering algorithm, selecting
For stepping of the fractional delay filter, a group of filter banks is designed to meet the requirement that the delay time is (-0.5T) s ,0.5T s ]And storing the coefficient production mapping table of the designed filter bank into the SDRAM of the FPGA.
Further, step 3 the ADC data acquisition module samples the multichannel synchronization signal, and obtains a digital signal after multichannel acquisition and sends the digital signal to the ADC data receiving module of the FPGA, specifically:
the ADC data acquisition module samples the multichannel synchronous signals to obtain digital signals a after multichannel acquisition i (N), i =1,2,3 …, N being the total number of channels; and the ADC data acquisition module transmits the sampling data to the ADC data receiving module by adopting a high-speed data serial transmission protocol JESD 204B.
Further, the programmable control module in step 5 performs FFT operation according to the sampling data obtained in step 4, and calculates I, Q data, specifically as follows:
according to the sampling data ai (N) obtained in the step four, performing N/2-point complex radix-four-FFT operation according to the formula (1), and calculating I, Q data dat _ r by simultaneous formulas (2), (3) and (4) i [n]And dat _ i i [n]：
In the formula X i (k) Representing the N/2 point FFT operation result of the ith channel; x is the number of i (n) denotes a sequence of real numbers a i (n) a complex sequence of (a);
is the rotation operator for calculating FFT; n represents the number of FFT points;
X a (k)＝X a.r (k)+jX a.i (k) (4)
an algorithm for calculating an N-point real sequence FFT by adopting an N/2-point complex sequence FFT is adopted, and an FPGA (field programmable gate array) divides a real number sequence of an N point into an odd sequence and an even sequence of the N/2 point, respectively serving as a real part and an imaginary part of a complex sequence, and then performing the N/2-point complex FFT calculation; wherein
And
is defined as shown in formula (2), X a.r (k) And X a.i (k) Is defined as formula (3), and the real number sequence a is obtained by substituting the result of formula (3) into formula (4) i (N) N-point FFT result, dat _ r i [n]And dat _ i i [n]Are each X a (k) Real and imaginary parts of (c).
Further, in step 6, according to the I/Q data obtained in step 5, the phase of each channel is extracted through the CORDIC algorithm, the first channel is selected as the reference channel, the phase difference between each channel and the reference channel is calculated, the delay between each channel and the reference channel is calculated according to the phase difference, and the integer multiple and the fraction multiple of the sampling period are calculated by using the relationship between the sampling period and the delay of the system, which is specifically as follows:
based on the obtained I/Q data dat _ r i [n]And dat _ i i [n]Extracting phase of each channel by using CORDIC algorithm i [n]Selecting the first channel as a reference channel, and calculating the phase difference between each channel and the first channel according to the formula (5)
According to the formula (6),obtaining the delay difference tau between each channel and the first channel i K is calculated according to the formula (7) i And P i ：
In the formula
Phase difference of each channel and the first channel; phase 1 [n]Representing the phase extracted by the first channel; phase i [n]The phase extracted by the ith channel is represented, and i represents the number of channels;
wherein f represents the frequency of the output calibration signal of the clock calibration source; tau is i Representing the delay of the ith channel and the first channel;
in the formula K i An integer number representing a sampling period; p i The number of the fraction points of the sampling period is represented, and the value range is (-0.5,0.5)]，T s Indicating the sampling period.
Further, in step 7, according to the integer multiple of the sampling period, the programmable control module controls the output delay corresponding point of each channel FIFO data cache module to complete the movement of the integer multiple, so as to obtain a sequence after the movement of the integer multiple, specifically:
the programmable control module controls the corresponding K of the output delay of the FIFO data cache module of each channel i Point, completing integral multiple movement to obtain integral multiple moved sequence x i (n-k i T s )。
Further, step 8, sending the sequence after the integer multiple shift to the fractional delay filter, looking up a table according to the fractional multiple of the sampling period to obtain the coefficient of the fractional delay filter, and completing the shift of the fractional multiple, specifically:
the sampling data x after the time delay of integral multiple of the sampling period i (n-k i T s ) Sending the data to a fractional delay filter, looking up a table to obtain the coefficient of the fractional delay filter according to the fractional multiple of the sampling period, and completing the movement of the fractional multiple to obtain x i (n-k i T s -P i T s )。
The invention is described in further detail below with reference to the figures and the embodiments.
Examples
The invention discloses a high-precision multichannel synchronous high-speed data acquisition and processing system and a method, wherein an implementation block diagram is shown in figure 1, and the specific implementation mode is as follows:
firstly, according to the requirement of synchronous precision of a multi-channel high-speed data acquisition and processing system and the design principle of a fractional delay filter, in order to save computing resources, the invention adopts a fast-running FIR filter to realize a fractional delay filtering algorithm, the algorithm block diagram is shown as figure 2, and the selection is made
For the step of the fractional delay filter, a set of filter banks is designed to meet the requirement that the delay time is (-0.5T) s ,0.5T s ]And storing the coefficient production mapping table of the designed filter bank into the SDRAM of the FPGA.
And secondly, after the multichannel high-speed data acquisition and processing system is started, the programmable control module controls the working state to be a training mode, at the moment, the clock distribution calibration source switches the radio frequency switch to the calibration branch, and the calibration source generates multichannel synchronous signals and synchronous clocks and distributes the multichannel synchronous signals and synchronous clocks to the ADC data acquisition module.
Thirdly, completing the initialization setting of ADC data acquisition, sampling the multichannel synchronous signals to obtain the digital signals a after multichannel acquisition i (n), the ADC data acquisition module transmits the sampled data to the FPGA by adopting a high-speed data serial transmission protocol JESD 204B.
Fourth step, FPGA samplingReceiving the sampling data a by a high-speed data serial protocol JESD204B i And (n) buffering the sampled data through a FIFO data buffering module, wherein the FIFO data delay time is controlled by a programmable control module.
A fifth step of programmable control module, based on the sampling data a obtained in the fourth step i (N) performing N/2-point complex 'radix-four-FFT' operation according to the formula (1), and calculating I (in-phase) data dat _ r and Q (quadrature) data dat _ r by combining the formulas (2), (3) and (4) i [n]And dat _ i i [n]。
In the formula X i (k) Representing the N/2 point FFT operation result of the ith channel;
in the formula x i (n) denotes a sequence of real numbers a i (n) a complex sequence of (a);
in the formula
Is the rotation operator for calculating the FFT;
in the formula, N represents the number of FFT points, and the value is 32 in the invention;
the invention adopts an algorithm of N/2-point complex sequence FFT to calculate N-point real sequence FFT, and an FPGA divides a real number sequence of N points into an odd sequence and an even sequence of N/2 points, which are respectively used as a real part and an imaginary part of a complex number sequence, and then performs N/2-point complex FFT calculation. The algorithm flow chart is shown in FIG. 3, where
And
is defined as shown in formula (2), X a.r (k) And X a.i (k) The definition of (2) is shown in formula (3), and the real number sequence a can be obtained by substituting the result of formula (3) into formula (4) i (N) N-point FFT result, dat _ r i [n]And dat _ i i [n]Are each X a (k) Real and imaginary parts of (c).
X a (k)＝X a.r (k)+jX a.i (k) (4)
Sixthly, the programmable control module obtains the I/Q data dat _ r according to the step five i [n]And dat _ i i [n]Extracting phase of each channel by using CORDIC algorithm i [n]Selecting the first channel as the reference channel, and calculating the phase difference between each channel and the first channel according to the formula (5)
Obtaining the delay difference tau between each channel and the first channel according to the formula (6) i K is calculated according to the formula (7) i And P i 。
In the formula
Phase difference of each channel and the first channel; phase 1 [n]Representing the phase extracted by the first channel; phase i [n]Represents the phase extracted by the ith channel;
wherein i represents the number of channels;
wherein f represents the frequency of the output calibration signal of the clock calibration source;
in the formula tau i Representing the delay of the ith channel and the first channel;
in the formula K i An integer number representing a sampling period; p i The number of the fraction points of the sampling period is represented, and the value range is (-0.5,0.5)]；T s Represents a sampling period;
step seven, obtaining K according to the step six i The programmable control module controls the corresponding K for the movement of the FIFO data cache module of each channel i Point, finishing the movement of the integral multiple of the sampling period to obtain the moved data xi (n-k) i T s )。
Eighth step, the P obtained in the sixth step i Looking up the table to obtain the coefficient of the fractional delay filter, and delaying the seven steps by integral multiple of the sampling period by adopting the data x i (n-k i T s ) Performing a delay filter to complete point movement of fractional times of a sampling period to obtain x i (n-k i T s -P i T s )。
Ninthly, accurately moving the sampling data through the steps to obtain a data sequence xi (n-k) of each channel i T s -P i T s ) Namely a high-precision multi-channel synchronous sequence, the programmable control module controls the radio frequency switch of the clock distribution calibration source, switches to the working state, starts to detect and receive external signals, and adopts the K obtained by the training i And P i The sampling sequences are respectively moved to obtain high-precision multichannel synchronous sampling data, and a flow chart is shown in figure 4, so that the high-precision multichannel synchronous high-speed data acquisition and processing process is completed.
The method for acquiring and processing the multichannel synchronous high-speed data has high synchronization precision, not only realizes the synchronization of integral multiple of the sampling period, but also realizes the synchronization of integral multiple of the sampling period, and has wide application prospect in a signal processing system with high synchronization requirement; the method for acquiring and processing the multi-channel synchronous high-speed data has high automation degree, is suitable for engineering, is controlled by a programmable control module, automatically trains after the system is started, and switches to a working state after the training is finished; the invention has flexible design, can design a corresponding fractional delay filter according to the synchronization precision requirement of a multi-channel high-speed data acquisition and processing system, and achieves the aim of high-precision synchronization.
Claims (10)
1. The utility model provides a high accuracy multichannel synchronization high speed data acquisition processing system which characterized in that, includes clock distribution calibration source, ADC data acquisition module and FPGA, FPGA includes ADC data receiving module, FIFO data buffer module, fraction time delay filtering module and programmable control module, wherein:
the clock distribution calibration source is used for switching the radio frequency switch to a calibration branch or a working branch, generating a multi-channel synchronous signal and a synchronous clock and distributing the multi-channel synchronous signal and the synchronous clock to the ADC data acquisition module;
the ADC data acquisition module is used for sampling the multichannel synchronous signals to obtain multichannel acquired digital signals and sending the multichannel acquired digital signals to the ADC data receiving module of the FPGA;
the ADC data receiving module is used for receiving the sampling data sent by the ADC data acquisition module and sending the sampling data to the FIFO data cache module;
the FIFO data cache module caches the sampled data, and the FIFO data delay time is controlled by the programmable control module to finish the movement of integral multiples of the sampling period;
the programmable control module is used for respectively carrying out FFT operation according to the obtained sampling data, extracting the phase difference between each channel and the reference channel through a CORDIC algorithm, and then calculating the delay difference of each channel relative to the reference channel, wherein the delay difference consists of integral multiples and fractional multiples of a sampling period;
and the fractional delay filter finishes the movement of fractional times of a sampling period, and finally obtains a data sequence of each channel, namely a multi-channel synchronous sequence.
2. The high-precision multichannel synchronous high-speed data acquisition and processing system as claimed in claim 1, wherein the ADC data acquisition module adopts a high-speed data serial transmission protocol JESD204B to send the sampled data to the ADC data receiving module.
3. The high-precision multi-channel synchronous high-speed data acquisition and processing system according to claim 1, wherein the fractional delay filter is specifically as follows: adopting a fast FIR filter to realize a fractional delay filtering algorithm, selecting
For the step of the fractional delay filter, a set of filter banks is designed to meet the delay time at
And storing the coefficient production mapping table of the designed filter bank into the SDRAM of the FPGA.
4. A high-precision multichannel synchronous high-speed data acquisition and processing method is characterized by comprising the following steps:
step 1, selecting fractional time sampling period stepping according to a synchronous precision requirement and a design principle of a fractional time delay filter, designing a group of fractional time delay filter banks, generating a mapping table from coefficients of the designed filter banks, and storing the mapping table into an SDRAM (synchronous dynamic random access memory) of an FPGA (field programmable gate array);
step 2, after the system is started, the programmable control module controls the working state to be a training mode, and at the moment, the clock distribution calibration source switches the radio frequency switch to a calibration branch to generate a multi-channel synchronous signal and a synchronous clock, and distributes the multi-channel synchronous signal and the synchronous clock to the ADC data acquisition module;
step 3, sampling the multichannel synchronous signals by an ADC data acquisition module to obtain multichannel acquired digital signals, and sending the multichannel acquired digital signals to an ADC data receiving module of the FPGA;
step 4, the ADC data receiving module receives the sampling data sent by the ADC data acquisition module and sends the sampling data to the FIFO data caching module to cache the sampling data;
step 5, the programmable control module respectively performs FFT operation according to the sampling data obtained in the step 4 to calculate I, Q data;
step 6, extracting the phase of each channel through a CORDIC algorithm according to the I/Q data obtained in the step 5, selecting a first channel as a reference channel, calculating the phase difference between each channel and the reference channel, calculating the time delay between each channel and the reference channel according to the phase difference, and calculating the integer multiple and the fractional multiple of the sampling period by utilizing the relation between the sampling period and the time delay of the system;
step 7, according to integer multiple of sampling period, the programmable control module controls output delay corresponding point of FIFO data buffer module of each channel, completes integer multiple movement, obtains sequence after integer multiple movement;
step 8, sending the sequence after the integral multiple movement to a fractional delay filter, looking up a table to obtain the coefficient of the fractional delay filter according to the fractional multiple of the sampling period, and finishing the movement of the fractional multiple;
and 9, moving the sampling data twice to obtain a data sequence of each channel, namely a multichannel synchronous sequence, controlling a radio frequency switch of a clock distribution calibration source by the programmable control module, switching to a working state, beginning to detect and receive external signals, and moving the sampling sequence respectively by adopting the obtained integer multiple and fraction multiple of the sampling period to obtain the multichannel synchronous sampling data.
5. The high-precision multichannel synchronous high-speed data acquisition and processing method according to claim 4, wherein in step 1, according to the synchronous precision requirement and the design principle of the fractional delay filter, fractional-time sampling period stepping is selected, a group of fractional delay filter banks is designed, and the coefficients of the designed filter banks are generated into a mapping table and stored in the SDRAM of the FPGA, specifically as follows:
adopting a fast FIR filter to realize a fractional delay filtering algorithm, selecting
For the step of the fractional delay filter, a set of filter banks is designed to meet the delay time at
And storing the coefficient production mapping table of the designed filter bank into the SDRAM of the FPGA.
6. The high-precision multichannel synchronous high-speed data acquisition and processing method according to claim 5, wherein the ADC data acquisition module in step 3 samples multichannel synchronous signals to obtain multichannel acquired digital signals, and the multichannel acquired digital signals are sent to an ADC data receiving module of the FPGA, and specifically the method comprises the following steps:
the ADC data acquisition module samples the multichannel synchronous signals to obtain multichannel acquired digital signals ai (N), wherein i =1,2,3 …, and N is the total number of channels; and the ADC data acquisition module transmits the sampling data to the ADC data receiving module by adopting a high-speed data serial transmission protocol JESD 204B.
7. The method according to claim 6, wherein the programmable control module in step 5 performs FFT operation according to the sampled data obtained in step 4 to calculate I, Q data, specifically as follows:
performing N/2-point complex radix-Quadrature Fourier transform (FFT) operation according to the formula (1) according to the sampling data ai (N) obtained in the fourth step, and calculating I, Q data dat _ ri [ N ] and dat _ ii [ N ] by combining the formulas (2), (3) and (4):
in the formula X i (k) Representing the N/2 point FFT operation result of the ith channel; x is the number of i (n) denotes a sequence of real numbers a i (n) a complex sequence of (a);
is the rotation operator for calculating the FFT; n represents the number of FFT points;
X a (k)＝X a.r (k)+jX a.i (k) (4)
an algorithm for calculating an N-point real sequence FFT by adopting an N/2-point complex sequence FFT is adopted, and an FPGA (field programmable gate array) divides a real number sequence of an N point into an odd sequence and an even sequence of the N/2 point, respectively serving as a real part and an imaginary part of a complex sequence, and then performing the N/2-point complex FFT calculation; wherein
And
is defined as shown in formula (2), X a.r (k) And X a.i (k) Is defined as formula (3), and the real number sequence a is obtained by substituting the result of formula (3) into formula (4) i (N) N-point FFT result, dat _ r i [n]And dat _ i i [n]Are each X a (k) Real and imaginary parts of (c).
8. The method as claimed in claim 7, wherein in step 6, according to the I/Q data obtained in step 5, the phase of each channel is extracted by CORDIC algorithm, the first channel is selected as a reference channel, the phase difference between each channel and the reference channel is calculated, the delay between each channel and the reference channel is calculated according to the phase difference, and the integer multiple and the fractional multiple of the sampling period are obtained by using the relationship between the sampling period and the delay of the system, specifically as follows:
based on the obtained I/Q data dat _ r i [n]And dat _ i i [n]Extracting phase of each channel by using CORDIC algorithm i [n]Selecting the first channel as the reference channel, and calculating the channels according to the formula (5)Phase difference between track and first channel
Obtaining the delay difference tau between each channel and the first channel according to the formula (6) i K is calculated according to the formula (7) i And P i ：
In the formula
Phase difference of each channel and the first channel; phase 1 [n]Representing the phase extracted by the first channel; phase i [n]The phase extracted by the ith channel is represented, and i represents the number of channels;
wherein f represents the frequency of the output calibration signal of the clock calibration source; tau is i Representing the delay of the ith channel and the first channel;
in the formula K i An integer number representing a sampling period; p i The number of the fraction points of the sampling period is represented, and the value range is (-0.5,0.5)]，T s Representing the sampling period.
9. The method as claimed in claim 8, wherein in step 7, the programmable control module controls the output delay of the FIFO data buffer modules of each channel according to the integer multiple of the sampling period to complete the shift of the integer multiple, and obtain the sequence after the shift of the integer multiple, specifically:: i
The programmable control module controls the corresponding K of the output delay of the FIFO data buffer module of each channel i Point, finishing integral multiple movement to obtain sequence x after integral multiple movement i (n-k i T s )。
10. The method according to claim 9, wherein step 8 is to send the sequence after the integer multiple shift to a fractional delay filter, look up a table according to the fractional multiple of the sampling period to obtain the coefficient of the fractional delay filter, and complete the shift of the fractional multiple, and specifically:
the sampling data x after the time delay of integral multiple of the sampling period i (n-k i T s ) Sending the data to a fractional delay filter, looking up a table to obtain the coefficient of the fractional delay filter according to the fractional multiple of the sampling period, and completing the movement of the fractional multiple to obtain x i (n-k i T s -P i T s )。
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