CN108574459B - Efficient time domain broadband beam forming circuit and method - Google Patents
Efficient time domain broadband beam forming circuit and method Download PDFInfo
- Publication number
- CN108574459B CN108574459B CN201710151095.0A CN201710151095A CN108574459B CN 108574459 B CN108574459 B CN 108574459B CN 201710151095 A CN201710151095 A CN 201710151095A CN 108574459 B CN108574459 B CN 108574459B
- Authority
- CN
- China
- Prior art keywords
- delay
- module
- channel
- digital
- coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H2017/0072—Theoretical filter design
- H03H2017/0081—Theoretical filter design of FIR filters
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Filters That Use Time-Delay Elements (AREA)
Abstract
The invention discloses a high-efficiency time domain broadband beam forming circuit adopting a cascade FIR transverse filtering structure, which consists of N channel delay and equalization modules, 1 data synthesis module and 1 digital low-pass filtering and channel equalizer coefficient calculation module. Each channel delay and equalization module consists of a variable integer/fraction delay module, a digital down-conversion module, a digital low-pass filtering and channel equalization integrated module. The invention realizes the functions of the digital down-conversion low-pass filter and the channel equalization filter by jointly optimizing the coefficients of the two filters and only using one variable coefficient FIR filter, thereby effectively reducing the resource consumption. The invention adopts a cascaded FIR transverse filtering structure, effectively reduces resource consumption by a time delay function preposition and FIR filter combined optimization technology, efficiently realizes time domain broadband beam forming and channel equalization functions, and can be widely applied to systems such as radar broadband digital beam forming, microphone arrays, sonar arrays and the like.
Description
Technical Field
The invention belongs to the field of broadband array signal processing, and particularly relates to a high-efficiency time domain broadband beam forming circuit and method adopting a cascaded FIR transverse filtering structure.
Background
The digital beam forming is that a plurality of sensors arranged at different positions in space form a sensor array to collect signals, and then an expected directional diagram is formed in a digital domain through a digital beam forming algorithm, so that the quality of useful signals is improved in a space domain, and interference signals are suppressed.
The basic principle of digital beam forming is to control the time delay of signals in an array to offset the time delay of signals from different directions in space, so that the signals among array elements can be added in phase, and beam pointing and directional gain can be obtained. Since most of the conventional digital array systems are narrow-band systems with relatively small variation of the transmitting and receiving frequencies, phase control can be used to approximately replace delay control. However, for a wideband digital array system, if the technical means of phase control is used to approximately replace delay control, the delay time corresponding to the same phase within a larger frequency band will have a larger difference, and the in-array delay generated by the signal cannot cancel the spatial delay of the signal within the whole bandwidth, so that the beam direction of the antenna is shifted, the directional gain of the antenna is reduced, and the wide-angle scanning is more serious. This phenomenon is called aperture effect in phased array antennas, and the method for solving the aperture effect is to use direct delay control instead of indirect phase control.
The broadband digital array system has a large working bandwidth, and requires the array antenna and each radio frequency component to have a large bandwidth. Differences in the characteristics of the analog devices and the circuits they make up can cause the channels to exhibit inconsistent amplitude and phase characteristics with frequency, commonly referred to as channel mismatch. Channel mismatch is an important error of a Wideband digital array radar, and can generate large influence on Wideband Digital Beamforming (WDBF), pulse compression, side lobe cancellation, and the like, and a channel equalization filter needs to be inserted into each channel to compensate for the amplitude-phase error related to frequency.
The existing time-domain delay-based broadband digital beam forming circuit and method generally aim at the broadband beam forming application of fixed beam pointing, cannot quickly and flexibly adjust beam pointing, do not consider the practical problem of joint optimization with a channel equalization technology, and have complex structure.
Disclosure of Invention
The invention aims to provide a high-efficiency time domain broadband beam forming circuit and method adopting a cascade FIR transverse filtering structure.
The technical solution for realizing the purpose of the invention is as follows: a high-efficiency time domain broadband beam forming circuit adopting a cascaded FIR transverse filtering structure comprises N channel delay and equalization modules, 1 data synthesis module and 1 digital low-pass filtering and channel equalizer coefficient calculation module, wherein the N channel delay and equalization modules are all connected with the data synthesis module and transmit processed data to the data synthesis module, each channel delay and equalization module comprises a variable integer/fractional delay module, a digital down-conversion module and a digital low-pass filtering and channel equalization integrated module which are sequentially connected, the variable integer/fractional delay module transmits delayed data to the digital down-conversion module, the digital down-conversion module transmits orthogonal baseband data to the digital low-pass filtering and channel equalization integrated module, and the down-conversion digital module also transmits the data to the digital low-pass filtering and channel equalizer coefficient calculation module, and the digital low-pass filtering and channel equalizer coefficient calculating module transmits the calculated filter coefficient to the digital low-pass filtering and channel equalization integrated module.
A working method based on the circuit comprises three working modes, namely: the method comprises an initialization mode, a channel equalization mode and a normal working mode, wherein the initialization mode comprises the following steps:
the channel equalization mode comprises the following steps:
a, a digital low-pass filtering and channel equalizer coefficient calculating module calculates the equalizer amplitude-phase characteristics of each channel by adopting a frequency domain channel equalization method according to the output data of each channel digital down-conversion module;
b, multiplying the amplitude-phase characteristic of each channel equalizer obtained in the step A by the amplitude-phase characteristic of an ideal digital low-pass filter by a digital low-pass filtering and channel equalizer coefficient calculating module to obtain the combined amplitude-phase characteristic of each channel, and respectively optimizing the coefficient of the P-order digital low-pass filter of each channel to approximate to the respective combined amplitude-phase characteristic;
setting the coefficient of a variable coefficient FIR filter of each channel digital low-pass filtering and channel equalization integrated module as a corresponding P-order optimization coefficient;
the normal operation mode comprises the following execution steps:
step a, calculating delay values of all channels according to the requirement of the change of the beam pointing direction, converting the delay values into integral multiples of clock periods and fractional time delays, and adjusting in real time;
b, setting the integral multiple of the clock period and the fractional multiple delay of each channel variable integer/fractional delay module according to the result;
c, each module of the whole circuit works by adopting a parallel pipeline structure, namely, data is delayed for a corresponding clock period through a variable integer/fraction delay module; the delayed data enters a digital down-conversion module again to become I/Q data of baseband quadrature; the I/Q data with orthogonal baseband is processed by a digital low-pass filtering and channel equalization integrated module to obtain broadband beam forming data with low data rate; the broadband beam forming data enters a data synthesis module and a beam is output.
Compared with the prior art, the invention has the following advantages: 1) the high-efficiency time domain broadband beam forming circuit adopting the cascade FIR transverse filtering structure can realize real-time broadband digital beam forming, effectively solve the problem of broadband beam directional diagram distortion caused by aperture effect and compensate mismatch among channels. 2) The digital processing circuit suitable for engineering realization adopts a cascade FIR transverse filtering structure to realize high-efficiency time domain broadband beam forming and broadband equalization among channels, and effectively reduces resource consumption by adopting a delay function preposition and FIR filter integrated design optimization technology. 3) The invention can be widely applied to radar digital array antenna, communication intelligent antenna, microphone array, sonar array and other systems.
Drawings
FIG. 1 is a general block diagram of the digital processing circuit of the present invention.
FIG. 2 is a detailed block diagram of the modules developed in FIG. 1 for the present invention.
FIG. 3 is a diagram of the mean square error of the amplitude-frequency response and the mean square error of the delay amount of the variable fractional delay Farrow filter, and the number of the sets and the order thereof, wherein a) is the relation of the mean square error of the amplitude-frequency response and the number of the sets and the order thereof of the Farrow filter, and b) is the relation of the mean square error of the delay amount of the Farrow filter, and the number of the sets and the order thereof.
Fig. 4 is a block diagram of the internal structure of a variable fractional delay Farrow filter 1112 for providing fractional delay to the variable integer/fractional delay module 111 shown in fig. 2 according to the present invention.
Fig. 5 is a diagram illustrating an implementation and interconnection relationship of parts of the digital down-conversion module 112 and the digital low-pass filtering and channel equalization integration module 113 shown in fig. 2 according to the present invention.
Fig. 6 shows an implementation of the digital low-pass FIR filter and equalizer synthesis optimization for the digital low-pass and channel equalization 330 of fig. 5 of the present invention.
Detailed Description
The invention provides a digital time domain delay and digital channel balanced broadband beam forming circuit for solving the problems of aperture effect and channel mismatch in a broadband digital array radar, realizes accurate beam pointing and compensates mismatch between channels. The circuit adopts a cascaded FIR transverse filtering structure to realize efficient time domain broadband beam forming and broadband balance among channels, and effectively reduces resource consumption through the integrated design of partial circuits.
The invention adopts a high-efficiency time domain broadband beam forming circuit with a cascade FIR transverse filtering structure, which consists of N channel delay and equalization modules, 1 data synthesis module and 1 digital low-pass filtering and channel equalizer coefficient calculation module, wherein each channel delay and equalization module consists of a variable integer/fractional delay module, a digital down-conversion module and a digital low-pass filtering and channel equalization integrated module. The integral multiple time delay of the variable clock period of the variable integer/fraction time delay module is realized by an FIFO (first in first out) structure, and the fractional time delay of the variable clock period adopts a Farrow filter; the digital down-conversion module adopts an orthogonal digital down-conversion method to periodically take the original value, zero and negate the original value of the original data; the digital low-pass filtering and channel equalization integrated module adopts a variable coefficient FIR filter to realize the functions of low-pass filtering and channel equalization.
The invention discloses a working method of a high-efficiency time domain broadband beam forming circuit adopting a cascade FIR transverse filtering structure, which comprises three working modes, namely:
1. an initialization mode: setting a fixed coefficient of a variable fractional delay Farrow filter of the variable integer/fractional delay module, setting a coefficient of a variable coefficient FIR filter of the digital low-pass filtering and channel equalization integrated module as a coefficient of a P-order digital low-pass filter, and simultaneously setting the integral multiple of the clock period and the fractional time delay of the variable integer/fractional delay module as 0.
2. Channel equalization mode: the digital low-pass filtering and channel equalizer coefficient calculating module calculates the equalizer amplitude-phase characteristics of each channel, the equalizer amplitude-phase characteristics and the equalizer amplitude-phase characteristics of the digital low-pass filters are synthesized to obtain combined amplitude-phase characteristics, the P-order digital low-pass filter coefficients of each channel are respectively optimized to approximate the respective combined amplitude-phase characteristics, and the optimized coefficients are arranged in the variable coefficient FIR filter of the digital low-pass filtering and channel equalization integrated module of each channel.
3. And (3) a normal working mode: setting the integral multiple of clock period and fractional time delay of each channel variable integer/fractional time delay module calculated according to the requirement of the change of the beam pointing direction, wherein each module of the whole circuit works by adopting a parallel pipeline structure, namely, data firstly passes through the variable integer/fractional time delay module to delay corresponding clock period, then enters the digital down-conversion module to be changed into I/Q data with orthogonal base bands, then passes through the digital low-pass filtering and channel balancing integrated module to obtain broadband beam forming data with low data rate, and finally enters the data synthesis module to output beams.
As described in more detail below.
A high-efficiency time domain broadband beam forming circuit adopting a cascaded FIR transverse filtering structure comprises N channel delay and equalization modules, 1 data synthesis module and 1 digital low-pass filtering and channel equalizer coefficient calculation module, wherein the N channel delay and equalization modules are all connected with the data synthesis module and transmit processed data to the data synthesis module, each channel delay and equalization module comprises a variable integer/fractional delay module, a digital down-conversion module and a digital low-pass filtering and channel equalization integrated module which are sequentially connected, the variable integer/fractional delay module transmits delayed data to the digital down-conversion module, the digital down-conversion module transmits orthogonal baseband data to the digital low-pass filtering and channel equalization integrated module, and the down-conversion digital module also transmits the data to the digital low-pass filtering and channel equalizer coefficient calculation module, and the digital low-pass filtering and channel equalizer coefficient calculating module transmits the calculated filter coefficient to the digital low-pass filtering and channel equalization integrated module.
The variable integer/fraction delay module comprises an integer delay unit and a fraction delay unit which are sequentially connected, wherein the integer delay unit adopts an FIFO structure to realize variable clock cycle integral multiple delay, and the fraction delay unit adopts a Farrow filter to realize variable clock cycle fractional multiple delay.
The digital low-pass filtering and channel equalization integrated module adopts a variable coefficient FIR filter and is used for realizing low-pass filtering extraction and channel equalization.
Preferably, the variable integer/fractional delay module is configured to write data of each channel into a respective FIFO for buffering, and implement variable integer multiple delay of clock cycle by controlling the clock cycle delay amount of data read at the output end of the FIFO structure; the module optimizes the Farrow filter structure and the related coefficient thereof according to the delay precision and the delay error requirement in the bandwidth, and realizes variable clock period fractional time delay by adjusting the fractional delay parameter of the Farrow filter in the using process.
The digital down-conversion module is realized by the following modes: when sampling frequency fsSum signal center frequency f0Satisfy fs＝4f0Or 3fs＝4f0In the process, the orthogonal down-conversion local oscillation sequence only needs to periodically select three values of-1, 0 and 1, namely, the original data is periodically subjected to operations of taking the original value, taking zero and taking the inverse, so that the digital down-conversion function can be realized.
Preferably, the implementation scheme of the digital low-pass filtering and channel equalization integrated module is as follows: and performing joint optimization by using a digital low-pass filtering and channel equalizer coefficient calculation module according to the synthetic amplitude-phase characteristics of the P-order digital low-pass filter and the equalizer to obtain a filter coefficient, and realizing the functions of low-pass filtering and channel equalization by using a P-order variable coefficient FIR filter.
A working method based on the circuit comprises three working modes, namely: the method comprises an initialization mode, a channel equalization mode and a normal working mode, wherein the initialization mode comprises the following steps:
the channel equalization mode comprises the following steps:
a, a digital low-pass filtering and channel equalizer coefficient calculating module calculates the equalizer amplitude-phase characteristics of each channel by adopting a frequency domain channel equalization method according to the output data of each channel digital down-conversion module;
b, multiplying the amplitude-phase characteristic of each channel equalizer obtained in the step A by the amplitude-phase characteristic of an ideal digital low-pass filter by a digital low-pass filtering and channel equalizer coefficient calculating module to obtain the combined amplitude-phase characteristic of each channel, and respectively optimizing the coefficient of the P-order digital low-pass filter of each channel to approximate to the respective combined amplitude-phase characteristic;
setting the coefficient of a variable coefficient FIR filter of each channel digital low-pass filtering and channel equalization integrated module as a corresponding P-order optimization coefficient;
the normal operation mode comprises the following execution steps:
step a, calculating delay values of all channels according to the requirement of the change of the beam pointing direction, converting the delay values into integral multiples of clock periods and fractional time delays, and adjusting in real time; the formula for calculating the delay value of each channel according to the requirement of the change of the beam pointing direction is as follows:
τn＝nd sinθ0/c n＝1,2,...,N
wherein d represents the array element spacing, θ0Denotes the beam pointing direction, c denotes the speed of the electromagnetic wave propagating in the vacuum, N denotes the number of channels, τnIndicating the delay value of the nth lane.
B, setting the integral multiple of the clock period and the fractional multiple delay of each channel variable integer/fractional delay module according to the result;
c, each module of the whole circuit works by adopting a parallel pipeline structure, namely, data is delayed for a corresponding clock period through a variable integer/fraction delay module; the delayed data enters a digital down-conversion module again to become I/Q data of baseband quadrature; the I/Q data with orthogonal baseband is processed by a digital low-pass filtering and channel equalization integrated module to obtain broadband beam forming data with low data rate; the broadband beam forming data enters a data synthesis module and a beam is output.
The high-efficiency time domain broadband beam forming circuit adopting the cascade FIR transverse filtering structure can realize real-time broadband digital beam forming, effectively solve the problem of broadband beam directional diagram distortion caused by aperture effect and compensate mismatch among channels.
The present invention will be described in further detail with reference to examples.
Example 1
The invention provides a high-efficiency time domain broadband wave beam forming digital processing circuit adopting a cascaded FIR transverse filtering structure aiming at the problems of inaccurate wave beam pointing and mismatch among channels caused by an aperture effect, thereby realizing the broadband wave beam forming with accurate wave beam pointing and compensating the mismatch among the channels. Fig. 1 shows a general block diagram of a digital processing circuit, and fig. 2 shows a detailed block diagram of each module, all logic functions of the circuit can be implemented in a single-chip FPGA, and mainly implement functions of digital time domain delay, digital down conversion, filtering extraction, channel equalization, beam forming, and the like. The circuit consists of N channel delay and equalization modules 110, 1 data synthesis module 120, and 1 digital low pass filter and channel equalizer coefficient calculation module 130. Each channel delay and equalization module 110 is composed of a variable integer/fractional delay module 111, a digital down-conversion module 112, and a digital low-pass filtering and channel equalization integrated module 113.
The structure of a commonly used broadband digital beam forming and channel equalizing circuit is that data is converted into two paths of baseband orthogonal I/Q data after down-conversion and filtering extraction, and then the mismatch between channels is equalized through a complex equalizer. On the basis, the equalized data can be processed by a variable integer/fractional delay module to complete the broadband beam forming.
However, the above structure has the following two problems: 1) after digital down conversion, the I/Q two paths of data need to be filtered and extracted, each path of each path needs to use a digital low-pass FIR filter, and the nature of the equalizer is also the FIR filter, although the functions are different, the structure is repeated; 2) time-domain delay broadband beam forming is performed after equalization, which means that two I/Q branches of each channel need to be connected with a variable integer/fractional delay module, and resource consumption is large.
In order to efficiently realize the time delay broadband beam forming and the channel equalization, the invention corrects the structure. 1) The digital low-pass FIR filter and the equalizer are subjected to synthesis optimization design and are realized by adopting a variable coefficient FIR filter. 2) The variable integer/fractional delay module is adjusted before quadrature down-conversion and digital filtering decimation. The delay amount of the variable integer/fractional delay module can be controlled, so that the delay amount of the variable integer/fractional delay module of each channel can be set to be 0 when channel equalization is carried out, and the mismatch among the channels is only inherent inconsistency among the channels. The number of the variable integer/fractional delay modules of each channel is reduced from two to one, so that the use of resources is reduced.
Variable integer/fractional delay module 111: the processing method for the variable clock period integral multiple time delay is to write the data of each channel into the FIFO structure 1111 for caching, and is realized by controlling the clock period time delay of the data read at the output end of the FIFO structure 1111; the variable fractional delay of the clock cycle is realized by a variable fractional delay Farrow filter 1112, and the Farrow filter 1112 is optimized according to the set delay precision and the delay error requirement in the bandwidth, and is realized by adjusting the fractional delay parameter.
Digital down-conversion module 112: digital down-conversion is achieved using a quadrature digital down-conversion, DDC, method 1121. The calculation formulas of the sequence values of the orthogonal digital down-conversion local oscillation are respectively
When sampling frequency fsSum signal center frequency f0Satisfy fs＝4f0Or 3fs＝4f0In the process, the orthogonal digital down-conversion local oscillation sequence formulas (1) and (2) only need to periodically select three values of-1, 0 and 1, so that the processing process of the orthogonal digital down-conversion is simplified into the operation of periodically selecting an original value, zero and negation for original data.
The digital low-pass filtering and channel equalization integrated module 113: to reduce the data rate, the digital down-conversion is followed by a filtering decimation. Since an equalizer needs to be inserted into each channel to compensate for mismatch between the channels, the equalizer is combined with a digital low-pass FIR filter of P order after digital down-conversion, and the combination is implemented by using a FIR filter of P order variable coefficients, and the coefficients of the FIR filter are initialized to the coefficients of the digital low-pass FIR filter. And when the channel is equalized, the coefficient of the channel is the optimized P-order digital low-pass FIR filter coefficient.
The data synthesis module 120: this module completes the summation operation of the wideband beamforming data for each channel to obtain the beam output 104.
Digital low pass filtering and channel equalizer coefficient calculation module 130: the module converts the amplitude-phase characteristic H of each channel equalizereqAmplitude-phase characteristic H of (omega) and digital low-pass FIR filterFIRAnd (omega) obtaining the combined amplitude-phase characteristics of each channel according to the formula (3), and optimizing the P-order digital low-pass FIR filter coefficient of each channel to enable the coefficient to approach the respective combined amplitude-phase characteristics.
H(ω)＝Heq(ω)HFIR(ω) (3)
The digital processing circuit suitable for engineering realization adopts a cascade FIR transverse filtering structure to realize high-efficiency time domain broadband beam forming and broadband equalization among channels, and effectively reduces resource consumption by adopting a delay function preposition and FIR filter integrated design optimization technology.
Example 2
Sampling frequency fs200MHz, the echo signal is a broadband swept frequency signal with a center frequency f050MHz, and 30MHz bandwidth B. The working method of the invention comprises an initialization mode, a channel equalization mode and a normal working mode.
The steps of initializing the mode are:
according to the central frequency and the sampling frequency of the signal, the ideal amplitude-frequency response of the Farrow filter is constant and the phase-frequency response is linear phase within the range of the digital angular frequency omega epsilon [0.35 pi, 0.65 pi ]. The mean square error of amplitude-frequency response in the bandwidth is required to be better than 0.1dB, and the mean square error of delay quantity is required to be better than 10 ps.
Fig. 3a) and b) respectively show the relationship between the amplitude-frequency response mean square error and the delay amount mean square error of the variable fractional delay Farrow filter and the group number and the order thereof. On the premise of meeting the performance requirement, the resource consumption is reduced as much as possible, 7 groups of Farrow filters with 6 orders are selected, and the structural block diagram is shown in fig. 4. The FIR filters 228-221 forming the Farrow filter are arranged in the sequence of FIR 7-FIR 0, and the coefficient of each FIR filter is configured with the calculated coefficient, which is listed in table 1, and only needs to be configured once and called by IP core. The Farrow filters of the N channels have the same structure and coefficient, and the difference between the Farrow filters is that the delay control parameter p260 is different.
TABLE 17 set of 6 th order Farrow filter coefficients
fig. 5 shows an implementation scheme and interconnection relationship of the digital down-conversion module 112 and the digital low-pass filtering and channel equalization integrated module 113.
According to the center frequency and the sampling frequency of the signal, the values of the orthogonal local oscillation sequence 321 and the local oscillation sequence 322 listed in table 2 are calculated. The processing of quadrature digital down-conversion 320 is to periodically take the original value, zero, and inverse of the original data.
TABLE 2 Quadrature local oscillator sequence values
| Orthogonal local oscillator sequence | n＝0 | n＝1 | n＝2 | n＝3 | n＝4 | n＝5 | n＝6 | n＝7 | … |
| cos(w0n) | 1 | 0 | -1 | 0 | 1 | 0 | -1 | 0 | … |
| sin(w0n) | 0 | 1 | 0 | -1 | 0 | 1 | 0 | -1 | … |
Digital low pass filtering and channel equalization 330 performs 4 times filtering decimation and compensates for mismatch between channels. The HBF331 is a half-band filter, realizes 2 times of extraction, and meets the requirements of 15MHz passband cut-off frequency, 85MHz stopband cut-off frequency and-100 dB stopband attenuation. FIR332 is a digital low-pass FIR filter, which realizes 2 times of extraction, the cut-off frequency of the pass band is 15MHz, the cut-off frequency of the stop band is 25MHz, the pass band ripple is 0.1dB, the stop band attenuation is-110 dB, and the order of the filter is 42; equalizer 333 implements a channel equalization function.
And 3, setting the integral multiple of the clock period and the fractional multiple delay of the variable integer/fractional delay module 111 to 0.
The channel equalization mode is executed by the following steps:
step A, the digital low-pass filtering and channel equalizer coefficient calculating module 130 calculates the equalizer amplitude-phase characteristics of each channel according to the output data of each channel digital down-conversion module 112 by using a frequency domain channel equalization algorithm (obtained through Adaptive channel equalization for space-time Adaptive processing);
step B, the digital low-pass filtering and channel equalizer coefficient calculating module 130 synthesizes the amplitude-phase characteristics of the 42-order digital low-pass FIR filter 332 and the equalizer 333 of each channel according to the formula (3) to obtain the joint amplitude-phase characteristics of each channel, and optimizes the 42-order digital low-pass FIR filter coefficient of each channel to approach the respective joint amplitude-phase characteristics;
and C, setting the coefficient of the variable coefficient FIR filter 1131 of each channel digital low-pass filtering and channel equalization integrated module 113 to be a corresponding 42-order optimization coefficient.
The implementation scheme of the digital low-pass FIR filter 332 and the equalizer 333 after synthesis optimization is shown in fig. 6, where complex filtering is converted into real filtering, and 401 and 402 are inputs of in-phase data and quadrature data, respectively; they enter the real part coefficient 403 and imaginary part coefficient 404 of the variable coefficient FIR filter, respectively, and then add and subtract to obtain the in-phase data output 405 and the quadrature data output 406.
The execution steps of the normal working mode are as follows:
step a, calculating delay values of all channels according to the requirement of change of beam pointing direction and the formula (4), converting the delay values into integral multiples of clock periods and fractional time delays, and adjusting in real time;
τn＝nd sinθ0/c n＝1,2,...,N (4)
wherein d represents the array element spacing, θ0Denotes the beam pointing direction, c denotes the speed of the electromagnetic wave propagating in the vacuum, N denotes the number of channels, τnIndicating the delay value for each channel.
Step b, setting the integral multiple of the clock period and the fractional multiple delay of each channel variable integer/fractional delay module 111 according to the result;
step c, all modules of the whole circuit work by adopting a parallel pipeline structure, namely, data is delayed by a corresponding clock period through the variable integer/fraction delay module 111; the delayed data enters the digital down-conversion module 112 again to become the I/Q data of the baseband quadrature; the I/Q data with orthogonal baseband is processed by a digital low-pass filtering and channel equalization integrated module 113 to obtain broadband beam forming data with low data rate; the wideband beamformed data enters the data synthesis module 120 and is output as a beam.
The invention can be widely applied to radar digital array antenna, communication intelligent antenna, microphone array, sonar array and other systems.
Claims (7)
1. A working method of a high-efficiency time domain broadband beam forming circuit is characterized by comprising N channel delay and equalization modules, 1 data synthesis module and 1 digital low-pass filtering and channel equalizer coefficient calculation module, wherein the N channel delay and equalization modules are all connected with the data synthesis module and transmit processed data to the data synthesis module, each channel delay and equalization module comprises a variable integer/fractional delay module, a digital down-conversion module and a digital low-pass filtering and channel equalization integrated module which are sequentially connected, the variable integer/fractional delay module transmits delayed data to the digital down-conversion module, the digital down-conversion module transmits orthogonal baseband data to the digital low-pass filtering and channel equalization integrated module, the digital down-conversion module also transmits the data to the digital low-pass filtering and channel equalizer coefficient calculation module, the digital low-pass filtering and channel equalizer coefficient calculation module transmits the calculated filter coefficient to the digital low-pass filtering and channel equalization integrated module;
the method comprises three working modes which are respectively as follows: the method comprises an initialization mode, a channel equalization mode and a normal working mode, wherein the initialization mode comprises the following steps:
step 1, determining a coefficient of a Farrow filter according to a set delay precision and a delay error in a bandwidth, and putting a fixed coefficient of a variable fraction delay Farrow filter of a variable integer/fraction delay module;
step 2, setting the variable FIR filter coefficient of the digital low-pass filtering and channel equalization integrated module as the coefficient of a P-order digital low-pass filter;
step 3, setting the integral multiple of the clock period and the fractional multiple delay of the variable integer/fractional delay module to 0;
the channel equalization mode comprises the following steps:
a, a digital low-pass filtering and channel equalizer coefficient calculating module calculates the equalizer amplitude-phase characteristics of each channel by adopting a frequency domain channel equalization method according to the output data of each channel digital down-conversion module;
b, multiplying the amplitude-phase characteristic of each channel equalizer obtained in the step A by the amplitude-phase characteristic of an ideal digital low-pass filter by a digital low-pass filtering and channel equalizer coefficient calculating module to obtain the combined amplitude-phase characteristic of each channel, and respectively optimizing the coefficient of the P-order digital low-pass filter of each channel to approximate to the respective combined amplitude-phase characteristic;
setting the coefficient of a variable coefficient FIR filter of each channel digital low-pass filtering and channel equalization integrated module as a corresponding P-order optimization coefficient;
the normal operation mode comprises the following execution steps:
step a, calculating delay values of all channels according to the requirement of the change of the beam pointing direction, converting the delay values into integral multiples of clock periods and fractional time delays, and adjusting in real time;
b, setting the integral multiple of the clock period and the fractional multiple delay of each channel variable integral/fractional delay module in real time according to the integral multiple of the clock period and the fractional multiple delay result in the result;
c, each module of the whole circuit works by adopting a parallel pipeline structure, namely, data is delayed for a corresponding clock period through a variable integer/fraction delay module; the delayed data enters a digital down-conversion module again to become I/Q data of baseband quadrature; the I/Q data with orthogonal baseband is processed by a digital low-pass filtering and channel equalization integrated module to obtain broadband beam forming data with low data rate; the broadband beam forming data enters a data synthesis module and a beam is output.
2. The method of claim 1, wherein the variable integer/fractional delay module comprises an integer delay unit and a fractional delay unit connected in sequence, wherein the integer delay unit employs a FIFO structure to implement variable integer multiple delay of the clock period, and the fractional delay unit employs a Farrow filter to implement variable fractional multiple delay of the clock period.
3. The operating method of the efficient time-domain broadband beamforming circuit according to claim 1, wherein the digital low-pass filtering and channel equalization integration module employs a variable-coefficient FIR filter for implementing low-pass filtering decimation and channel equalization.
4. The method of claim 2, wherein the variable integer/fractional delay module is configured to write data of each channel into a respective FIFO buffer, and implement variable clock cycle integer-times delay by controlling a clock cycle delay amount of data read at an output end of the FIFO structure; the module optimizes the Farrow filter structure and the related coefficient thereof according to the delay precision and the delay error requirement in the bandwidth, and realizes variable clock period fractional time delay by adjusting the fractional delay parameter of the Farrow filter in the using process.
5. The method of claim 1, wherein the digital down-conversion module is implemented by: when sampling frequency fsSum signal center frequency f0Satisfy fs＝4f0Or 3fs＝4f0In the process, the orthogonal down-conversion local oscillation sequence only needs to periodically select three values of-1, 0 and 1, namely, the original data is periodically subjected to operations of taking the original value, taking zero and taking the inverse, so that the digital down-conversion function can be realized.
6. The operating method of the efficient time-domain broadband beamforming circuit according to claim 3, wherein the implementation scheme of the digital low-pass filtering and channel equalization integrated module is as follows: and performing joint optimization by using a digital low-pass filtering and channel equalizer coefficient calculation module according to the synthetic amplitude-phase characteristics of the P-order digital low-pass filter and the equalizer to obtain a filter coefficient, and realizing the functions of low-pass filtering and channel equalization by using a P-order variable coefficient FIR filter.
7. The method of claim 1, wherein the step a of calculating the delay value of each channel according to the requirement of the change of the beam pointing direction is represented by the following formula:
τn＝ndsinθ0/c n＝1,2,...,N
wherein d represents the array element spacing, θ0Denotes the beam pointing direction, c denotes the speed of the electromagnetic wave propagating in the vacuum, N denotes the number of channels, τnIndicating the delay value of the nth lane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710151095.0A CN108574459B (en) | 2017-03-14 | 2017-03-14 | Efficient time domain broadband beam forming circuit and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710151095.0A CN108574459B (en) | 2017-03-14 | 2017-03-14 | Efficient time domain broadband beam forming circuit and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108574459A CN108574459A (en) | 2018-09-25 |
| CN108574459B true CN108574459B (en) | 2022-04-01 |
Family
ID=63577271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710151095.0A Active CN108574459B (en) | 2017-03-14 | 2017-03-14 | Efficient time domain broadband beam forming circuit and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108574459B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109164437B (en) * | 2018-10-26 | 2021-03-16 | 海鹰企业集团有限责任公司 | Continuous variable decimal time delay estimation method and device for vector array popularity |
| CN112511208B (en) * | 2020-11-13 | 2022-06-14 | 河海大学 | Frequency domain broadband beam forming multi-filter combination processing method and system |
| CN113162626B (en) * | 2021-04-29 | 2023-01-03 | 中国船舶重工集团公司第七二三研究所 | High-precision multichannel synchronous high-speed data acquisition and processing system and method |
| CN113328716B (en) * | 2021-05-28 | 2023-08-01 | 中国电子科技集团公司第十四研究所 | FPGA-based broadband filter module and implementation method |
| CN113193889B (en) * | 2021-06-16 | 2022-08-19 | 嘉兴军创电子科技有限公司 | Ultra-wideband digital multi-beam transmitting method based on fractional time delay |
| WO2023031648A1 (en) * | 2021-08-31 | 2023-03-09 | Telefonaktiebolaget Lm Ericsson (Publ) | Forward distortion correction for time domain beamforming |
Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6269175A (en) * | 1985-09-24 | 1987-03-30 | Oki Electric Ind Co Ltd | Passive ranging system |
| CN1449603A (en) * | 2000-07-24 | 2003-10-15 | 高通股份有限公司 | Method and apparatus for processing a modulated signal using an equalizer and a rake receiver |
| CN1731706A (en) * | 2005-09-02 | 2006-02-08 | 东南大学 | Device for forming annular array beam in VAN |
| CN101098179A (en) * | 2006-06-30 | 2008-01-02 | 中国科学院声学研究所 | Method for forming broadband frequency domain digital beam |
| CN101218750A (en) * | 2005-03-18 | 2008-07-09 | 美商内数位科技公司 | Channel estimation enhanced LMS equalizer |
| CN102281045A (en) * | 2011-04-15 | 2011-12-14 | 深圳大学 | Method for constructing subband self-adapting filter |
| CN102404039A (en) * | 2011-12-23 | 2012-04-04 | 桂林电子科技大学 | Multi-antenna diversity receiving method and device based on time inversion |
| CN103220036A (en) * | 2012-01-21 | 2013-07-24 | 空间数码系统公司 | System and method of multi-channel communication power dynamic combination capable of improving signal power level |
| CN103888209A (en) * | 2014-04-15 | 2014-06-25 | 重庆大学 | Method for correcting channel amplitude phase error time domain of broadband receiving array antenna |
| CN103959813A (en) * | 2011-12-08 | 2014-07-30 | 索尼公司 | Earhole attachment-type sound pickup device, signal processing device, and sound pickup method |
| CN103969626A (en) * | 2014-05-20 | 2014-08-06 | 西安电子科技大学 | Wideband digital wave beam forming method based on all-pass type variable fractional delay filter |
| CN104218920A (en) * | 2014-08-29 | 2014-12-17 | 南京理工大学 | Partitioning concurrence based adaptive digital beamforming method and implementing device thereof |
| CN104779989A (en) * | 2015-05-11 | 2015-07-15 | 重庆大学 | Boardband array correcting filter coefficient calculation method |
| CN105044675A (en) * | 2015-07-16 | 2015-11-11 | 南京航空航天大学 | Fast SRP sound source positioning method |
| CN105991489A (en) * | 2015-02-10 | 2016-10-05 | 鄢炎新 | Method for realizing channel equalization by using frequency-domain oversampling |
| CN106019236A (en) * | 2016-05-24 | 2016-10-12 | 南京理工大学 | Sparse array digital wave beam formation method based on data reconstruction |
| CN106411379A (en) * | 2016-09-29 | 2017-02-15 | 电子科技大学 | Broadband beam forming design method for lowering hardware resource consumption |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI226765B (en) * | 2002-03-01 | 2005-01-11 | Cognio Inc | System and method for joint maximal ratio combining using time-domain signal processing |
| US9647731B2 (en) * | 2011-10-20 | 2017-05-09 | Microelectronics Research & Development Corp. | Reconfigurable network on a chip (NoC) radio through reduced instruction set computer (RISC) agents by overwriting program store for different phases of demodulation |
| KR20130073131A (en) * | 2011-12-23 | 2013-07-03 | 삼성전자주식회사 | Beamforming apparatus and method in mobile communication system |
| US9240814B2 (en) * | 2012-03-27 | 2016-01-19 | Texas Instruments Incorporated | Ultrasonic receiver front-end |
-
2017
- 2017-03-14 CN CN201710151095.0A patent/CN108574459B/en active Active
Patent Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6269175A (en) * | 1985-09-24 | 1987-03-30 | Oki Electric Ind Co Ltd | Passive ranging system |
| CN1449603A (en) * | 2000-07-24 | 2003-10-15 | 高通股份有限公司 | Method and apparatus for processing a modulated signal using an equalizer and a rake receiver |
| CN101218750A (en) * | 2005-03-18 | 2008-07-09 | 美商内数位科技公司 | Channel estimation enhanced LMS equalizer |
| CN1731706A (en) * | 2005-09-02 | 2006-02-08 | 东南大学 | Device for forming annular array beam in VAN |
| CN101098179A (en) * | 2006-06-30 | 2008-01-02 | 中国科学院声学研究所 | Method for forming broadband frequency domain digital beam |
| CN102281045A (en) * | 2011-04-15 | 2011-12-14 | 深圳大学 | Method for constructing subband self-adapting filter |
| CN103959813A (en) * | 2011-12-08 | 2014-07-30 | 索尼公司 | Earhole attachment-type sound pickup device, signal processing device, and sound pickup method |
| CN102404039A (en) * | 2011-12-23 | 2012-04-04 | 桂林电子科技大学 | Multi-antenna diversity receiving method and device based on time inversion |
| CN103220036A (en) * | 2012-01-21 | 2013-07-24 | 空间数码系统公司 | System and method of multi-channel communication power dynamic combination capable of improving signal power level |
| CN103888209A (en) * | 2014-04-15 | 2014-06-25 | 重庆大学 | Method for correcting channel amplitude phase error time domain of broadband receiving array antenna |
| CN103969626A (en) * | 2014-05-20 | 2014-08-06 | 西安电子科技大学 | Wideband digital wave beam forming method based on all-pass type variable fractional delay filter |
| CN104218920A (en) * | 2014-08-29 | 2014-12-17 | 南京理工大学 | Partitioning concurrence based adaptive digital beamforming method and implementing device thereof |
| CN105991489A (en) * | 2015-02-10 | 2016-10-05 | 鄢炎新 | Method for realizing channel equalization by using frequency-domain oversampling |
| CN104779989A (en) * | 2015-05-11 | 2015-07-15 | 重庆大学 | Boardband array correcting filter coefficient calculation method |
| CN105044675A (en) * | 2015-07-16 | 2015-11-11 | 南京航空航天大学 | Fast SRP sound source positioning method |
| CN106019236A (en) * | 2016-05-24 | 2016-10-12 | 南京理工大学 | Sparse array digital wave beam formation method based on data reconstruction |
| CN106411379A (en) * | 2016-09-29 | 2017-02-15 | 电子科技大学 | Broadband beam forming design method for lowering hardware resource consumption |
Non-Patent Citations (7)
| Title |
|---|
| Design of multiband/broadband software-defined super-sparse digital beam forming array for down-link satellite communications;J.J.H. Wang 等;《IEEE Antennas and Propagation Society Symposium, 2004》;20040625;3992-3995 * |
| 一种改进的宽带数字阵通道均衡频域算法;陈刚 等;《雷达科学与技术》;20081215;第6卷(第6期);463-466 * |
| 可控测角精度和范围的数字阵列单脉冲和差波束优化;马晓峰 等;《电子与信息学报》;20161215;第38卷(第12期);3107-3113 * |
| 宽带数字阵列中通道均衡技术的研究及应用;高浩;《中国优秀硕士学位论文全文数据库 信息科技辑》;20131215(第S2(2013年)期);I136-188 * |
| 宽带数字阵雷达数字波束形成系统研究;王峰 等;《雷达学报》;20130829;第2卷(第03期);314-318 * |
| 宽带波束形成结构及算法研究;赵拥军 等;《电子测量与仪器学报》;20140715;第28卷(第7期);687-694 * |
| 频率不变宽带波束形成权重系数的稀疏优化;张书瑞 等;《航空学报》;20170119;第38卷(第07期);279-287 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108574459A (en) | 2018-09-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108574459B (en) | Efficient time domain broadband beam forming circuit and method | |
| JP2561031B2 (en) | Transceiver | |
| CN113472371B (en) | Adaptive array antenna digital beam synthesis anti-interference processing method | |
| KR100901787B1 (en) | Fractional delay filter-based beamformer apparatus using post filtering | |
| CN109274388B (en) | Radio frequency cancellation device and method for digital domain interference reconstruction | |
| US8952844B1 (en) | System and method for adaptively matching the frequency response of multiple channels | |
| CN111108694B (en) | Multi-channel passive intermodulation digital cancellation circuit | |
| CN110708103B (en) | Broadband beam forming method without pre-delay | |
| CN111416649A (en) | Digital beam forming method based on zero intermediate frequency architecture | |
| CN108141237A (en) | High-performance PIM with feedback is eliminated | |
| CN113162670A (en) | Digital multi-beam correction and synthesis method | |
| CN113219434A (en) | Self-adaptive broadband digital zero-setting system and method based on Zynq chip | |
| CN109116377B (en) | Satellite navigation anti-interference method and device based on time domain submatrix calculation | |
| WO2014210518A1 (en) | All-analog and hybrid radio interference cancelation using cables, attenuators and power splitters | |
| US10714828B2 (en) | Microwave analog cancellation for in-aperture simultaneous transmit and receive | |
| US10243643B2 (en) | Beam adjustment apparatus and method for array antenna | |
| CN112034492A (en) | Space-time pole three-dimensional joint navigation array anti-interference processing method | |
| CN210243826U (en) | Radar multichannel signal preprocessing device and pulse compression unit thereof | |
| US11888538B2 (en) | Receiving apparatus | |
| CN115149985B (en) | Multi-phase self-adaptive multi-beam forming system and method | |
| JPH0629890A (en) | Interference wave eliminating device | |
| Jihong et al. | An effective joint implementation design of channel equalizer and DDC for WDAR receiver | |
| CN117579108A (en) | Low-complexity broadband receiving digital beam former | |
| RU2788573C1 (en) | Method for adaptive spatio-temporal signal filtering in the antenna array | |
| CN112600536A (en) | Transmitting digital beam forming method based on hyperbolic structure fractional delay filter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Zhang Shurui Inventor after: Ma Xiaofeng Inventor after: Sheng Weixing Inventor after: Guo Ming Inventor after: Han Yubing Inventor after: Zhang Renli Inventor after: Cui Jie Inventor before: Ma Xiaofeng Inventor before: Zhang Shurui Inventor before: Sheng Weixing Inventor before: Guo Ming Inventor before: Han Yubing Inventor before: Zhang Renli Inventor before: Cui Jie |