CN117579108A

CN117579108A - Low-complexity broadband receiving digital beam former

Info

Publication number: CN117579108A
Application number: CN202311245998.7A
Authority: CN
Inventors: 邹林; 李林洋; 唐墨; 刘世澳; 钱璐; 周云
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2023-09-25
Filing date: 2023-09-25
Publication date: 2024-02-20

Abstract

The invention discloses a low-complexity broadband receiving digital beam former, and belongs to the field of radars. The invention comprises the following steps: the device comprises a parallel DDS module, N receiving channels, an accumulation module and 2 anti-aliasing filtering and extracting modules. Wherein the receiving channel comprises: the device comprises a multipath digital-to-analog conversion module, a digital time delay module, a frequency mixing module and an amplitude-to-amplitude weighting module. The invention uses digital time delay, can effectively eliminate the influence brought by aperture effect and transit time when the broadband digital wave beam is formed; the digital time delay is carried out before extraction, so that the time delay precision is improved; the digital delay module is arranged in front of the mixing module, and all receiving channels share 2 anti-aliasing filtering and extracting modules, so that the system structure is effectively simplified and the hardware implementation is facilitated; the parallel processing is adopted, so that the method can adapt to the characteristic of high data rate of the broadband digital signal.

Description

Low-complexity broadband receiving digital beam former

Technical Field

The invention belongs to the field of signal processing, and particularly relates to a novel low-complexity implementation structure of a broadband receiving digital beam former.

Background

The broadband phased array radar system has the long-distance detection, rapid beam scanning and forming and dense target detection and tracking capabilities of a phased array radar, and has the high-resolution detection and imaging, low interception rate and clutter and interference resistance capabilities of the broadband radar. Digital array radars (Digital Array Radar, DAR) that form receive and transmit beams based on digital beam forming techniques (Digital Beamforming, DBF) have evolved greatly, thanks to the development of digital technology in recent years. The DAR is realized in a digital mode from beam forming to data processing, and has excellent performance, simple system structure and high reconfigurability. Broadband digital array radar (Wideband Digital Array Radar, WB-DAR) combines the advantages of broadband phased array radar and DAR, and is an important development direction for phased array radar.

The receiving DBF technique is an important step in the digital signal processing of DAR receivers and is the basis for all subsequent signal processing, considering that in the case of wideband signals, the implementation of delay and phase shift at different occasions (compared to the down-conversion process) is different and the resource consumption, so that in designing a low complexity wideband digital beamformer, it is necessary to incorporate the design of the digital down-conversion (Digital Down Conversion, DDC) process.

The conventional wideband receiving digital beam forming is usually performed on a digital baseband, and its implementation structure is shown in fig. 1, and the DDC processing is performed on the digital signal after the analog-to-digital conversion, including mixing, anti-aliasing filtering and decimation on two paths of signals I, Q, and then the amplitude adding weight and the digital delay are performed on the two paths of digital baseband signals after the DDC. In the structure, the digital time delay is carried out after DDC, and a digital time delay module is needed for each of the I, Q paths, so that the complexity of the structure is increased; under the condition that the coefficient and the order of the fractional delay filter are determined, the precision of the fractional delay is related to the sampling rate of the signal, the higher the sampling rate is, the higher the delay precision is, and the signal is a low-rate digital baseband signal after DDC, and the digital delay precision is lower at the moment; meanwhile, since DDC needs to be performed before the amplitude addition weight and the digital delay, each channel has 2 corresponding anti-aliasing filters (one for each I, Q path), which also makes the complexity of the system large.

The above analysis shows that the conventional wideband receiving digital beam forming structure has room for further optimization in terms of structural complexity and fractional delay precision, and in order to adapt to the high data rate of wideband signals, it is also necessary to consider the use of a parallelization structure to reduce the clock frequency in the processing process when designing the wideband DBF structure.

Disclosure of Invention

The invention aims to solve the technical problem of providing a broadband receiving digital beam former with low complexity and high time delay precision for a broadband digital array radar.

The invention adopts the technical proposal that a low-complexity broadband receiving digital beam forming device is adopted, and the wave speed forming device comprises: parallel DDS, N receiving channels, accumulation module, anti-confusion filtering and extraction module, output module, including in every channel: the device comprises an input module, an analog-to-digital conversion module, a digital time delay module, a mixing module and an amplitude adding weighting module;

the analog-to-digital conversion module is used for sampling input analog signals, sequentially dividing the obtained digital signals into multiple paths according to time sequence, and outputting multiple paths of parallel digital signals;

the digital delay module is used for carrying out digital delay on the input sampled multipath parallel digital signals and outputting multipath parallel digital signals after the digital delay, wherein the digital delay is divided into an integer delay part and a fractional delay part, the integer delay part is used for carrying out the integer delay by using a register delay latch, the fractional delay part is used for carrying out the fractional delay by using a fractional delay filter, and the fractional filter adopts a parallelization processing structure;

the frequency mixing module mixes the input digital delayed multipath parallel digital signals with parallel orthogonal digital oscillation signals and outputs the mixed multipath parallel digital signals, wherein the parallel orthogonal digital oscillation signals are generated by the parallel DDS module, and the mixed multipath parallel digital signals comprise multipath parallel I-path signals and multipath parallel Q-path signals;

the amplitude-phase weighting module is used for carrying out amplitude and phase weighting on the input multipath parallel digital signals after frequency mixing and outputting multipath parallel digital signals after amplitude-phase weighting, wherein the phase weighting value is required to be determined according to the spatial phase difference of the radio frequency receiving signals between channels and the extra phase difference introduced during digital time delay;

the parallel DDS module outputs parallel orthogonal digital oscillation signals to the frequency mixing module in each receiving channel, wherein the parallel orthogonal digital oscillation signals comprise multiple paths of parallel I-path signals and multiple paths of parallel Q-path signals;

each receiving channel processes echo signals of an array element of the digital array radar in the N receiving channels; the input module in each receiving channel inputs analog signals, an analog-to-digital conversion module is adopted to sample the input analog signals to obtain multipath parallel digital signals, the sampled multipath parallel digital signals sequentially pass through a digital delay module, a frequency mixing module and an amplitude adding weighting module to carry out digital delay, frequency mixing and amplitude adding weighting, and finally the multipath parallel digital signals are output to an accumulating module to accumulate the signals of each receiving channel;

the accumulation module uses a multi-input adder tree to accumulate the input N-channel phase-shifted multipath parallel digital signals and outputs accumulated multipath parallel I, Q paths of signals;

the anti-aliasing filtering and extracting module firstly adopts a parallel anti-aliasing filter to carry out anti-aliasing filtering on the input accumulated multipath parallel I, Q paths of signals, and then reduces the data rate of the signals by using a uniform extracting mode and outputs the signals;

the fractional delay filter in the digital delay module is as follows:

wherein M represents the number of total sub-filters of the fractional delay filter minus 1, N is expressedThe number of taps of each sub-filter is shown minus 1; h (n, m) represents the coefficient h (n, m) of each sub-filter, D ^m Representing a correction amount, changing a fractional delay value of the fractional delay filter by changing a value of D; the calculation method of the time delay value comprises the following steps:

D _i,frac ＝τ _i -D _i,int i＝0,1,…

τ ₀ ＝0

wherein τ _i The delay value required by the digital delay module in the receiving channel of the array element i is represented, d represents the array element spacing, theta represents the angle between the expected beam direction and the array normal, c is the speed of light, floor (·) represents the downward rounding, and t _s Is the intermediate frequency sampling period, the value of which is the intermediate frequency sampling rate f _s,IF Inverse of D _i,int For the integer delay value of element i, i.e. the number of clock cycles of the register delay latch, D _i,frac The fractional delay value of the array element i;

the phase weight value of each element receiving channel in the amplitude-phase weighting module is

Wherein i is the label of the receiving channel of different array elements, the receiving channel of the label 0 is the reference channel,for the phase weight corresponding to channel i, f ₀ Is the carrier frequency of the radio frequency signal, f _IF Representing the intermediate frequency.

The beneficial effects of the invention are as follows: the influence caused by phased array aperture effect and transit time can be effectively eliminated under the condition of broadband signals; the digital time delay is used, the precision is high, and the direction of the array directional diagram is accurate; the use of low complexity and parallelized designs reduces implementation and operation costs and is suitable for high data rate systems.

Drawings

Fig. 1 is a diagram of a conventional wideband receive digital beamforming implementation;

FIG. 2 is a schematic diagram of a uniform linear array;

FIG. 3 is a low complexity wideband digital beamforming architecture;

FIG. 4 is a 4 parallel delay structure variable fraction delay filter;

fig. 5 is a graph of group delay response of a variable delay filter at different fractional delays;

FIG. 6 is a graph of the amplitude-frequency response of a variable delay filter at different fractional delays;

FIG. 7 is an 8-input adder tree schematic;

FIG. 8 is an image of the amplitude-frequency response of an anti-aliasing filter;

fig. 9 is a comparison of the receive beam pattern formed in this embodiment with an ideal pattern;

fig. 10 shows the error between the digital delay and the ideal delay for each element.

Detailed Description

In the embodiment of the application, the overall parallelism of the system is l=4, the dar adopts a uniform linear array, the number of array elements is n=8, and the radio frequency carrier frequency f ₀ =4 GHz, intermediate frequency f _IF =300 MHz, intermediate frequency low pass sampling rate f _s,IF The radar signal is a linear frequency modulation signal, the signal bandwidth b=150 MHz, the pulse width t=5 μs, and the baseband sampling rate after extraction is f _s,base The desired beam pointing at an angle θ=30° to the array normal, with the array element spacing d being half the wavelength of the radio frequency carrier wave, =200 MHz. The schematic diagram of the uniform linear array is shown in fig. 2, the first array element on the left side is referred to as the reference array element, which is marked as the array element 0, and the rest array elements are sequentially from left to right as the array elements 1 to 7.

The overall structure of the embodiment is shown in fig. 3, that is, the overall structure is composed of 1 parallel DDS, 8 receiving channels, 1 accumulation module and 2 anti-aliasing filtering and extraction modules, and each receiving channel is composed of 1 analog-to-digital conversion module, 1 digital delay module, 1 mixing module and 1 amplitude-adding weighting module; each receiving channel of the 8 receiving channels corresponds to one array element in the uniform linear radar array, analog intermediate frequency signals of radar echoes of each array element are firstly converted into digital intermediate frequency signals through an analog-to-digital conversion module, then the digital intermediate frequency signals are input into a frequency mixing module through a digital time delay module, the frequency mixing module multiplies the input signals with parallel orthogonal digital oscillation signals output by 4 paths of parallel DDSs to finish frequency mixing, and outputs 4 paths of parallel I and Q signals to an amplitude adding weighting module to finish amplitude adding weighting, then all receiving channels output signals after amplitude weighting to an accumulating module to be accumulated, and finally the I and Q signals respectively pass through 1 anti-aliasing filtering and extracting modules to obtain low-speed baseband signals and output the low-speed baseband signals;

the analog intermediate frequency signals of each array element receiving channel are subjected to low-pass sampling by an analog-to-digital conversion module, and are converted into 4 paths of parallel digital intermediate frequency signals, and then digital time delay is needed; the integer part of the digital delay can be completed through register delay latching, and the system function of the fractional part structure variable fractional delay filter can be expressed as follows:

here, a structure variable fractional delay filter using 4 sub-filters is selected, namely m=3 in the above formula, the number of taps of each sub-filter is 40, namely n=39 in the above formula, the coefficient h (N, M) of each sub-filter is calculated by using spline interpolation and a polynomial fitting method, and the fractional delay value of the fractional delay filter can be changed by changing the value of D; the group delay response curve and the amplitude-frequency response curve of the variable fraction delay filter under different fraction delays are shown in fig. 5 and 6. Each sub-filter is processed in 4 parallel based on the modified Winograd algorithm, and a 4-parallel structure variable fraction delay filter is shown in fig. 4, wherein one of the variable fraction delay filters needs 252 multipliers in consideration of the coefficient symmetry property of the sub-filters. On the basis, the time delay required by the digital time delay module in the receiving channel of the array element i (i=0, 1,2, …, 7) is calculatedValue τ _i 。

τ ₀ ＝0 (2)

D _i,frac ＝τ _i -D _i,int i＝0,1,…,7 (5)

Wherein c is the speed of light, floor (·) represents the rounding down, t _s Is the intermediate frequency sampling period, the value of which is the intermediate frequency sampling rate f _s,IF Inverse of D _i,int For the integer delay value of element i, i.e. the number of clock cycles of the register delay latch, D _i,frac The fractional delay value of the array element i is the value of the parameter D in the input fractional delay filter.

The signal after digital time delay is input into a frequency mixing module, and the frequency mixing module mixes the input signal with a parallel quadrature frequency mixing signal generated by a parallel DDS. The mixing module requires 8 multipliers. The 4-path parallel orthogonal digital oscillation signal generated by the DDS comprises 4-path parallel I-path signal cos (2 pi f) _NCO n+Φ _k ) Q-way signal-sin (2pi.f) parallel to 4-way _NCO n+Φ _k ) Wherein Φ is _k The initial phase of the kth signal in the 4 parallel I, Q signals. The frequency f of each signal _NCO Identical, equal to intermediate frequency f _IF The sampling rate is the intermediate frequency sampling rate f _s,IF 1/4 of the initial phase of each branch

The signal output by the frequency mixing module is a 4-path parallel I, Q-path signal, and the signals are input into the amplitude-phase weighting module for phase weighting and amplitude weighting respectively. In this embodiment, the phase weighting is performed based on the CORDIC algorithm, and the phase weighting value of each array element receiving channel is

Wherein i is the label of the receiving channel of different array elements, the receiving channel of the label 0 is the reference channel,for the phase weight corresponding to channel i, f ₀ Is the carrier frequency of the radio frequency signal. In this embodiment, the amplitude weighting is performed by using a multiplier in a manner of doffer-chebyshev weighting. The amplitude-phase weighting module requires 8 multipliers.

In summary, a single receive channel requires 268 multipliers.

The output signals of the amplitude-phase weighting module of each array element receiving channel are all output to the accumulation module for accumulation, and the 4 parallel I-path signals and the 4 parallel Q-path signals output by each channel are respectively accumulated, so that 8 adder trees are needed to complete accumulation, and because the number of the array elements and the receiving channels is 8, a single adder tree has 8 inputs and 1 output, and a schematic diagram is shown in fig. 7.

The 4 parallel I, Q signals output by the accumulation module are respectively converted into low-rate baseband signals to be output after passing through 2 confusion filtering and extraction modules. In this embodiment, a low-pass FIR filter with a normalized cut-off frequency of 0.5 pi is designed as a prototype filter by using an equal ripple design method, and then 4 parallel processing is performed on the low-pass FIR filter based on a modified Winograd algorithm, and 144 multipliers are needed for 2 anti-aliasing filters, and the amplitude-frequency response of the anti-aliasing filters is shown in fig. 8. The signal after anti-aliasing filtering is extracted by 4 times, and a low-rate baseband signal with the sampling rate of 200MHz can be output. Fig. 9 shows a comparison of the receive beam pattern formed using the present embodiment and an ideal pattern.

Compared with the conventional structure shown in fig. 1, the digital time delay is advanced to be before extraction, and higher time delay precision is obtained. In this embodiment, the multiple of the extraction is 4, and the D bit width in fig. 4 is 8 bits when the hardware is implemented, so that under the structure described in this embodiment and the conventional structure, the error between the digital delay and the ideal delay of each array element is as shown in fig. 10, and the error between the actual value and the ideal value of the digital delay is smaller in this embodiment.

Meanwhile, compared with the traditional structure, the structure disclosed by the application has less hardware resource consumption, particularly less multiplier consumption. In the conventional structure, anti-aliasing filtering and fractional delay filtering are performed, filters having the same number of sub-filters and tap numbers as those of the present embodiment are used, and coefficient symmetry properties are considered to reduce multiplier consumption. In the whole processing procedure of the conventional structure, the same 4 parallel processing method as in the present embodiment is adopted before the extraction, and no parallel processing is performed after the extraction. For a single receive channel, the mixing module requires 8 multipliers, the 2 anti-aliasing filtering and decimation modules require 144 multipliers, the 2 amplitude adding weighting modules require 4 multipliers, and the 2 digital delay modules require 166 multipliers, i.e., a single channel requires 322 multipliers. For an 8-element DAR, a total of 322×8=2576 multipliers are required in the conventional structure, and in contrast, 268×8+144=2288 multipliers are required in the structure of this embodiment. It is noted that the advantages of the structure of the present application of saving multipliers will be further emphasized when the number of array elements is further increased.

Claims

1. A low complexity wideband receive digital beamformer, the beamformer comprising: parallel DDS, N receiving channels, accumulation module, anti-confusion filtering and extraction module, output module, including in every channel: the device comprises an input module, an analog-to-digital conversion module, a digital time delay module, a mixing module and an amplitude adding weighting module;

the amplitude-phase weighting module is used for carrying out amplitude and phase weighting on the input multipath parallel digital signals after frequency mixing and outputting multipath parallel digital signals after amplitude-phase weighting, wherein the phase weighting value is required to be determined according to the spatial phase difference of the radio-frequency receiving frequency signals between channels and the extra phase difference introduced during digital time delay;

the fractional delay filter in the digital delay module is as follows:

wherein M represents the number of total sub-filters of the fractional delay filter minus 1, and N represents the number of taps of each sub-filter minus 1; h (n, m) represents the coefficient h (n, m) of each sub-filter, D ^m Representing a correction amount, changing a fractional delay value of the fractional delay filter by changing a value of D; the time delay value calculating method comprises the following steps:

D _i,frac ＝τ _i -D _i,int i＝0,1,…

τ ₀ ＝0

2. The low complexity wideband receive digital beamformer of claim 1, wherein the parallel quadrature digital oscillation signals generated by the parallel DDS module include multiple parallel I-channel signals cos (2ρf _NCO n+Φ _k ) And a multi-path parallel Q-way signal-sin (2pi.f) _NCO n+Φ _k ) Wherein Φ is _k Is the initial phase of the kth signal in the multipath parallel I, Q signals. The frequencies of the signals are the same, and f _NCO The sampling rate is the sampling rate f of the analog-to-digital conversion module _s Wherein L is the number of parallel channels of the parallel DDS module, and the initial phase of each branch is

3. The low complexity wideband receive digital beamformer of claim 2, wherein the analog to digital conversion module divides each sampled digital signal into L paths in time sequence, each signal having a data rate of a sampling rate f _s 1/L of (C).

4. The low-complexity wideband receiving digital beam former according to claim 2, wherein the amplitude-adding weighting module is composed of a plurality of digital phase shifters and multipliers, each phase shifter inputs one path of I signals or one path of Q signals respectively, phase weights the signals and outputs phase weighted I, Q paths of signals, and the multipliers are used for amplitude weighting the phase weighted I, Q paths of signals respectively; the phase shift values of all phase shifters in one array element receiving channel are equal and are

Wherein i is the reference number of the different receiving channels, the receiving channel with the reference number 0 is the reference channel,for receiving the phase weight value corresponding to channel i, f ₀ Is the carrier frequency of the radio frequency signal, t _i For the time difference, t, when the radio frequency signal is received by the ith receiving channel and the reference channel respectively _i A value greater than 0 indicates that channel i receives the rf signal earlier than the reference channel and vice versa.

5. The low complexity wideband receive digital beamformer of claim 2, wherein the accumulation module uses a plurality of N-input adder trees to accumulate the multiple parallel I, Q paths of signals output by the N receive channels, respectively.

6. The low complexity wideband receive digital beamformer of claim 2, wherein the anti-aliasing filtering and decimating module first performs anti-aliasing filtering on the input accumulated multipath parallel I, Q paths of signals using parallel anti-aliasing filters, and then uses uniform decimation to reduce the data rate of the signals and output.