CN112653424A

CN112653424A - Signal processing method, device and computer readable storage medium

Info

Publication number: CN112653424A
Application number: CN202011438396.XA
Authority: CN
Inventors: 杨元浩; 王宇; 杜江; 王伟; 王沛; 禹卫东; 邓云凯; 赵庆超; 陈圳; 张华春
Original assignee: Aerospace Information Research Institute of CAS
Current assignee: Aerospace Information Research Institute of CAS
Priority date: 2020-12-07
Filing date: 2020-12-07
Publication date: 2021-04-13

Abstract

The embodiment of the invention discloses a signal processing method, which comprises the following steps: carrying out frequency reduction processing on a received signal to be processed of each channel of a plurality of channels to obtain a first signal, carrying out weighting delay processing on the first signal of each channel to obtain a second signal of each channel, synthesizing a first path of signals of the second signals of the plurality of channels to obtain a first path of synthesized signals, and synthesizing a second path of signals of the second signals of the plurality of channels to obtain a second path of synthesized signals; the third signal comprises a first path of synthesized signal and a second path of synthesized signal; demodulating and synthesizing the first path of synthesized signal to obtain a first path of demodulated and synthesized signal, and demodulating and synthesizing the second path of synthesized signal to obtain a second path of demodulated and synthesized signal; the fourth signal comprises a first path of demodulation synthesis signal and a second path of demodulation synthesis signal; and carrying out low-pass filtering processing on the fourth signal to obtain a target signal. The embodiment of the invention also discloses a signal processing device and a computer readable storage medium.

Description

Signal processing method, device and computer readable storage medium

Technical Field

The present invention relates to the field of digital signal processing, and in particular, to a signal processing method, device, and computer-readable storage medium.

Background

The Digital Beam Forming (DBF) technology in the pitching direction is a new technology established along with the development of Digital signal processing methods, and the technology not only can fully retain information collected on an array antenna, but also can process signals by using a complex Digital signal processing method. In mapping and imaging application of a Synthetic Aperture Radar (SAR) system, digital beam forming of a receiving end is firstly researched, namely, an antenna of the receiving end is divided into a plurality of sub-apertures; the DBF technique is used to synthesize the signals to be processed received by each sub-aperture (channel), and finally, a target signal can be generated. In the related art, when a DBF technology is used to synthesize signals to be processed received by each channel to obtain a target signal, the signals to be processed of each of a plurality of channels need to be received, the signals to be processed of each channel are sequentially demodulated, low-pass filtered and weighted delayed, and then the signals after weighted delayed processing of the plurality of channels are synthesized.

However, in the process of obtaining the target signal in the related art, 2 filters are required for the signal to be processed in each channel when the signal to be processed is subjected to the low-pass filtering, and the number of filters required for the data to be processed in the multiple channels when the data to be processed is subjected to the low-pass filtering is larger, which results in higher complexity of the SAR system.

Disclosure of Invention

In order to solve the above technical problems, embodiments of the present invention provide a signal processing method, a signal processing apparatus, and a computer-readable storage medium, which solve the problem in the related art that a large number of filters are required when to-be-processed data of multiple channels is subjected to low-pass filtering, and reduce the complexity of an SAR system.

The technical scheme of the invention is realized as follows:

a method of signal processing, the method comprising:

carrying out frequency reduction processing on a received signal to be processed of each channel in a plurality of channels to obtain a first signal;

performing weighted delay processing on the first signal of each channel to obtain a second signal of each channel;

synthesizing a first path of signals of the second signals of the plurality of channels to obtain a first path of synthesized signals, and synthesizing a second path of signals of the second signals of the plurality of channels to obtain a second path of synthesized signals; the third signal comprises the first path of synthesized signal and the second path of synthesized signal;

demodulating and synthesizing the first path of synthesized signal to obtain a first path of demodulated and synthesized signal, and demodulating and synthesizing the second path of synthesized signal to obtain a second path of demodulated and synthesized signal; the fourth signal comprises the first path of demodulation and synthesis signal and the second path of demodulation and synthesis signal;

and carrying out low-pass filtering processing on the fourth signal to obtain a target signal.

In the foregoing scheme, the down-converting the received signal to be processed of each of the multiple channels to obtain the first signal includes:

dividing the signal to be processed of each channel to obtain a plurality of paths of first division signals for each channel; wherein the first signal comprises the multi-path first split signal.

In the foregoing scheme, the performing weighted delay processing on the first signal of each channel to obtain the second signal of each channel includes:

and if the signal type of the multi-channel first division signal is consistent with the preset signal type, performing weighted delay processing on the multi-channel first division signal to obtain the second signal of each channel.

In the above scheme, the method further comprises:

if the signal type of the multi-path first division signal is inconsistent with the preset signal type, performing signal type conversion on the multi-path first division signal;

and performing weighted delay processing on the multi-path first division signals after the signal type conversion to obtain the second signals of each channel, wherein the signal type of the multi-path first division signals after the conversion is a preset signal type.

In the foregoing scheme, performing weighted delay processing on the multiple first division signals of which the types are consistent with the preset signal type to obtain the second signal of each channel includes:

time synchronization is carried out on the multi-channel first division signals with the same type as the preset signals, and multi-channel time synchronization signals of each channel are obtained;

and performing weighted delay processing on the multi-channel time synchronization signal of each channel to obtain the second signal of each channel.

In the foregoing scheme, the performing weighted delay processing on the multiple paths of time synchronization signals of each channel to obtain the second signal of each channel includes:

acquiring a filter coefficient and a weighting parameter of each channel;

weighting the multi-channel time synchronization signal of each channel based on the weighting parameter of each channel to obtain the multi-channel weighting signal of each channel;

setting parameters of a filter based on the filter coefficient of each channel, and performing delay filtering processing on the multi-channel weighted signals by adopting the filter with the set parameters to obtain multi-channel delay filtering signals of each channel;

and synthesizing the multi-channel delay filtering signals of each channel to obtain the second signal of each channel.

In the foregoing scheme, the obtaining the filter coefficient and the weighting parameter of each channel includes:

acquiring filter group number information of each channel based on the identification information of each channel;

and acquiring the filter coefficient and the weighting parameter of each channel based on the filter group number information of each channel.

In the foregoing scheme, the demodulating and synthesizing the first path of synthesized signal to obtain a first path of demodulated and synthesized signal, and demodulating and synthesizing the second path of synthesized signal to obtain a second path of demodulated and synthesized signal includes:

performing orthogonal demodulation processing on the first path of synthesized signal to obtain a first path of demodulated signal and a second path of demodulated signal, and performing orthogonal demodulation processing on the second path of synthesized signal to obtain a third path of demodulated signal and a fourth path of demodulated signal;

and synthesizing the first path of demodulation signal and the third path of demodulation signal to obtain a first path of demodulation synthesized signal, and synthesizing the second path of demodulation signal and the fourth path of demodulation signal to a second path of demodulation synthesized signal.

In the foregoing solution, before performing frequency reduction processing on a received signal to be processed of each of a plurality of channels to obtain a first signal, the method includes:

acquiring a plurality of paths of intermediate frequency signals to be processed;

and performing analog-to-digital conversion processing on the multiple paths of intermediate frequency signals to be processed to obtain signals to be processed of each channel.

A signal processing apparatus, the apparatus comprising: a processor, a memory, and a communication bus;

the communication bus is used for realizing communication connection between the processor and the memory;

the processor is configured to execute a signal processing program stored in the memory to implement the steps of:

A computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement the steps of the above-described signal processing method.

The signal processing method, the signal processing device and the computer readable storage medium provided by the embodiment of the invention perform frequency reduction processing on a received signal to be processed of each channel in a plurality of channels to obtain a first signal; carrying out weighted delay processing on the first signal of each channel to obtain a second signal of each channel; synthesizing a first path of signals of the second signals of the plurality of channels to obtain a first path of synthesized signals, and synthesizing a second path of signals of the second signals of the plurality of channels to obtain a second path of synthesized signals; the third signal comprises a first path of synthesized signal and a second path of synthesized signal; demodulating and synthesizing the first path of synthesized signal to obtain a first path of demodulated and synthesized signal, and demodulating and synthesizing the second path of synthesized signal to obtain a second path of demodulated and synthesized signal; the fourth signal comprises a first path of demodulation and synthesis signal and a second path of demodulation and synthesis signal; the fourth signal is subjected to low-pass filtering processing to obtain a target signal, so that the signals to be processed of the multiple channels are demodulated and synthesized to obtain a first path of demodulated and synthesized signal and a second path of demodulated and synthesized signal, only two filters are needed when the signals to be processed of all the channels are subjected to filtering processing, the problem that the number of the filters needed when the signals to be processed of the multiple channels are subjected to low-pass filtering processing in the related art is large is solved, and the complexity of an SAR system is reduced.

Drawings

Fig. 1 is a schematic flow chart of a signal processing method according to an embodiment of the present invention;

fig. 2 is a schematic flow chart of a signal processing method according to an embodiment of the present invention;

fig. 3 is a schematic flowchart of a signal processing method according to an embodiment of the present invention;

fig. 4 is a schematic signal flow diagram of a signal processing method according to an embodiment of the present invention;

fig. 5 is a schematic signal flow diagram illustrating a signal processing method according to an embodiment of the present invention;

fig. 6A is a schematic diagram of data before delay filtering when a signal processing method is implemented on an FPGA according to an embodiment of the present invention;

fig. 6B is a schematic diagram of data before delay filtering when a signal processing method is implemented based on an MATLAB program of a computer device according to an embodiment of the present invention;

fig. 7A is a schematic diagram of data after delay filtering when a signal processing method is implemented on an FPGA according to an embodiment of the present invention;

fig. 7B is a schematic diagram of data after delay filtering when a signal processing method is implemented based on an MATLAB program of a computer device according to an embodiment of the present invention;

fig. 8A is a schematic diagram of data after quadrature demodulation when a signal processing method is implemented on an FPGA according to an embodiment of the present invention;

fig. 8B is a schematic diagram of data after orthogonal demodulation when a signal processing method is implemented based on an MATLAB program of a computer device according to an embodiment of the present invention.

Fig. 9 is a schematic structural diagram of a signal processing apparatus according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

The embodiment of the invention provides a signal processing method, which is applied to a satellite-borne synthetic aperture radar system, and can utilize a digital beam forming technology to realize multi-channel receiving echo signals in a pitching direction and process the echo signals in the mapping and imaging application of the satellite-borne synthetic aperture radar system. In an embodiment of the present invention, the system for a satellite-borne synthetic aperture radar includes: a sending terminal, a receiving terminal and a signal processing device.

In a feasible implementation mode, the satellite-borne SAR system uses an active phased array antenna, the distance direction has N apertures, each aperture corresponds to 1 channel, the transmitting end uses a middle aperture or a partial aperture to transmit a wide beam to irradiate the whole mapping band region, each aperture receives an echo independently when the receiving end receives the echo, the receiving end sends the echo independently received by each aperture to the signal processing equipment, and the echo received by each aperture is processed by the signal processing equipment to realize the optimal synthesis of the echo received by each sub-aperture.

It should be noted that the signal processing apparatus may be a device having a receiving processing capability, such as: computer equipment, receivers, Field Programmable Gate Arrays (FPGAs), or other devices that receive processing power. The following provides a signal processing method through various embodiments, which will be explained in detail to realize the optimal synthesis of the echoes received by each sub-aperture.

An embodiment of the present invention provides a signal processing method, which is applied to the signal processing device in the above satellite-borne synthetic aperture radar system, as shown in fig. 1, the method includes the following steps:

s101, performing frequency reduction processing on the received signal to be processed of each channel in the plurality of channels to obtain a first signal.

The signal to be processed is an intermediate frequency signal, and because the frequency of the intermediate frequency signal is high, the signal processing device has a high processing difficulty when processing the received signal to be processed of each channel, and therefore the intermediate frequency signal needs to be subjected to frequency reduction processing to obtain a first signal. Wherein the frequency of the first signal is lower than the frequency of the signal to be processed. The following explains the signal to be processed in a manner of performing down-conversion processing by way of example.

In a feasible implementation manner, the frequency of the signal to be processed is 1.6GHZ, and the requirement on the clock frequency of the signal processing device is too high when the signal to be processed at 1.6GHZ is processed, so that the intermediate frequency signal cannot be subsequently processed. Therefore, the frequency of the signal to be processed can be reduced to 1/4, 1/5, 1/6 of the frequency of the signal to be processed, so that the signal processing apparatus can perform subsequent processing on the first signal with a low frequency by the lower frequency of the first signal obtained by down-conversion.

In the embodiment of the present invention, taking the specific number of channels of the multiple channels as an example of 8, the signal processing device needs to receive signals to be processed of the 8 channels, and needs to perform frequency reduction processing on the signals to be processed of each channel of the 8 channels, so as to process the first signal after the frequency reduction processing in the subsequent step.

It should be noted that, each signal processing device has a limited data processing amount, and the number of the corresponding signal processing devices may be determined according to the number of the specific channels, and if the number of the specific channels of the multiple channels is 16, when one signal processing device can process signals to be processed of at most 8 channels, two signal processing devices are required to process signals to be processed of 8 channels respectively.

And S102, carrying out weighted delay processing on the first signal of each channel to obtain a second signal of each channel.

Wherein, the weighted delay processing comprises: weighting process and delay filter process

The radar echo components are complex, various component signals such as main signals, noise, clutter and radio frequency interference often exist at the same time, and the radar echo signals can be weighted according to the distribution characteristics of the main signals and other signals in the echo, so that the main signals (main beams) are enhanced, side lobes (interference of other signals) are reduced, and the width increase of the main beams is minimum. In a practical way, the first signal of each channel is weighted to reduce the interference of other signals and enhance the main signal (main beam).

After the first signals of each channel are weighted, phase offsets exist between the first signals of each channel, and if a plurality of first signals are directly synthesized, gain loss is caused due to coherence of each first signal, so that the weighted signals need to be delayed and filtered, and a second signal corresponding to each channel can be obtained after delayed and filtered.

S103, synthesizing a first path of signals of the second signals of the plurality of channels to obtain a first path of synthesized signals, and synthesizing a second path of signals of the second signals of the plurality of channels to obtain a second path of synthesized signals.

The third signal comprises a first path of synthesized signal and a second path of synthesized signal.

It should be noted that the second signal is composed of a first signal and a second signal, where the first signal may be represented by an I signal, and the second signal may be represented by a Q signal; when the second signals of the multiple channels are synthesized into one signal, the I signals of the second signals of the multiple channels can be accumulated to obtain a first path of synthesized signal; and finally, synthesizing the second signals of the multiple channels to obtain a third signal consisting of the first synthesized signal and the second synthesized signal.

S104, demodulating and synthesizing the first path of synthesized signal to obtain a first path of demodulated and synthesized signal, and demodulating and synthesizing the second path of synthesized signal to obtain a second path of demodulated and synthesized signal.

The fourth signal includes a first path of demodulation and synthesis signal and a second path of demodulation and synthesis signal, and the demodulation and synthesis processing includes: demodulation processing and synthesis processing.

Before a sending end sends a signal to be transmitted, a digital baseband signal needs to be converted into a digital modulation signal suitable for channel transmission, namely a modulated signal or a frequency band signal; the receiving end needs to restore the modulated signal or the frequency band signal to the digital baseband signal through the demodulation process. The demodulation method comprises the following steps: sine wave amplitude demodulation, sine wave angle demodulation, and resonance demodulation.

In an implementation manner, the first path of synthesized signal is demodulated and then synthesized to obtain a first path of demodulated and synthesized signal, and the second path of synthesized signal is demodulated and then synthesized to obtain a second path of demodulated and synthesized signal, so that the first path of demodulated and synthesized signal and the second path of demodulated and synthesized signal can be processed in subsequent steps. Note that the signal type before demodulation is a real signal, and the signal type after demodulation is a complex signal.

And S105, carrying out low-pass filtering processing on the fourth signal to obtain a target signal.

In an implementation manner, the first path of demodulated and synthesized signal and the second path of demodulated and synthesized signal are respectively subjected to low-pass filtering processing to obtain a target signal. Specifically, the first path of demodulated and synthesized signal and the second path of demodulated and synthesized signal are respectively processed by two low-pass filters according to a preset frequency, signals higher than the preset frequency in the first path of demodulated and synthesized signal and the second path of demodulated and synthesized signal are filtered, all signals lower than the preset frequency are allowed to pass through, and finally a target signal is obtained.

The signal processing method provided by the embodiment of the invention carries out frequency reduction processing on a signal to be processed of each channel in a plurality of received channels to obtain a first signal; carrying out weighted delay processing on the first signal of each channel to obtain a second signal of each channel; synthesizing a first path of signals of the second signals of the plurality of channels to obtain a first path of synthesized signals, and synthesizing a second path of signals of the second signals of the plurality of channels to obtain a second path of synthesized signals; the third signal comprises a first path of synthesized signal and a second path of synthesized signal; demodulating and synthesizing the first path of synthesized signal to obtain a first path of demodulated and synthesized signal, and demodulating and synthesizing the second path of synthesized signal to obtain a second path of demodulated and synthesized signal; the fourth signal comprises a first path of demodulation and synthesis signal and a second path of demodulation and synthesis signal; the fourth signal is subjected to low-pass filtering processing to obtain a target signal, so that the signals to be processed of the multiple channels are demodulated and synthesized to obtain a first path of demodulated and synthesized signal and a second path of demodulated and synthesized signal, only two filters are needed when the signals to be processed of all the channels are subjected to low-pass filtering, the problem that the number of the filters needed when the signals to be processed of the multiple channels are subjected to low-pass filtering processing in the related art is large is solved, and the complexity of an SAR system is reduced.

Based on the foregoing embodiments, an embodiment of the present invention further provides a signal processing method, as shown in fig. 2, including the following steps:

s201, the signal processing equipment acquires multiple paths of intermediate frequency signals to be processed.

The multi-channel intermediate frequency signals to be processed are intermediate frequency echo signals received by a plurality of channels of an analog SAR system generated by MATLAB through programming, and can also be multi-channel intermediate frequency echo signals actually acquired from a plurality of apertures of the SAR system; and leading the multiple paths of intermediate frequency signals to be processed into signal processing equipment so that the signal processing equipment can carry out subsequent processing on the multiple paths of intermediate frequency signals.

S202, the signal processing equipment performs analog-to-digital conversion processing on the multiple paths of intermediate frequency signals to be processed to obtain signals to be processed of each channel.

In the embodiment of the invention, the multi-path intermediate frequency signals to be processed are analog signals, and the analog signals can be processed subsequently through the signal processing equipment only when being converted into digital signals.

In a feasible implementation manner, an A/D converter is adopted to perform analog-to-digital conversion processing on a plurality of paths of intermediate frequency signals to be processed to obtain signals to be processed of each channel, and the signals to be processed of each channel are digital signals; the analog-to-digital conversion mainly samples an analog signal, and then quantizes and encodes the analog signal into a binary digital signal.

S203, the signal processing equipment divides the signals to be processed of each channel to obtain a plurality of paths of first division signals for each channel.

Wherein the first signal comprises a plurality of first split signals.

In the embodiment of the present invention, the signal to be processed is an intermediate frequency signal, and when the frequency of the signal to be processed of each channel is subjected to down-conversion processing, the signal to be processed of each channel may be divided according to a preset division threshold, so as to obtain multiple first division signals corresponding to the preset division threshold, where the first division signals are low frequency signals. In the following, taking an example that the preset segmentation threshold is 4, the signal to be processed of each channel is segmented, and a multi-path first segmentation signal of each channel is obtained to be explained in detail.

In a possible implementation manner, the preset division threshold is 4, the signal to be processed of each channel can be divided into 4 paths of signals, and finally, 4 paths of first division signals can be obtained, where the frequency of each path of signal to be processed is 1/4 of the frequency of the signal to be processed.

It should be noted that the specific value of the preset dividing threshold corresponds to the specific number of the multiple paths of the first divided signals, for example, if the preset dividing threshold is n, n paths of the first divided signals can be finally obtained, and the frequency of the first divided signal is 1/n of the frequency of the signal to be processed. Wherein, the frequency of each path of first division signal is the same.

It should be noted that S204 or S205 may be executed after S203;

and S204, if the signal type of the multi-channel first division signal is consistent with the preset signal type, the signal processing equipment performs weighted delay processing on the multi-channel first division signal to obtain a second signal of each channel.

In one possible implementation, the predetermined signal type is a signed number type. And comparing the signal type of the multi-path first division signal of each channel with a preset signal type, and if the comparison result indicates that the signal type of the multi-path first division signal of each channel is consistent with the preset signal type, namely the signal type of the multi-path first division signal of each channel is a signed number type, performing weighted delay processing on the multi-path first division signal of each channel to obtain a second signal of each channel.

And S205, if the signal type of the multi-path first division signal is not consistent with the preset signal type, the signal processing equipment performs signal type conversion on the multi-path first division signal.

In a feasible implementation manner, the signal type of the multi-path first division signal of each channel is compared with a preset signal type, and if the comparison result indicates that the signal type of the multi-path first division signal of each channel is inconsistent with the preset signal type, that is, when the signal type of the multi-path first division signal of each channel is an unsigned number type, the signal type of the multi-path first division signal of each channel needs to be converted, so that the signal type of the multi-path first division signal obtained after conversion is consistent with the preset signal type and is a signed number type.

It should be noted that the unsigned number has no positive or negative score, all bits are used to represent the number itself, the most significant bit of the signed number is used to represent the positive or negative of the number, the most significant bit is 1 to represent a negative number, and the most significant bit is 0 to represent a positive number; when the unsigned number is converted into a signed number, whether the most significant bit of the unsigned number is 1 or not is judged, if not, the signed number is directly equal to the unsigned number; and if the most significant bit of the unsigned number is 1, complementing the unsigned number to obtain a signed number.

S206, the signal processing equipment carries out weighting delay processing on the multi-path first division signals after the signal type conversion to obtain a second signal of each channel.

The signal type of the converted multi-path first division signal is consistent with a preset signal type, and the preset signal type is a signed number type.

In the embodiment of the present invention, when the signal type of the converted multiple first division signals of each channel is a signed type, the converted multiple first division signals of each channel are subjected to weighted delay processing to obtain the second signal of each channel, so that the second signal of each channel is processed in the subsequent step.

It should be noted that S204 and S206 can be implemented by:

A. and the signal processing equipment carries out time synchronization on the multi-channel first division signals with the same type as the preset signals to obtain multi-channel time synchronization signals of each channel.

In the embodiment of the present invention, the processing speeds of the signal processing devices for the signals to be processed of each channel are different, which results in different times for acquiring the multiple first division signals of the same type as the preset signal, and in order to reduce the influence of the different times for acquiring the multiple first division signals of the same type as the preset signal on the weighted delay processing of each channel, time synchronization processing needs to be performed on the multiple first division signals of the same type as the preset signal, which are obtained by the multiple channels, before the weighted delay processing, so as to ensure time synchronization when the multiple first division signals of the same type as the preset signal are obtained by each channel.

In a feasible implementation manner, the multiple first division signals of all channels, which are consistent with the type of the preset signal, may be transferred to the same clock domain, so as to ensure time synchronization of the multiple first division signals of the multiple channels, which are consistent with the type of the preset signal, and obtain the multiple time synchronization signals of each channel, so as to process the multiple time synchronization signals in a subsequent step.

B. And the signal processing equipment carries out weighted delay processing on the multi-channel time synchronization signal of each channel to obtain a second signal of each channel.

In this embodiment, after obtaining the multiple channels of time synchronization signals of each channel, the signals perform weighted delay processing on the multiple channels of time synchronization signals of each channel, so as to obtain the second signal of each channel.

It should be noted that, after step 204 and step 206, the following steps may be performed:

s207, the signal processing equipment synthesizes a first path of signals of the second signals of the multiple channels to obtain a first path of synthesized signals, and synthesizes a second path of signals of the second signals of the multiple channels to obtain a second path of synthesized signals.

And S208, demodulating and synthesizing the first path of synthesized signal to obtain a first path of demodulated and synthesized signal, and demodulating and synthesizing the second path of synthesized signal to obtain a second path of demodulated and synthesized signal.

The fourth signal comprises a first path of demodulation and synthesis signal and a second path of demodulation and synthesis signal.

And S209, performing low-pass filtering processing on the fourth signal to obtain a target signal.

It should be noted that, for the descriptions of the same steps and the same contents in this embodiment as those in other embodiments, reference may be made to the descriptions in other embodiments, which are not described herein again.

It should be noted that, in the related art, a complex signal is obtained by demodulating a signal to be processed and then performing low-pass filtering processing, so that when performing weighted delay processing on the complex signal after low-pass filtering, complex multiplication operation is performed on the complex signal, so that the multiplication times are greatly increased, and in the technical scheme provided by the application, the weighted delay is to perform real multiplication operation on a real signal, so that the multiplication times are obviously reduced compared with the complex multiplication operation, the operation time is saved, and the time (operation) complexity of the SAR system is further reduced; and no matter whether the number of channels is increased or not, only two filters are adopted during low-pass filtering, so that the space complexity of the SAR system is reduced.

Based on the foregoing embodiments, an embodiment of the present invention provides a signal processing method, as shown in fig. 3, the method including:

s301, the signal processing equipment acquires multiple paths of intermediate frequency signals to be processed.

S302, the signal processing equipment performs analog-to-digital conversion processing on the multiple paths of intermediate frequency signals to be processed to obtain signals to be processed of each channel.

And S303, the signal processing equipment divides the signal to be processed of each channel to obtain a plurality of paths of first division signals for each channel.

Wherein the first signal comprises a plurality of first split signals.

It should be noted that S305 to S313 are performed if the signal type of the multi-path first segmentation signal is consistent with the predetermined signal type, and S304 to S313 are performed if the signal type of the multi-path first segmentation signal is inconsistent with the predetermined signal type.

And S304, the signal processing equipment performs signal type conversion on the multi-path first division signal.

S305, the signal processing equipment carries out time synchronization on the multi-path first division signal with the same type as the preset signal to obtain multi-path time synchronization signals of each channel.

S306, the signal processing equipment acquires the filter coefficient and the weighting parameter of each channel.

In the embodiment of the present invention, when performing the weighted delay processing on the multiple synchronous signals of each channel, it is necessary to obtain the filter coefficient of each channel and obtain the weighting parameter of each channel from the preset auxiliary data, so as to perform the weighted delay processing on the multiple synchronous signals of each channel according to the filter coefficient and the weighting parameter of each channel.

It should be noted that, for signal processing devices that process different signals to be processed, the formats of the preset auxiliary data are different; in one possible implementation, bits 4-8 of the auxiliary data are weighting parameters.

Wherein S306 can be realized through S306a-S306 b:

s306a, the signal processing device obtains filter group number information of each channel based on the identification information of each channel.

The identification information of each channel may be, but is not limited to, a serial number (channel number) of the channel, for example: the channel number of the 1 st channel is "1", the channel number of the second channel is "2", and the filter bank number information is stored in the preset auxiliary data. And acquiring the filter group number information of each channel from preset auxiliary data based on the identification information of each channel.

In the embodiment of the present invention, the information of the number of filter groups in the preset auxiliary data is controlled and retrieved based on the identification information of the channel by a clock signal in the signal processing device, and the specific process is as follows: the signal processing apparatus may control which channel of the filter bank number information in the preset auxiliary data is specifically extracted by controlling the clock signal. For example: the clock signal has a plurality of states, each state has a corresponding operation channel, and the information of the number of filter groups of each channel is extracted through the periodic operation of the plurality of states of the clock signal.

In a possible implementation manner, in the clock signal, the extraction of the filter group number information of which channel from the preset auxiliary data is controlled by the control signal S0, wherein the states of 5, 6,7, 9, 11, 12, 13, 14, 17, 18, 19, 22, 24, 25, 27, 28 of S0 correspond to the filter group number information of 1, 2, 3, 4, 5, 6,7, 8, 9, 10, 11, 12, 13, 14, 15, 16 channels, respectively. The filter bank number information needs to be transmitted according to the filter bank number signal.

It should be noted that the filter bank number information needs to be transmitted according to the filter bank number signal, but since the filter bank number signal belongs to the register signal and cannot be transmitted in the signal processing apparatus, an intermediate signal, that is, an intermediate filter bank number signal is needed. And the intermediate filter bank number signal is transmitted in the signal processing equipment instead of the filter bank number signal, so that the transmission of the filter bank number information is realized.

In a possible implementation manner, the signal processing device controls an intermediate filter bank number signal carrying filter bank number information of preset auxiliary data of a channel corresponding to the state according to the state of the clock signal, so that the intermediate filter bank number signal can transfer the filter bank number information carrying the channel to a filter corresponding to the channel.

In a possible implementation manner, the signal processing device controls, according to the state of the clock signal, a weighting parameter signal carrying a weighting parameter of the preset auxiliary data of the channel corresponding to the state, so that the weighting parameter signal can transfer the weighting parameter to the signal processing device, so as to process the first signal according to the weighting parameter in a subsequent step.

S306b, the signal processing apparatus acquires the filter coefficient and weighting parameter of each channel based on the filter group number information of each channel.

In the embodiment of the present invention, the weighting parameter of each channel may be extracted from the preset auxiliary data through the information of the number of filter groups of each channel.

In a possible implementation manner, for the filter bank number information of any channel, the weighting parameter corresponding to the channel may be extracted from the preset auxiliary data based on the filter bank number information of the channel, and then the filter bank number information is transmitted to the filter corresponding to the channel based on the intermediate filter bank number signal carrying the filter bank number information of the channel, and the corresponding filter coefficient is determined from a plurality of filter coefficients pre-stored in the filter of the channel based on the filter bank number information of the channel.

It should be noted that, a plurality of filter coefficients calculated in advance are stored in the filter of each channel, and based on the filter group number information carried in the intermediate filter group number signal received by the filter, the filter coefficient corresponding to the filter group number information can be determined from the stored plurality of filter coefficients.

The calculation process of the filter coefficients is explained in detail below.

The filter coefficients are calculated as follows:

kernal＝(1:points)-points/2+pianyi

sincindex＝kernal

outfirval＝sinc(sincindex)

wherein, kernal refers to a group of point sequences and represents the serial numbers from the first channel to the last channel, and the kernal takes the central channel as 0 and is symmetrically distributed in positive and negative directions; points refers to the number of channels, pianyi refers to an offset, pianyi is delay/dis, and delay is the delay between a signal received by the channel and a reference channel; dis is the pitch of each channel center; sinindex is a variable name provided separately for distinguishing between functions. By the above calculation, filter coefficients of a plurality of channels can be obtained.

In a possible implementation, the filter coefficients of multiple channels are generated and stored in the filter by the fdatool tool of MATLAB, and the file with the suffix of coe is generated and stored in the filter, and the filter of each channel can store the filter coefficients of multiple channels in advance. .

S307, the signal processing equipment carries out weighting processing on the multi-channel time synchronization signal of each channel based on the weighting parameter of each channel to obtain the multi-channel weighting signal of each channel.

In a feasible implementation manner, after the weighting parameter of each channel is obtained, a weight may be generated according to the weighting parameter of each channel, and the multi-path time synchronization signal of the channel is weighted by the generated weight, so that the multi-path weighting signal of each channel may be obtained finally.

S308, the signal processing equipment sets parameters of the filter based on the filter coefficient of each channel, and performs delay filtering processing on the multipath weighted signals by adopting the filter with the set parameters to obtain multipath delay filtering signals of each channel.

In a feasible implementation manner, parameters of the filter are set according to the filter coefficients of each channel, and after the parameters are set, the filter after the parameters are set is used for performing delay filtering processing on the multipath weighted signals to obtain multipath delay filtered signals of each channel.

It should be noted that the parameter setting of the filter can be implemented in various ways, such as: for the filter of any channel, after acquiring the corresponding filter coefficient from the multiple filter coefficients stored in the filter of the channel based on the filter group number information, the parameter may be automatically set, or the signal processing device sets the parameter of the filter according to the filter coefficient.

It should be noted that the filter is a Finite Impulse Response (FIR) filter, and the FIR filter is also called a non-recursive filter; the FIR filter can ensure any amplitude-frequency characteristic and has strict linear phase-frequency characteristic, and the unit sampling response of the FIR filter is finite.

In the embodiment of the invention, the multipath weighted signals of the channel are subjected to delay filtering processing through the filter with the set parameters to obtain the multipath delay filtering signals corresponding to each channel, so that the phenomenon that the receiving gain is reduced due to pulse width extension loss caused by a certain width of radar pulse is avoided.

It should be noted that the pulse width Extension Loss (PEL) phenomenon is a phenomenon that the echo gain of a single-point target cannot be maximized within the whole pulse width by adjusting the DBF beam pointing in real time because the pulse of a radar wave has a certain width, the signal spectrum is weighted, the high-frequency component of the signal is reduced, so that the main lobe is widened after the pulse compression, and the reception gain is reduced.

S309, the signal processing equipment carries out synthesis processing on the multi-channel delay filtering signals of each channel to obtain a second signal of each channel.

In the embodiment of the invention, the weighted signal of each channel is subjected to delay filtering to obtain a plurality of paths of delay filtering signals, and the plurality of paths of delay filtering signals of each channel can be subjected to synthesis processing to obtain a second signal, so that the computational complexity of signal processing in the subsequent process is reduced.

S310, the signal processing equipment synthesizes a first path of signals of the second signals of the channels to obtain a first path of synthesized signals, and synthesizes a second path of signals of the second signals of the channels to obtain a second path of synthesized signals.

S311, performing orthogonal demodulation processing on the first path of synthesized signal to obtain a first path of demodulated signal and a second path of demodulated signal, and performing orthogonal demodulation processing on the second path of synthesized signal to obtain a third path of demodulated signal and a fourth path of demodulated signal.

The first path of synthesized signal and the second path of synthesized signal are both real signals, and after orthogonal demodulation is respectively carried out on the first path of synthesized signal and the second path of synthesized signal, the obtained first path of demodulated signal and the second path of demodulated signal form complex signals; the third path of demodulation signal and the fourth path of demodulation signal form a complex signal.

After the first synthesized signal is subjected to quadrature demodulation, 2 paths of signals can be obtained, namely a first path of demodulated signal and a second path of demodulated signal, wherein the first path of demodulated signal is an I signal, and the second path of demodulated signal is a Q signal; and performing orthogonal demodulation on the second path of synthesized signal to obtain 2 paths of signals, namely a third path of demodulated signal and a fourth path of demodulated signal. The third path of demodulation signal is an I signal, and the fourth path of demodulation signal is a Q signal.

It should be noted that, when performing orthogonal demodulation on the first path of synthesized signal and the second path of synthesized signal, the frequency and the sampling frequency when the signal to be processed is an intermediate frequency signal may be substituted into the demodulation coefficient, and finally, the first path of demodulated signal, the second path of demodulated signal, the third path of demodulated signal, and the fourth path of demodulated signal after orthogonal demodulation may be obtained.

S312, the signal processing equipment synthesizes the first path of demodulation signal and the third path of demodulation signal to obtain a first path of demodulation synthesized signal, and synthesizes the second path of demodulation signal and the fourth path of demodulation signal to obtain a second path of demodulation synthesized signal.

In the embodiment of the present invention, the first path of demodulation signal and the third path of demodulation signal are synthesized to obtain the first path of demodulation synthesized signal, that is, 2 paths of I signals are accumulated to obtain one path of I signal (that is, the first path of demodulation synthesized signal), and the second path of demodulation signal and the fourth path of demodulation signal are synthesized to the second path of demodulation synthesized signal, that is, 2 paths of Q signals are accumulated to obtain one path of Q signal (that is, the second path of demodulation synthesized signal).

And S313, the signal processing equipment performs low-pass filtering processing on the fourth signal to obtain a target signal.

Based on the foregoing embodiments, an embodiment of the present invention provides a signal flow schematic diagram of a signal processing method, where the method is applied to a signal processing device, and as shown in fig. 4, a processing procedure of the signal processing method is explained in detail by using the signal processing device as an FPGA and using a specific number of channels of a plurality of channels as 16.

As shown in fig. 4, 2 FPGAs respectively receive 8 channels of intermediate frequency signals to be processed, and perform analog-to-digital conversion processing on the 8 channels of intermediate frequency signals to be processed, after processing, each FPGA can obtain 8 channels of signals to be processed, and each FPGA can cache the 8 channels of signals to be processed in a cache module in the FPGA, so that the signals to be processed of each channel are subsequently retrieved from the cache module, and the signals to be processed of each channel are subsequently processed. (in the embodiment of the present invention, the processing flow of dividing the signal to be processed to obtain the multi-channel first divided signals for each channel is not shown in fig. 4.)

As shown in fig. 4, the multi-channel first division signal having the same type as the preset signal is time-synchronized to obtain a multi-channel time-synchronized signal for each channel, the filter bank number information of each channel is obtained from the preset auxiliary data based on the identification information of each channel, the weighting parameter of each channel is obtained based on the filter bank number information of each channel, and the multi-channel time-synchronized signal of each channel is weighted based on the weighting parameter of each channel obtained from the auxiliary data, so that the multi-channel weighted signal of each channel can be obtained.

For any channel, transmitting an intermediate filter bank number signal carrying filter bank number information of the channel to a filter corresponding to the channel, selecting a filter coefficient corresponding to the filter bank number information from a plurality of filter coefficients stored in the filter in advance, and setting parameters of the filter through the selected filter coefficient.

In a feasible implementation manner, as shown in fig. 5, the FPGA controls an intermediate filter bank number signal carrying filter bank number information of preset auxiliary data of a channel corresponding to a state according to the state of a clock signal, so that the intermediate filter bank number signal can transmit the filter bank number information carrying the channel to a filter of the channel, then selects a filter coefficient corresponding to the filter bank number information from a plurality of filter coefficients pre-stored in the filter, sets specific parameters of the filter based on the selected filter coefficient, and performs delay filtering processing on a multi-channel weighted signal by using the filter with the set parameters, so as to obtain a multi-channel delay filtered signal of each channel. And synthesizing the multi-path delay filtering signals of each channel to obtain a second signal of each channel. (in the embodiment of the present invention, the synthesis process is performed on the multi-path delay filtered signal of each channel, which is not shown in fig. 4).

As shown in fig. 4, each FPGA may synthesize a first path of signals of second signals of 8 channels to obtain a first path of synthesized signals, and synthesize a second path of signals of the second signals of 8 channels to obtain a second path of synthesized signals, where the first path of synthesized signals and the second path of synthesized signals form a third path of signals, and 2 FPGAs may finally obtain a third path of signals respectively, and any one FPGA of the 2 FPGAs may cache the third signal obtained by the FPGA, so as to call the cached third signal from the cache module and synthesize a third signal transmitted by another FPGA, and obtain the first path of synthesized signals and the second path of synthesized signals again after synthesis, where the first path of synthesized signals and the second path of synthesized signals are obtained by processing signals to be processed of 16 channels.

It should be noted that, if the specific number of the channels is 8, only 1 FPGA is needed to obtain a third signal, where the third signal is composed of a first synthesized signal and a second synthesized signal, and the first synthesized signal and the second synthesized signal are obtained by processing signals to be processed of 8 channels.

And performing orthogonal demodulation processing on the first path of synthesized signal to obtain a first path of demodulated signal and a second path of demodulated signal, and performing orthogonal demodulation processing on the second path of synthesized signal to obtain a third path of demodulated signal and a fourth path of demodulated signal. And synthesizing the 4 paths of demodulation signals obtained by the orthogonal demodulation to obtain a first path of demodulation synthesized signal and a second path of demodulation synthesized signal. And performing low-pass filtering processing on the first path of demodulation and synthesis signal and the second path of demodulation and synthesis signal by respectively adopting a low-pass filter, and obtaining a target signal after processing. And carrying out cache processing on the target signal, calling the target signal from the cache module and outputting the target signal through an optical fiber.

In the embodiment of the present invention, taking the signal processing devices as an FPGA and a computer device as examples, when the signal processing device is a computer device, a malt program for implementing the signal processing method is stored on the computer device, and the following explains the signal processing method implemented on the computer device and the signal processing method implemented on the FPGA in detail through the drawings.

The data of the row with the number "1" shown in FIG. 6A corresponds to the data of the first channel, which corresponds to data in [0] -data in [3] in FIG. 6B, and each signal to be processed is divided into 4 paths during the down-conversion process, so the comparison needs to be performed on a 4 basis. For example: "-126" in the first lane of FIG. 6A corresponds to the first column number of data in [0] in FIG. 6B; "-117" in the first lane of FIG. 6A corresponds to the first column number of data in [1] in FIG. 6B; "-101" in the first lane in FIG. 6A corresponds to the first column number for data in [2] in FIG. 6B; "-77" in the first lane of FIG. 6A corresponds to the first column number of data in [3] in FIG. 6B; as can be seen from comparison between fig. 6A and fig. 6B, the processing of the signal to be processed before the delay filtering can be implemented on both the FPGA and the computer device, and comparison between fig. 6A and fig. 6B shows that the processing result obtained by the FPGA and the processing result obtained by the computer device before the delay filtering are the same.

As shown in fig. 7A, the data in the row of the number "1" is the data of the first channel, corresponding to the data of the filter _ out _0_8bit to the filter _ out _3_8bit in fig. 6B, each path of the signal to be processed is divided into 4 paths during the down-conversion process, so the comparison needs to be performed on the basis of 4. For example: "-1" in the first channel in FIG. 7A corresponds to the first column count of filter _ out _0_8 bits in FIG. 7B; "-126" in the first channel of FIG. 7A corresponds to the first column count of filter _ out _1_8 bits in FIG. 7B; "-116" in the first channel of FIG. 7A corresponds to the first column count of filter _ out _2_8 bits in FIG. 7B; "-101" in the first channel in fig. 7A corresponds to the first column count of filter _ out _3_8 bits in fig. 7B. As can be seen from fig. 7A and 7B, both the FPGA and the computer device can implement the delay filtering processing on the signal to be processed, and the processing results obtained after the delay filtering processing is performed on the FPGA and the computer device on the signal to be processed are the same.

As shown in FIG. 8A, the first 8 data lines of "1" correspond to data _ jietiao 1-data _ jietiao8 in FIG. 8B, since each FPGA processes 8 signals to be processed, 8 comparison is needed, as 3.5504 in FIG. 8A corresponds to the first column number of data _ jietiao 1; 12.4717 corresponds to the first column count of data _ jietiao 2; -4.8942 corresponds to the first number of columns of d data _ jietiao 3; it should be noted that, in fig. 8A, 2 FPGAs process data shown by signals to be processed. As can be seen from fig. 8A and 8B, the orthogonal demodulation processing can be implemented on both the FPGA and the computer device for the signal to be processed, and the processing results obtained after the orthogonal demodulation processing is performed on the FPGA and the computer device for the signal to be processed are slightly different. Before orthogonal demodulation of a signal to be processed is realized on the FPGA, A/D sampling is calculated in a digital form of 8 bits; before the quadrature demodulation of the signal to be processed is realized on the computer equipment, the A/D sampling is calculated in a digital form of 64 bits, so that quantization error exists, but the error is small and can be ignored, and the comparison can show that the quadrature demodulation method in the FPGA is correct.

Based on the foregoing embodiments, an embodiment of the present invention provides a signal processing apparatus, which may be applied to the signal processing method provided in the embodiments corresponding to fig. 1 to 3, and as shown in fig. 9, the apparatus may include: a processor 91, a memory 92, and a communication bus 93, wherein:

the communication bus 93 is used for realizing communication connection between the processor 91 and the memory 92;

the processor 91 is configured to execute a signal processing program stored in the memory 92 to implement the following steps:

carrying out weighted delay processing on the first signal of each channel to obtain a second signal of each channel;

synthesizing a first path of signals of the second signals of the plurality of channels to obtain a first path of synthesized signals, and synthesizing a second path of signals of the second signals of the plurality of channels to obtain a second path of synthesized signals; the third signal comprises a first path of synthesized signal and a second path of synthesized signal;

demodulating and synthesizing the first path of synthesized signal to obtain a first path of demodulated and synthesized signal, and demodulating and synthesizing the second path of synthesized signal to obtain a second path of demodulated and synthesized signal; the fourth signal comprises a first path of demodulation and synthesis signal and a second path of demodulation and synthesis signal;

In other embodiments of the present invention, the processor 91 is configured to execute the signal to be processed stored in the memory 92 to implement the following steps:

dividing the signal to be processed of each channel to obtain a plurality of paths of first division signals for each channel; wherein the first signal comprises a plurality of first split signals.

In other embodiments of the present invention, the processor 91 is configured to perform weighted delay processing on the first signal of each channel stored in the memory 92 to obtain the second signal of each channel, so as to implement the following steps:

and if the signal type of the multi-path first division signal is consistent with the preset signal type, performing weighted delay processing on the multi-path first division signal to obtain a second signal of each channel.

In other embodiments of the present invention, the processor 91 is configured to execute the plurality of first split signals stored in the memory 92 to implement the following steps:

and performing weighted delay processing on the multi-path first division signals after the signal type conversion to obtain a second signal of each channel, wherein the signal type of the multi-path first division signals after the conversion is a preset signal type.

In other embodiments of the present invention, the processor 91 is configured to perform weighted delay processing on the multiple first split signals, which are stored in the memory 92 and are consistent with the preset signal type, to obtain the second signal of each channel, so as to implement the following steps:

and carrying out weighted delay processing on the multi-channel time synchronization signal of each channel to obtain a second signal of each channel.

In other embodiments of the present invention, the processor 91 is configured to perform weighted delay processing on the multiple time synchronization signals of each channel stored in the memory 92 to obtain the second signal of each channel, so as to implement the following steps:

acquiring a filter coefficient and a weighting parameter of each channel;

setting parameters of a filter based on the filter coefficient of each channel, and performing delay filtering processing on the multipath weighted signals by adopting the filter with the set parameters to obtain multipath delay filtering signals of each channel;

and synthesizing the multi-path delay filtering signals of each channel to obtain a second signal of each channel.

In other embodiments of the present invention, the processor 91 is configured to execute the steps stored in the memory 92 of obtaining the filter coefficients and weighting parameters for each channel to implement the following steps:

acquiring filter group number information and weighting parameters of each channel based on the identification information of each channel;

and acquiring the filter coefficient of each channel from the filter group number information of each channel.

In other embodiments of the present invention, the processor 91 is configured to execute the demodulation and synthesis processing on the first synthesized signal stored in the memory 92 to obtain a first demodulated and synthesized signal, and perform the demodulation and synthesis processing on the second synthesized signal to obtain a second demodulated and synthesized signal, so as to implement the following steps:

and synthesizing the first path of demodulation signal and the third path of demodulation signal to obtain a first path of demodulation synthesized signal, and synthesizing the third path of demodulation signal and the fourth path of demodulation signal to a second path of demodulation synthesized signal.

In other embodiments of the present invention, the processor 91 is configured to perform the following steps before performing the frequency reduction processing on the received signal to be processed of each of the multiple channels stored in the memory 92 to obtain the first signal:

It should be noted that, for a specific implementation process of the steps executed by the processor in this embodiment, reference may be made to the implementation processes in the signal processing method provided in the embodiments corresponding to fig. 1 to 3, and details are not described here again.

The signal processing device provided by the embodiment of the invention demodulates and synthesizes the signals to be processed of the multiple channels to obtain the first path of demodulated and synthesized signal and the second path of demodulated and synthesized signal, only two filters are needed when the signals to be processed of all the channels are subjected to filtering processing, the problem that the number of the filters needed when the signals to be processed of the multiple channels are subjected to low-pass filtering processing in the related art is large is solved, and the complexity of an SAR system is reduced.

Based on the foregoing embodiments, the embodiments of the present invention provide a computer-readable storage medium, which stores one or more programs, where the one or more programs are executable by one or more processors to implement the steps in the signal processing method provided by the embodiments corresponding to fig. 1-3.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A method of signal processing, the method comprising:

2. The method of claim 1, wherein down-converting the received signal to be processed for each of the plurality of channels to obtain the first signal comprises:

3. The method of claim 2, wherein the performing weighted delay processing on the first signal of each channel to obtain the second signal of each channel comprises:

4. The method of claim 3, further comprising:

5. The method according to claim 3 or 4, wherein performing weighted delay processing on the multiple first division signals in accordance with the preset signal type to obtain the second signal of each channel comprises:

6. The method according to claim 5, wherein said performing weighted delay processing on the multiple time synchronization signals of each channel to obtain the second signal of each channel comprises:

acquiring a filter coefficient and a weighting parameter of each channel;

7. The method of claim 6, wherein obtaining the filter coefficients and weighting parameters for each channel comprises:

8. The method of claim 1, wherein the demodulating and synthesizing the first path of synthesized signal to obtain a first path of demodulated and synthesized signal, and demodulating and synthesizing the second path of synthesized signal to obtain a second path of demodulated and synthesized signal comprises:

9. The method of claim 1, wherein before down-converting the received signal to be processed for each of the plurality of channels to obtain the first signal, the method comprises:

10. A signal processing apparatus, characterized in that the apparatus comprises: a processor, a memory, and a communication bus;

11. A computer-readable storage medium, characterized in that the computer-readable storage medium stores one or more programs which are executable by one or more processors to implement the steps of the signal processing method according to any one of claims 1 to 9.