CN107863967B - Multichannel synchronous output calibration device and method - Google Patents
Multichannel synchronous output calibration device and method Download PDFInfo
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Abstract
The invention discloses a multichannel synchronous output calibration device and method. The calibration device comprises a clock module, a clock delay module, a waveform generation module, a pulse shaping module, a logic AND gate module, a pulse width measurement module and a synchronous control module. The pulse shaping module, the logic AND gate module and the pulse width measurement module are adopted to obtain the synchronous delay error among the channels, the circuit structure is simple, the hardware implementation is easy, the complex calculation is avoided, an ADC (analog to digital converter) circuit and a high-performance calculation module are not needed, and the cost is low. When the error is corrected, the calibration device sequentially adjusts the sampling clock delay and the waveform phase through the clock delay module and the waveform generation module until the synchronous delay error among the channels meets the design requirement, the precision is high, and the channel consistency is good. In addition, the pulse width measurement module adopts a mode of matching precise delay adjustment and edge detection, and the pulse width measurement error is effectively reduced.
Description
Technical Field
The invention belongs to the field of arbitrary waveform generation, and particularly relates to a multichannel synchronous output calibration device and method.
Background
The arbitrary waveform generator is a signal generating source based on digital, analog and computer technologies, can provide some conventional function waveforms, complex editable waveforms, environment analog signals, digital modulation signals and the like, and is widely applied to various fields of radar, communication, biomedical and chip detection and the like. Generally, an arbitrary waveform generator integrates a plurality of output channels, meets the requirements of users on multi-path waveform signals, has strong signal excitation capability, and the abundant signal excitation capability comprises a high-speed waveform generator, a function generator, a pulse/sequence generator, a sweep frequency generator, a trigger generator, a broadband white noise signal generator, an amplitude modulation source and the like. Meanwhile, the multipath waveform signals need to keep accurate phase relation and can be synchronously output so as to meet the requirement of modern time domain test. With the development of electronic technology, the multichannel arbitrary waveform generator can play an important role in a variety of applications such as broadband communication, radar systems, high-speed pulse simulation, high-speed digital design, field environment simulation and playback, and the like.
The inter-channel delay error is one of the main factors affecting the channel synchronization, and mainly consists of the deviation between sampling clocks and the channel delay. The correction of the delay error is the key to the channel synchronization calibration. Currently, the error calibration method can be divided into calibration using a dedicated instrument outside the instrument and calibration using a circuit module inside the instrument.
The external calibration is mainly characterized in that the external part of the instrument is interconnected with an arbitrary waveform generator through special equipment, a plurality of channels of the arbitrary waveform generator respectively output signals for determining phase difference, the special equipment measures phase errors, and the phase of the waveform output by the arbitrary waveform generator is adjusted according to the measurement result to compensate. The method can realize high-precision synchronization among the channels.
The existing external synchronous calibration mode adopts special calibration equipment to calibrate the multi-channel output of the arbitrary waveform generator, so that the overhead is high. The calibration equipment and the arbitrary waveform generator need to open a data interaction port to realize calibration data transmission, and the operation is complex. When the external environment of any waveform generator changes, the characteristics of components in the output channels may deviate, which causes the increase of synchronous delay errors among the channels, and thus recalibration is required. The external synchronous calibration operation has poor repeatability and long time consumption.
The internal calibration of the instrument is mainly to embed a calibration circuit module in an arbitrary waveform generator, wherein the circuit module adopts a multi-channel ADC chip to collect output signals of each channel in a certain time interval, carries out a series of operations such as correlation and inverse trigonometric functions on the collected multi-channel signals to obtain phase differences among the signals, then calculates by combining the time interval to obtain delay errors among the channels, and finally corrects the delay errors by adjusting the waveform phase of the channels.
Because the circuit of the internal calibration of the existing instrument is an internal calibration module based on ADC, a multi-path ADC circuit in the internal calibration module needs to be designed with low distortion, and the requirement of a hardware circuit is high. When calculating the phase difference between signals, a series of operations such as correlation and inverse trigonometric functions are performed, and the amount of calculation is large. In order to solve the problem of large calculation amount, the internal calibration module needs to be configured with a high-performance calculation module so as to improve the calculation efficiency. Meanwhile, when the error is corrected, the internal calibration module only adjusts the waveform phase, and cannot correct the error caused by the delay of the sampling clock, so that the problem of poor channel consistency is caused.
Disclosure of Invention
The invention aims to provide a multichannel synchronous output calibration device which is simple in structure and high in synchronization precision.
In order to achieve the purpose, the invention adopts the following technical scheme:
a multichannel synchronous output calibration device comprises a clock module, a clock delay module, a waveform generation module, a pulse shaping module, a logic AND gate module, a pulse width measurement module and a synchronous control module;
wherein, the signal flow in each hardware module is:
sine wave signals output by each channel are input to a pulse shaping module for pulse shaping to obtain square wave signals;
appointing a reference channel, and performing logic AND operation on other channels and the square wave signal of the reference channel in a logic AND gate module in sequence to obtain a pulse signal;
the pulse width measuring module calculates the delay error between the channels by measuring the pulse width of the pulse signal;
the synchronous control module controls the clock delay module and the waveform generation module to sequentially adjust the sampling clock delay and the waveform phase of the channel according to the delay error obtained by measurement, and corrects the delay error;
the clock module is used for providing a homologous clock for the multi-channel synchronous output calibration device.
Preferably, the waveform generation module adopts a DDS waveform generation principle and is realized by FPGA logic;
the waveform generation module addresses a waveform lookup table at the rising edge of each clock according to the sine wave data phase value calculated by the phase accumulator to acquire corresponding sine wave data; the sine wave data is converted into a sine wave analog signal by the DAC.
Preferably, the clock delay module precisely delays the sampling clock of the DAC through the delay chip, so that an adjustable phase relationship occurs between DAC clocks corresponding to arbitrary wave channels, thereby changing the delay between DAC output signals.
Preferably, the pulse shaping module converts the sine wave signal into a level signal through a level conversion circuit.
Preferably, the pulse width measurement module comprises a precision delay adjustment module, an edge detection module, a counter, a pulse width calculation module and a measurement control module; wherein:
the edge detection module is matched with the counter to measure and obtain a time interval T1 of a sampling rising edge and a sampling falling edge; the precise time delay adjusting module is matched with the edge detecting module to measure and obtain a time interval T2 between the actual edge of the pulse signal and the sampling edge;
and the measurement control module controls the pulse width calculation module to calculate the pulse width time according to the time interval T1 and the time interval T2.
In addition, the invention also provides a multichannel synchronous output calibration method, which adopts the following technical scheme:
a calibration method of multichannel synchronous output is disclosed, wherein the adopted calibration device comprises a clock module, a clock delay module, a waveform generation module, a pulse shaping module, a logic AND gate module, a pulse width measurement module and a synchronous control module;
the channel synchronous output calibration method comprises the following steps:
s1. inputting the sine wave signal output by each channel into a pulse shaping module for pulse shaping to obtain square wave signal;
s2, a reference channel is designated, and other channels sequentially carry out logical AND operation with the square wave signals of the reference channel in a logical AND gate module so as to obtain pulse signals;
s3. pulse width measurement module calculates the delay error between channels by measuring the pulse width of pulse signal;
s4. the synchronous control module controls the clock delay module and the waveform generation module to adjust the sampling clock delay and the waveform phase of the channel in turn according to the delay error obtained by measurement, and corrects the delay error;
s5. repeating the above operations of measuring and correcting the delay error;
and when the delay errors of all the channels reach the design requirement, completing the synchronization among the channels.
Preferably, in step s3, the step of calculating the delay error by using the pulse width measurement module is as follows:
the pulse width measuring module comprises a precise delay adjusting module, an edge detecting module, a counter, a pulse width calculating module and a measuring control module; the precise DELAY adjustment module is realized by adopting IO _ DELAY resources of the FPGA;
the stepping time interval of the IO _ DELAY resource is delta, the stepping number is N, and the total DELAY time is delta multiplied by N;
the edge detection module samples the pulse signals at the rising edge of each FPGA clock;
the period of the FPGA clock is T _ clk; the high level sampling of the pulse signal is logic 1, the low level sampling is logic 0, and the high level sampling is the sampling rising edge of the pulse signal when the logic 0 is changed into the logic 1, otherwise, the low level sampling is the sampling falling edge;
the edge detection module is matched with the counter to measure and obtain a time interval T1 of a sampling rising edge and a sampling falling edge; the precise time delay adjusting module is matched with the edge detecting module to measure and obtain a time interval T2 between the actual edge of the pulse signal and the sampling edge;
the stepping number of the precise delay adjusting module is increased by 1, and the delay is increased by delta;
the edge detection module detects whether the position of the sampling edge of the pulse signal changes, and repeats the operation until the position of the sampling edge changes, so as to obtain the step pitch number of the precision delay adjustment module, the delay step pitch number N1 of the actual rising edge from the sampling rising edge and the delay step pitch number N2 of the actual falling edge from the sampling falling edge;
the measurement control module controls the pulse width calculation module to calculate the pulse width time A according to T1 and T2, and the calculation expression is as follows:
A＝Δδ×(N1+N2)+T_clk×M (1)
wherein, Δ δ is the delay stepping time interval of the precision delay adjustment module, and T _ clk is the period of the FPGA clock;
the synchronous control module calculates to obtain a synchronous delay error tau between channels according to the pulse width time A, and the calculation expression is as follows:
wherein, T _ sig is the period of the output signal.
Preferably, in the step s4, the specific process of correcting the delay error is as follows:
the time delay stepping time interval of the clock time delay module is delta rho, the stepping pitch is K, and the total time delay time is delta rho multiplied by K;
the waveform generation module realizes different phases of output signals by adjusting initial phase deviation values of waveform data of all channels, so that the time delay among the waveform data is changed; resolution of waveform generation module phase adjustment
Is composed of
Wherein, L is the bit number of the phase adder, and the calculation expression of the delay stepping time interval Δ S between waveform data is:
the expression epsilon of the synchronous delay compensation error is as follows:
ε＝|(Δρ×a+ΔS×b)-τ| (4)
wherein, a is the stepping pitch number of the clock delay module, and b is the stepping pitch number of the waveform generation module; and the synchronous control module traverses the values of a and b to ensure that epsilon reaches the minimum value, thereby realizing the minimum synchronous delay error after compensation.
The invention has the following advantages:
the multi-channel synchronous output calibration device is integrated in an arbitrary waveform generator. The calibration device comprises a clock module, a clock delay module, a waveform generation module, a pulse shaping module, a logic AND gate module, a pulse width measurement module and a synchronous control module. The pulse shaping module, the logic AND gate module and the pulse width measurement module are adopted to obtain the synchronous delay error among the channels, the circuit structure is simple, the hardware implementation is easy, the complex calculation is avoided, an ADC (analog to digital converter) circuit and a high-performance calculation module are not needed, and the cost is low. When the error is corrected, the calibration device sequentially adjusts the sampling clock delay and the waveform phase through the clock delay module and the waveform generation module until the synchronous delay error among the channels meets the design requirement, the precision is high, and the channel consistency is good. In addition, the pulse width measurement module adopts a mode of matching precise delay adjustment and edge detection, and the pulse width measurement error is effectively reduced.
Drawings
FIG. 1 is a schematic block diagram of a multi-channel synchronous output calibration apparatus according to the present invention;
FIG. 2 is a flow chart of a multi-channel synchronous output calibration method according to the present invention;
FIG. 3 is a timing diagram illustrating pulse shaping and logic and operations in accordance with the present invention;
FIG. 4 is a schematic block diagram of the pulse width measurement module according to the present invention;
FIG. 5 is a timing diagram of the pulse width measurement module of the present invention.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description:
referring to fig. 1, a multi-channel synchronous output calibration apparatus includes a clock module, a clock delay module, a waveform generation module, a pulse shaping module, a logic and gate module, a pulse width measurement module, and a synchronous control module.
Wherein, the signal flow in each hardware module is:
sine wave signals output by each channel are input to a pulse shaping module for pulse shaping to obtain square wave signals;
appointing a reference channel, and performing logic AND operation on other channels and the square wave signal of the reference channel in a logic AND gate module in sequence to obtain a pulse signal;
the pulse width measuring module calculates the delay error between the channels by measuring the pulse width of the pulse signal;
and the synchronous control module controls the clock delay module and the waveform generation module to sequentially adjust the sampling clock delay and the waveform phase of the channel according to the delay error obtained by measurement, and corrects the delay error.
The clock module is used for providing a homologous clock for the multi-channel synchronous output calibration device. After the clock module is stabilized, the calibration device starts the process of synchronous calibration, and the overall work flow chart is shown in fig. 2.
A calibration device adopted by the calibration method comprises a clock module, a clock delay module, a waveform generation module, a pulse shaping module, a logic AND gate module, a pulse width measurement module and a synchronous control module.
The channel synchronous output calibration method comprises the following steps:
s1. inputting the sine wave signal output by each channel into a pulse shaping module for pulse shaping to obtain square wave signal;
s2, a reference channel is designated, and other channels sequentially carry out logical AND operation with the square wave signals of the reference channel in a logical AND gate module so as to obtain pulse signals;
s3. pulse width measurement module calculates the delay error between channels by measuring the pulse width of pulse signal;
s4. the synchronous control module controls the clock delay module and the waveform generation module to adjust the sampling clock delay and the waveform phase of the channel in turn according to the delay error obtained by measurement, and corrects the delay error;
s5. repeating the above operations of measuring and correcting the delay error;
and when the delay errors of all the channels reach the design requirement, completing the synchronization among the channels.
The arbitrary waveform generator sets one channel as a reference channel and the other channels as channels to be calibrated. The reference channel is used as a comparison channel for measuring the synchronous delay among the channels, and other channels are synchronous with the reference channel, so that the synchronization of all the channels is achieved.
Firstly, the waveform generation module of each channel simultaneously outputs sine wave data under the control of the synchronous control module, and the period of the sine wave is T _ sig. The waveform generation module adopts a DDS waveform generation principle and is realized by FPGA logic. And the waveform generation module addresses the waveform lookup table according to the sine wave data phase value calculated by the phase accumulator on the rising edge of each clock to acquire corresponding sine wave data. The sine wave data is converted into a sine wave analog signal through a DAC circuit.
The pulse shaping module converts the sine wave analog signal into a level signal through a level conversion circuit. The positive amplitude of the sine wave signal is a high level logic 1 of the level signal, and the negative amplitude is a low level logic 0 of the level signal.
The timing diagram of the pulse shaping and logic and operation is shown in fig. 3, where the high level and the low level of the level signal both account for 50% of the whole period, and the time difference of the rising edge of the two level signals is the interchannel delay error τ.
And the logic AND gate module performs logic AND operation on the level signals of the reference channel and one of the channels to be calibrated through the logic gate chip to obtain a path of pulse signals. The timing diagram of the pulse shaping and logical and operation is shown in fig. 3, according to the logical rule of and operation, the high level and low level are anded as low level, the high level and high level are anded as high level, the pulse signal retains the time overlapping part of the two channel high level signals, and the other part is low level.
The pulse width measuring module is used for measuring the pulse width A of the pulse signal, namely the time of high level.
The block diagram of the pulse width measurement module is shown in fig. 4, and the pulse width measurement module includes a precision delay adjustment module, an edge detection module, a counter, a pulse width calculation module, and a measurement control module.
The precision DELAY adjustment module is realized by adopting IO _ DELAY resources of the FPGA, and can achieve DELAY of resolution ratio ps level.
The stepping time interval of the IO _ DELAY resource is delta, the number of stepping nodes is N, and the total DELAY time is delta multiplied by N. The timing diagram of the pulse width measurement module is shown in fig. 5.
The edge detection module samples the pulse signal at the rising edge of each FPGA clock.
The period of the FPGA clock is T _ clk. The high level sampling of the pulse signal is logic 1, the low level sampling is logic 0, and the pulse signal is a sampling rising edge when the logic 0 is changed into the logic 1, otherwise, the pulse signal is a sampling falling edge.
The counter records the number M of FPGA clock cycles between the sample rising edge and the sample falling edge, resulting in a time interval T1 of sample rising and falling edges. The time interval T2 between the actual edges (rising and falling edges) of the pulse signal and the sampling edge is measured by the fine delay adjustment module and the edge detection module in cooperation.
The stepping number of the precise delay adjusting module is increased by 1, and the delay is increased by delta.
The edge detection module detects whether the position of the sampling edge of the pulse signal changes, and repeats the operations until the position of the sampling edge changes, so as to obtain the step pitch number of the precision delay adjustment module, the delay step pitch number N1 of the actual rising edge from the sampling rising edge and the delay step pitch number N2 of the actual falling edge from the sampling falling edge.
The pulse width calculation module calculates the pulse width time A according to T1 and T2, and the calculation expression is as follows:
A＝Δδ×(N1+N2)+T_clk×M (1)
delta is the delay stepping time interval of the precision delay adjusting module, and T _ clk is the period of the FPGA clock.
The measurement control module is used for controlling the components such as the precision delay adjustment module, the edge detection module, the counter and the like.
The synchronous control module calculates to obtain a synchronous delay error tau between channels according to the pulse width time A, and the calculation expression is as follows:
wherein, T _ sig is the period of the output signal.
And the synchronous control module controls the clock delay module and the waveform generation module to calibrate the error according to the synchronous delay error tau.
The clock delay module accurately delays the sampling clock of the DAC through the delay chip, so that the adjustable phase relation occurs between the DAC clocks corresponding to any wave channel, and the delay between the DAC output signals is changed.
The time delay stepping time interval of the clock time delay module is delta rho, the stepping pitch is K, and the total time delay time is delta rho multiplied by K.
The waveform generation module realizes different phases of output signals by adjusting initial phase offset values of waveform data of all channels, so that the time delay among the waveform data is changed. Resolution of waveform generation module phase adjustment
Is composed of
Where L is the number of bits of the phase adder. The calculation expression of the delay step time interval Δ S between waveform data is:
the expression epsilon of the synchronous delay compensation error is as follows:
ε＝|(Δρ×a+ΔS×b)-τ| (4)
wherein, a is the stepping pitch number of the clock delay module, and b is the stepping pitch number of the waveform generation module. And the synchronous control module traverses the values of a and b to ensure that epsilon reaches the minimum value, thereby realizing the minimum synchronous delay error after compensation.
And repeating the operation until the delay errors of all the channels reach the design requirement, and completing the synchronization among the channels.
It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A multi-channel synchronous output calibration device is characterized by comprising a clock module, a clock delay module, a waveform generation module, a pulse shaping module, a logic AND gate module, a pulse width measurement module and a synchronous control module;
wherein, the signal flow in each hardware module is:
sine wave signals output by each channel are input to a pulse shaping module for pulse shaping to obtain square wave signals;
appointing a reference channel, and performing logic AND operation on other channels and the square wave signal of the reference channel in a logic AND gate module in sequence to obtain a pulse signal;
the pulse width measuring module calculates the delay error between the channels by measuring the pulse width of the pulse signal;
the synchronous control module controls the clock delay module and the waveform generation module to sequentially adjust the sampling clock delay and the waveform phase of the channel according to the delay error obtained by measurement, and corrects the delay error;
the clock module is used for providing a clock with the same source for the multi-channel synchronous output calibration device;
the pulse width measuring module comprises a precise delay adjusting module, an edge detecting module, a counter, a pulse width calculating module and a measuring control module;
the edge detection module is matched with the counter to measure and obtain a time interval T1 of a sampling rising edge and a sampling falling edge; the precise time delay adjusting module is matched with the edge detecting module to measure and obtain a time interval T2 between the actual edge of the pulse signal and the sampling edge;
and the measurement control module controls the pulse width calculation module to calculate the pulse width time according to the time interval T1 and the time interval T2.
2. The calibration device for multi-channel synchronous output according to claim 1, wherein the waveform generation module is implemented by FPGA logic by using DDS waveform generation principle;
the waveform generation module addresses a waveform lookup table at the rising edge of each clock according to the sine wave data phase value calculated by the phase accumulator to acquire corresponding sine wave data; the sine wave data is converted into a sine wave analog signal by the DAC.
3. The multi-channel synchronous output calibration device according to claim 2, wherein the clock delay module precisely delays the sampling clock of the DAC through the delay chip, so that an adjustable phase relationship occurs between DAC clocks corresponding to any wave channel, thereby changing the delay between DAC output signals.
4. The calibration device as claimed in claim 1, wherein the pulse shaping module converts the sine wave signal into a level signal through a level conversion circuit.
5. A calibration method of multichannel synchronous output is disclosed, wherein the adopted calibration device comprises a clock module, a clock delay module, a waveform generation module, a pulse shaping module, a logic AND gate module, a pulse width measurement module and a synchronous control module; it is characterized in that the preparation method is characterized in that,
the channel synchronous output calibration method comprises the following steps:
s1. inputting the sine wave signal output by each channel into a pulse shaping module for pulse shaping to obtain square wave signal;
s2, a reference channel is designated, and other channels sequentially carry out logical AND operation with the square wave signals of the reference channel in a logical AND gate module so as to obtain pulse signals;
s3. pulse width measurement module calculates the delay error between channels by measuring the pulse width of pulse signal;
s4. the synchronous control module controls the clock delay module and the waveform generation module to adjust the sampling clock delay and the waveform phase of the channel in turn according to the delay error obtained by measurement, and corrects the delay error;
s5. repeating the above operations of measuring and correcting the delay error;
and when the delay errors of all the channels reach the design requirement, completing the synchronization among the channels.
6. The calibration method for multi-channel synchronous output according to claim 5, wherein in step s3, the step of calculating the delay error by using the pulse width measurement module is as follows:
the pulse width measuring module comprises a precise delay adjusting module, an edge detecting module, a counter, a pulse width calculating module and a measuring control module; the precise DELAY adjustment module is realized by adopting IO _ DELAY resources of the FPGA;
setting the stepping time interval of the IO _ DELAY resource as delta, the stepping number as N and the total DELAY time as delta multiplied by N;
the edge detection module samples the pulse signals at the rising edge of each FPGA clock;
the period of the FPGA clock is T _ clk; the high level sampling of the pulse signal is logic 1, the low level sampling is logic 0, and the high level sampling is the sampling rising edge of the pulse signal when the logic 0 is changed into the logic 1, otherwise, the low level sampling is the sampling falling edge;
the edge detection module is matched with the counter to measure and obtain a time interval T1 of a sampling rising edge and a sampling falling edge; the precise time delay adjusting module is matched with the edge detecting module to measure and obtain a time interval T2 between the actual edge of the pulse signal and the sampling edge;
the stepping number of the precise delay adjusting module is increased by 1, and the delay is increased by delta;
the edge detection module detects whether the position of the sampling edge of the pulse signal changes, and repeats the operation until the position of the sampling edge changes, so as to obtain the step pitch number of the precision delay adjustment module, the delay step pitch number N1 of the actual rising edge from the sampling rising edge and the delay step pitch number N2 of the actual falling edge from the sampling falling edge;
the pulse width calculation module calculates the pulse width time A according to T1 and T2, and the calculation expression is as follows:
A＝Δδ×(N1+N2)+T_clk×M (1)
wherein, Δ δ is the delay stepping time interval of the precision delay adjustment module, and T _ clk is the period of the FPGA clock;
the synchronous control module calculates to obtain a synchronous delay error tau between channels according to the pulse width time A, and the calculation expression is as follows:
wherein, T _ sig is the period of the output signal.
7. The calibration method for multi-channel synchronous output according to claim 6, wherein in the step s4, the specific procedure for correcting the delay error is as follows:
the time delay stepping time interval of the clock time delay module is delta rho, the stepping pitch is K, and the total time delay time is delta rho multiplied by K;
the waveform generation module realizes different phases of output signals by adjusting initial phase deviation values of waveform data of all channels, so that the time delay among the waveform data is changed; resolution of waveform generation module phase adjustment
Is composed of
Wherein, L is the bit number of the phase adder, and the calculation expression of the delay stepping time interval Δ S between waveform data is:
the expression epsilon of the synchronous delay compensation error is as follows:
ε＝|(Δρ×a+ΔS×b)-τ| (4)
wherein, a is the stepping pitch number of the clock delay module, and b is the stepping pitch number of the waveform generation module; and the synchronous control module traverses the values of a and b to ensure that epsilon reaches the minimum value, thereby realizing the minimum synchronous delay error after compensation.
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