CN117054715A - Sampling synchronization method for multiple digital oscilloscopes - Google Patents
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R13/00—Arrangements for displaying electric variables or waveforms
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses a sampling synchronization method of a plurality of digital oscilloscopes, which mainly comprises two steps of clock synchronization and trigger synchronization; in the clock synchronization part, a master device crystal oscillator provides a source clock and outputs a synchronous clock signal to a slave device, and the slave device obtains the transmission delay time of the synchronous clock signal through an internal counter and performs phase compensation to realize sampling clock synchronization; in a trigger synchronization part, the master device and the slave device set the same trigger depth, the slave device establishes a trigger system through a FIFO read-write enabling signal and an intermediate control signal FIFO_MID generated by the master device to realize the read-write operation of trigger data, then the FPGA performs delay processing on the extracted acquisition data to compensate the deterministic delay of edge detection and the uncertain delay of a transmission path, and finally performs time sequence adjustment on the slave trigger signal FIFO_MID to complete trigger synchronization; and when the digital oscilloscopes connected in series sequentially complete sampling clock synchronization and trigger synchronization, finally realizing sampling synchronization of a plurality of digital oscilloscopes.
Description
Technical Field
The invention belongs to the technical field of digital oscilloscopes, and particularly relates to a sampling synchronization method of a plurality of digital oscilloscopes.
Background
The digital oscilloscope (Digital Storage oscilloscope, DSO) is a high-speed and high-precision measuring instrument, is widely applied to various complicated electronic measurement fields, has the capability of storing waveform data and processing the data compared with an analog oscilloscope, and has a richer triggering mode and stronger capturing capability on complex waveforms. With the progress of electronic technology, the volume phase difference of electronic equipment is larger and larger, and the testing environment is also more and more complex. Therefore, in order to improve the adaptability of the test instrument to different test environments, the demand for portable and miniaturized digital oscilloscopes is increasing. In order to reduce the volume and weight of the device, the small digital oscilloscope is often designed with a small number of channels, and is not suitable for a test scene requiring simultaneous measurement of a plurality of signals. Therefore, in order to improve the testing capability of the small digital oscilloscope, a method capable of synchronizing a plurality of digital oscilloscopes to realize synchronous and precise sampling must be designed.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a sampling synchronization method for a plurality of digital oscilloscopes, which realizes the acquisition synchronization, the storage synchronization and the display synchronization of multi-equipment data through clock synchronization and trigger synchronization, thereby achieving the high-precision index of multi-equipment synchronization trigger.
In order to achieve the above purpose, the invention provides a sampling synchronization method for a plurality of digital oscilloscopes, which is characterized by comprising the following steps:
(1) The system is provided with M digital oscilloscopes which need to be sampled synchronously, and each digital oscilloscopes are connected in series in sequence;
(2) Synchronizing sampling clocks of the master device and the slave device;
(2.1) taking a first digital oscilloscope as a master device and a second digital oscilloscope as a slave device to perform a digital oscilloscope acquisition process;
(2.1.1), the internal crystal oscillator of the main equipment provides a 10MHz clock source for the clock chip, and simultaneously outputs a 10MHz synchronous clock signal independently;
(2.1.2) the internal circuit designs of the master equipment and the slave equipment are the same, clock interfaces A and B with bidirectional input and output functions are designed, 10MHz synchronous clock signals are transmitted to the clock interface B through an FPGA clock programming control circuit in the master equipment, and the interfaces are connected with the slave equipment clock interface A through a coaxial line;
(2.1.3) transmitting the 10MHz synchronous clock signal to a clock circuit of the slave device through an FPGA clock programming control circuit in the slave device, wherein the circuit continuously adjusts the phase of a slave device crystal oscillator to be equal to the phase of the 10MHz synchronous clock signal, and the adjusted crystal oscillator provides a 10MHz clock source for a clock chip of the slave device;
(2.1.4) the master-slave device generates sampling clocks of the ADC through the same clock chip by using respective clock sources, starts data acquisition, and transmits analog signals to an internal FIFO memory of the FPGA through the ADC in the same path;
(2.2) performing an estimation process to calculate a transmission delay time DeltaT of the synchronous clock signal transmitted from the master crystal oscillator to the slave crystal oscillator clk ；
(2.2.1) a starting signal generator generates a 10MHz test signal, the 10MHz test signal is respectively connected to a clock interface A of a master device and a clock interface B of a slave device by coaxial connecting wires with equal lengths, and enters an FPGA in each device, and the transmission time is recorded as T1 and T2, and T1=T2;
(2.2.2), the test signal in the main equipment is transmitted to a clock circuit through an FPGA clock programming control module, the clock circuit continuously adjusts the phase of the crystal oscillator of the main equipment to be equal to the phase of the test signal, and the transmission time is recorded as Tclk; the adjusted crystal oscillator is transmitted to a clock interface A of the slave equipment according to a (2.1.2) transmission path, and finally transmitted to the interior of the slave equipment FPGA, and the transmission time is recorded as Tnet;
(2.2.3), starting an FPGA internal counter by the slave equipment, enabling a path from a test signal to the counter to be identical with a transmission path of a clock signal in an FPGA clock programming control circuit by using an FPGA internal wiring tool, starting counting by the counter after detecting the test signal output by the signal generator, ending counting after detecting a synchronous clock signal, wherein the counting time is as follows: t=t1+tclk+tnet-t2=tclk+tnet;
(2.2.4), from the synchronous clock signal transmission paths in (2.1.2) and (2.1.3) and the FPGA internal wiring layout in (2.2.3): transmission delay deltat for synchronizing clock signal transmission from master device crystal to slave device crystal clk =tclk+tnet, i.e. Δt clk ＝T；
(2.3), master-slave sampling clock skew correction;
let DeltaT be clk_min For the phase difference between the master sampling clock and the slave sampling clock, which is the phase difference between the latest rising edges, T is the sampling clock period, and N is delta T clk The maximum complete sampling clock cycle number is contained according to DeltaT clk ＝ΔT clk min +NT delays the ADC sampling clock phase difference of the slave device until the sampling clock phase of the master device is consistent, and the sampling clock of the master device and the slave device is synchronously completed;
(3) Triggering synchronization of the master device and the slave device;
(3.1) setting a trigger source of the master device as a self-simulation channel mode, setting a trigger source of the slave device as an external trigger channel mode, and setting the same trigger depth by the master device and the slave device;
(3.2) setting a trigger condition of the main equipment, and generating a FIFO read-write enabling signal for controlling data storage and reading by the FPGA of the main equipment according to the trigger condition;
(3.2.1), the master device jointly generates an intermediate control signal fifo_mid according to the FIFO read-write enabling signal, and the specific generation process is as follows: pulling up the fifo_mid after detecting the rising edge of the FIFO write enable signal, and pulling down the fifo_mid after detecting the falling edge of the FIFO read enable signal, remaining unchanged at other times;
(3.2.2), the FIFO_MID enters the slave device through the connection cable of the master device and the slave device, and the FPGA of the slave device generates a FIFO read-write enabling signal for controlling the data storage and reading of the slave device according to the FIFO_MID; when the FPGA of the slave device detects the rising edge of the FIFO_MID, the FIFO write enable signal of the slave device is pulled up, at the moment, the acquired data starts to be written into the FIFO of the slave device until the length of the written data is equal to the pre-trigger depth, and then the FIFO read enable signal of the slave device is pulled up, at the moment, the FIFO simultaneously performs the writing and reading operation of the acquired data;
when the FPGA of the slave device detects the falling edge of the FIFO_MID, the FIFO read enable signal of the slave device is pulled down, the FIFO stops reading data, collected data starts to be written into the post-trigger storage area until the post-trigger storage area is full of data, then the slave device is controlled to write enable down and read enable up, the fully written collected data is taken out for subsequent processing, and the slave device triggering process is completed;
(3.3), trigger point offset correction;
the FPGA of the slave device carries out delay processing on the acquired data, compensates for the delay of the edge detection and the transmission path, and adjusts the delay value through the upper computer until the trigger point position returns to the ideal trigger position;
(3.4) performing timing adjustment on the slave trigger signal FIFO_MID to enable the slave trigger signal FIFO_MID to be far away from a metastable state interval of a slave processing clock;
the optimal delay value is determined as follows: and delaying the trigger signal of the slave to be just far from the metastable state interval, taking the data transmission from non-alignment to alignment as a starting point delay0, then increasing the delay value until the data is just from alignment to non-alignment as an end point delay1, then taking the optimal delay value as (delay 0+delay 1)/2, and then calling an internal IDELAYE2 resource by the FPGA to independently adjust and delay the trigger signal of the slave, thereby completing the trigger synchronization of master and slave equipment.
(4) After the synchronization of the first digital oscilloscope and the second digital oscilloscope is finished, setting the second digital oscilloscope as a master device, setting the third digital oscilloscope as a slave device, finishing the synchronization according to the steps (2) and (3), and then finishing the synchronization of all the digital oscilloscopes by analogy;
(5) And after all the digital oscilloscopes are synchronously finished, one digital oscilloscopes is arbitrarily selected as a master device, and the rest digital oscilloscopes are slave devices, so that a multi-channel data acquisition system is formed.
The invention aims at realizing the following steps:
the invention relates to a sampling synchronization method of a plurality of digital oscilloscopes, which mainly comprises two steps of clock synchronization and trigger synchronization; in the clock synchronization part, a master device crystal oscillator provides a source clock and outputs a synchronous clock signal to a slave device, and the slave device obtains the transmission delay time of the synchronous clock signal through an internal counter and performs phase compensation to realize sampling clock synchronization; in a trigger synchronization part, the master device and the slave device set the same trigger depth, the slave device establishes a trigger system through the FIFO read-write enabling signal and the intermediate control signal FIFO_MID generated by the master device, the read-write operation of trigger data is realized, then the FPGA performs delay processing on the extracted acquisition data, the deterministic delay of edge detection and the uncertain delay of a transmission path are compensated, and finally the timing adjustment is performed on the slave trigger signal FIFO_MID to complete trigger synchronization. And the digital oscilloscopes connected in series sequentially complete sampling clock synchronization and trigger synchronization, and finally realize sampling synchronization of a plurality of digital oscilloscopes.
Meanwhile, the sampling synchronization method of the plurality of digital oscilloscopes has the following beneficial effects:
(1) The method can accurately realize clock synchronization and trigger synchronization of master-slave equipment by calculating and compensating the transmission delay time, ensures consistency of a plurality of digital oscilloscopes at sampling and trigger moments, and improves synchronization precision compared with the traditional multi-machine synchronization method; the higher synchronization precision can eliminate sampling errors caused by inconsistent clocks and triggers, and more accurate and reliable data can be provided;
(2) The method supports the serial connection of a plurality of digital oscilloscopes, and can combine the plurality of oscilloscopes according to actual scene requirements so as to achieve the aim of widening the number of channels; the application range of the digital oscilloscope in a high-speed multi-signal test scene can be expanded, the problem that the number of channels of the digital oscilloscope is relatively small is solved, the signal acquisition and analysis in a larger range are realized, and the complex experiment or test requirement is met;
(3) The multi-machine synchronous function is an important basis for subsequent multi-machine data split development, multi-machine sampling data can be split at intervals, and the highest sampling rate of the digital oscilloscope is improved by adopting a TIADC-like scheme, so that the acquisition performance of the digital oscilloscope is further improved.
Drawings
FIG. 1 is a flow chart of a method for synchronizing samples of a plurality of digital oscilloscopes;
FIG. 2 is a schematic diagram of a plurality of digital oscilloscope connections;
FIG. 3 is a block diagram of a clock circuit of a slave device;
fig. 4 is a diagram showing the delay of the clock signal transmission path.
Detailed Description
The following description of the embodiments of the invention is presented in conjunction with the accompanying drawings to provide a better understanding of the invention to those skilled in the art. It is to be expressly noted that in the description below, detailed descriptions of known functions and designs are omitted here as perhaps obscuring the present invention.
Examples
FIG. 1 is a flow chart of a method for synchronizing samples of a plurality of digital oscilloscopes.
In this embodiment, as shown in fig. 1, the sampling synchronization method of multiple digital oscilloscopes of the present invention includes the following steps:
s1, sampling synchronization is needed for M digital oscilloscopes in a system, and each digital oscilloscope is connected in series in sequence, wherein the connection mode is shown in figure 2;
s2, synchronizing sampling clocks of the master device and the slave device;
s2.1, taking a first digital oscilloscope as a master device and a second digital oscilloscope as a slave device, and carrying out a digital oscilloscope acquisition process;
s2.1.1, the internal crystal oscillator of the main equipment provides a 10MHz clock source for the clock chip, and simultaneously outputs a 10MHz synchronous clock signal independently;
s2.1.2, the internal circuit designs of the master device and the slave device are the same, clock interfaces A and B with two-way input and output functions are designed, a clock circuit design structure diagram and a clock signal transmission path in an acquisition mode are shown in fig. 3, 10MHz synchronous clock signals are transmitted to the clock interface B through an FPGA clock programming control circuit in the master device, and the interfaces are connected with the slave device clock interface A through coaxial lines;
s2.1.3 and 10MHz synchronous clock signals are transmitted to a clock circuit of the slave device through an FPGA clock programming control circuit in the slave device, the circuit consists of a voltage optimizing circuit, a phase-locked controller and a voltage-controlled oscillator VCO, the phase of a crystal oscillator of the slave device is continuously regulated by the phase-locked loop formed by the structure, the phase of the crystal oscillator is equal to that of the synchronous clock signals, and the regulated crystal oscillator provides a 10MHz clock source for a clock chip of the slave device;
s2.1.4, the master-slave equipment generates sampling clocks of the ADC through the same clock chip by using respective clock sources, starts data acquisition, and transmits analog signals to an internal FIFO memory of the FPGA through the ADC in the same path;
s2.2, performing an estimation process, and calculating a transmission delay time delta T of a synchronous clock signal transmitted from the master device crystal oscillator to the slave device crystal oscillator clk ；
S2.2.1, a starting signal generator generates a 10MHz test signal, the 10MHz test signal is respectively connected to a clock interface A of a master device and a clock interface B of a slave device by coaxial connecting wires with equal length, and enters an FPGA in each device, the transmission time is recorded as T1 and T2, T1=T2, and the signal transmission path delay is shown in figure 4;
s2.2.2, the test signal in the main equipment is transmitted to a clock circuit through an FPGA clock programming control module, the clock circuit continuously adjusts the phase of the crystal oscillator of the main equipment to be equal to the phase of the test signal, and the transmission time is recorded as Tclk; the adjusted crystal oscillator is transmitted to a clock interface A of the slave equipment according to a S2.1.2 transmission path, and finally transmitted to the interior of the FPGA of the slave equipment, and the transmission time is recorded as Tnet;
s2.2.3 starting an FPGA internal counter by the slave device, enabling the path from the test signal to the counter to be the same as the transmission path of the clock signal in the FPGA clock programming control circuit by using an FPGA internal wiring tool, starting counting by the counter after detecting the output test signal of the signal generator, and ending counting after detecting the synchronous clock signal, wherein the counting time is as follows: t=t1+tclk+tnet-t2=tclk+tnet;
s2.2.4, from the synchronous clock signal transmission paths in S2.1.2 and S2.1.3, and the internal wiring layout of S2.2.3FPGA: transmission delay deltat for synchronizing clock signal transmission from master device crystal to slave device crystal clk =tclk+tnet, i.e. Δt clk ＝T；
S2.3, correcting skew of master-slave sampling clocks;
the sampling clock phase adjustment may be adjusted within the clock chip HMC7044 or ADC. HMC7044 provides an analog regulation scheme for the output clock, with a step of 25ps, up to 600ps. The design uses ADC to adjust the time delay to be coarse-tuned by 1.13ps, the highest adjustable by 289ps, the fine-tuned by 19fs and the highest adjustable by 4.9ps, and comprehensively considers the selection of an ADC internal adjusting scheme with higher adjusting precision;
let DeltaT be clk_min For the phase difference between the master sampling clock and the slave sampling clock, which is the phase difference between the latest rising edges, T is the sampling clock period, and N is delta T clk The maximum complete sampling clock cycle number is contained according to DeltaT clk ＝ΔT clk_min +NT delays the ADC sampling clock phase difference of the slave device until the sampling clock phase of the master device is consistent, and the sampling clock of the master device and the slave device is synchronously completed;
s3, triggering synchronization of the master device and the slave device;
s3.1, setting a trigger source of a master device as a self-simulation channel mode, setting a trigger source of a slave device as an external trigger channel mode, and setting the same trigger depth by the master device and the slave device;
s3.2, setting a trigger condition of the main equipment, and generating a FIFO read-write enabling signal for controlling data storage and reading by the FPGA of the main equipment according to the trigger condition;
s3.2.1, the master device jointly generates an intermediate control signal fifo_mid according to the FIFO read-write enabling signal, and the specific generation process is as follows: pulling up the fifo_mid after detecting the rising edge of the FIFO write enable signal, and pulling down the fifo_mid after detecting the falling edge of the FIFO read enable signal, remaining unchanged at other times;
s3.2.2, the FIFO_MID enters the slave device through a connection line of the master device and the slave device, and the FPGA of the slave device generates a FIFO read-write enabling signal for controlling the data storage and reading of the slave device according to the FIFO_MID; when the FPGA of the slave device detects the rising edge of the FIFO_MID, the FIFO write enable signal of the slave device is pulled up, at the moment, the acquired data starts to be written into the FIFO of the slave device until the length of the written data is equal to the pre-trigger depth, and then the FIFO read enable signal of the slave device is pulled up, at the moment, the FIFO simultaneously performs the writing and reading operation of the acquired data;
when the FPGA of the slave device detects the falling edge of the FIFO_MID, the FIFO read enable signal of the slave device is pulled down, the FIFO stops reading data, collected data starts to be written into the post-trigger storage area until the post-trigger storage area is full of data, then the slave device is controlled to write enable down and read enable up, the fully written collected data is taken out for subsequent processing, and the slave device triggering process is completed;
s3.3, triggering point offset correction;
the slave control signal has a certain delay compared to the master control signal, including a certain beat delay due to edge detection and an uncertainty delay due to the transmission path. Because the clock circuit synchronization is designed before the triggering process, the sampling points of the master and slave devices are synchronized, the delay of the trigger signal of the slave device means that the trigger point can enter the FIFO earlier than the trigger signal, which leads to the deviation of the trigger point of the master and slave devices and the situation that the trigger point of the slave device is deviated from the normal situation, so that the delays must be corrected to promote the synchronization of the trigger points of the master and slave devices and the occurrence of the trigger points at the ideal trigger position;
the beat delay is fixed and known, the beat clock is 320MHz, the delay brought by each beat is 1/320 MHz=3.125 ns, and the beat number is two beats of one edge detected by the host and one edge detected by the slave, so that the data collected by the slave is only required to be subjected to two beat operations; the uncertain delay brought by the transmission path adopts IDELAYE2 statement integrated in the FPGA to realize delay adjustment of the acquired data, and corresponding port configuration values are modified in the upper computer software to dynamically adjust the delay value until the trigger point position returns to an ideal trigger position;
s3.4, performing time sequence adjustment on the slave trigger signal FIFO_MID to enable the slave trigger signal FIFO_MID to be far away from a metastable state interval of a slave processing clock;
when the total delay of the slave trigger signal transmission is similar to the processing clock period, the setup and hold time requirement of the slave processing clock may not be met, thereby causing metastability. Once the metastable state is generated, the signal may take effect after one or more periods, which may cause timing disorder of the trigger signal in the acquisition mode, and the FIFO performs error read-write control, which indicates that the trigger point is different every time the power is turned on. In order to make the transmission signal far away from the metastable state interval of the slave processing clock, proper time sequence delay is needed to be carried out on the transmission signal;
the optimal delay value is determined as follows: and delaying the FIFO_MID signal to be just far from the metastable state interval, taking the data transmission from non-alignment to alignment as a starting point delay0, then increasing the delay value to the point that the data is just from alignment to non-alignment as an end point delay1, setting the optimal delay value as (delay 0+delay 1)/2, and then calling an internal IDELAYE2 resource by the FPGA to independently adjust and delay a slave trigger signal, thereby completing the trigger synchronization of master and slave devices.
S4, after the synchronization of the first digital oscilloscope and the second digital oscilloscope is completed, setting the second digital oscilloscope as a master device, setting the third digital oscilloscope as a slave device, completing the synchronization according to the steps (2) and (3), and then completing the synchronization of all the digital oscilloscopes by analogy;
and S5, after all the digital oscilloscopes are synchronously finished, selecting one digital oscilloscopes as a master device, and the rest digital oscilloscopes are slave devices, so that a multi-channel data acquisition system is formed.
While the foregoing describes illustrative embodiments of the present invention to facilitate an understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, but is to be construed as protected by the accompanying claims insofar as various changes are within the spirit and scope of the present invention as defined and defined by the appended claims.
Claims (1)
1. The sampling synchronization method of the plurality of digital oscilloscopes is characterized by comprising the following steps of:
(1) The system is provided with M digital oscilloscopes which need to be sampled synchronously, and each digital oscilloscopes are connected in series in sequence;
(2) Synchronizing sampling clocks of the master device and the slave device;
(2.1) taking a first digital oscilloscope as a master device and a second digital oscilloscope as a slave device to perform a digital oscilloscope acquisition process;
(2.1.1), the internal crystal oscillator of the main equipment provides a 10MHz clock source for the clock chip, and simultaneously outputs a 10MHz synchronous clock signal independently;
(2.1.2) the internal circuit designs of the master equipment and the slave equipment are the same, clock interfaces A and B with bidirectional input and output functions are designed, 10MHz synchronous clock signals are transmitted to the clock interface B through an FPGA clock programming control circuit in the master equipment, and the interfaces are connected with the slave equipment clock interface A through a coaxial line;
(2.1.3) transmitting the 10MHz synchronous clock signal to a clock circuit of the slave device through an FPGA clock programming control circuit in the slave device, wherein the circuit continuously adjusts the phase of a slave device crystal oscillator to be equal to the phase of the 10MHz synchronous clock signal, and the adjusted crystal oscillator provides a 10MHz clock source for a clock chip of the slave device;
(2.1.4) the master-slave device generates sampling clocks of the ADC through the same clock chip by using respective clock sources, starts data acquisition, and transmits analog signals to an internal FIFO memory of the FPGA through the ADC in the same path;
(2.2) performing an estimation process to calculate a transmission delay time DeltaT of the synchronous clock signal transmitted from the master crystal oscillator to the slave crystal oscillator clk ；
(2.2.1) a starting signal generator generates a 10MHz test signal, the 10MHz test signal is respectively connected to a clock interface A of a master device and a clock interface B of a slave device by coaxial connecting wires with equal lengths, and enters an FPGA in each device, and the transmission time is recorded as T1 and T2, and T1=T2;
(2.2.2), the test signal in the main equipment is transmitted to a clock circuit through an FPGA clock programming control module, the clock circuit continuously adjusts the phase of the crystal oscillator of the main equipment to be equal to the phase of the test signal, and the transmission time is recorded as Tclk; the adjusted crystal oscillator is transmitted to a clock interface A of the slave equipment according to a (2.1.2) transmission path, and finally transmitted to the interior of the slave equipment FPGA, and the transmission time is recorded as Tnet;
(2.2.3), starting an FPGA internal counter by the slave equipment, enabling a path from a test signal to the counter to be identical with a transmission path of a clock signal in an FPGA clock programming control circuit by using an FPGA internal wiring tool, starting counting by the counter after detecting the test signal output by the signal generator, ending counting after detecting a synchronous clock signal, wherein the counting time is as follows: t=t1+tclk+tnet-t2=tclk+tnet;
(2.2.4), from the synchronous clock signal transmission paths in (2.1.2) and (2.1.3) and the FPGA internal wiring layout in (2.2.3): transmission delay deltat for synchronizing clock signal transmission from master device crystal to slave device crystal clk =tclk+tnet, i.e. Δt clk ＝T；
(2.3), master-slave sampling clock skew correction;
let DeltaT be clk_min For the phase difference between the master sampling clock and the slave sampling clock, which is the phase difference between the latest rising edges, T is the sampling clock period, and N is delta T clk The maximum complete sampling clock cycle number is contained according to DeltaT clk ＝ΔT clk_min +NT delays the ADC sampling clock phase difference of the slave device until the sampling clock phase of the master device is consistent, and the sampling clock of the master device and the slave device is synchronously completed;
(3) Triggering synchronization of the master device and the slave device;
(3.1) setting a trigger source of the master device as a self-simulation channel mode, setting a trigger source of the slave device as an external trigger channel mode, and setting the same trigger depth by the master device and the slave device;
(3.2) setting a trigger condition of the main equipment, and generating a FIFO read-write enabling signal for controlling data storage and reading by the FPGA of the main equipment according to the trigger condition;
(3.2.1), the master device jointly generates an intermediate control signal fifo_mid according to the FIFO read-write enabling signal, and the specific generation process is as follows: pulling up the fifo_mid after detecting the rising edge of the FIFO write enable signal, and pulling down the fifo_mid after detecting the falling edge of the FIFO read enable signal, remaining unchanged at other times;
(3.2.2), the FIFO_MID enters the slave device through the connection cable of the master device and the slave device, and the FPGA of the slave device generates a FIFO read-write enabling signal for controlling the data storage and reading of the slave device according to the FIFO_MID; when the FPGA of the slave device detects the rising edge of the FIFO_MID, the FIFO write enable signal of the slave device is pulled up, at the moment, the acquired data starts to be written into the FIFO of the slave device until the length of the written data is equal to the pre-trigger depth, and then the FIFO read enable signal of the slave device is pulled up, at the moment, the FIFO simultaneously performs the writing and reading operation of the acquired data;
when the FPGA of the slave device detects the falling edge of the FIFO_MID, the FIFO read enable signal of the slave device is pulled down, the FIFO stops reading data, collected data starts to be written into the post-trigger storage area until the post-trigger storage area is full of data, then the slave device is controlled to write enable down and read enable up, the fully written collected data is taken out for subsequent processing, and the slave device triggering process is completed;
(3.3), trigger point offset correction;
the FPGA of the slave device carries out delay processing on the acquired data, compensates for the delay of the edge detection and the transmission path, and adjusts the delay value through the upper computer until the trigger point position returns to the ideal trigger position;
(3.4) performing timing adjustment on the slave trigger signal FIFO_MID to enable the slave trigger signal FIFO_MID to be far away from a metastable state interval of a slave processing clock;
the optimal delay value is determined as follows: delaying the FIFO_MID signal to be just far from the metastable state interval, taking the data transmission from non-alignment to alignment as a starting point delay0, then increasing the delay value to the point that the data is just from alignment to non-alignment as an end point delay1, then taking the optimal delay value as (delay 0+delay 1)/2, and then the FPGA calls an internal IDELAYE2 resource to independently adjust and delay the slave trigger signal, so as to finish the trigger synchronization of master-slave equipment;
(4) After the synchronization of the first digital oscilloscope and the second digital oscilloscope is finished, setting the second digital oscilloscope as a master device, setting the third digital oscilloscope as a slave device, finishing the synchronization according to the steps (2) and (3), and then finishing the synchronization of all the digital oscilloscopes by analogy;
(5) And after all the digital oscilloscopes are synchronously finished, one digital oscilloscopes is arbitrarily selected as a master device, and the rest digital oscilloscopes are slave devices, so that a multi-channel data acquisition system is formed.
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