CN110971238B - External synchronization device for continuous equal-gap sampling of sigma-delta type AD - Google Patents
External synchronization device for continuous equal-gap sampling of sigma-delta type AD Download PDFInfo
- Publication number
- CN110971238B CN110971238B CN201911293360.4A CN201911293360A CN110971238B CN 110971238 B CN110971238 B CN 110971238B CN 201911293360 A CN201911293360 A CN 201911293360A CN 110971238 B CN110971238 B CN 110971238B
- Authority
- CN
- China
- Prior art keywords
- signal
- sampling
- clock
- clk
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
Abstract
The invention discloses an external synchronization device for continuous equal-interval sampling of sigma-delta type AD, which adopts an external synchronization intermittent sampling clock as a working clock of the sigma-delta type AD, the number of clock pulses between two times of synchronization signals is strictly consistent and is equal to the number of clock pulses required by one-time sampling, thus after the sigma-delta type AD is reset once by using a starting signal, each time of subsequent sampling can be synchronized with the synchronization signals without resetting a digital filter, and compared with a traditional device, the external synchronization device greatly reduces sampling noise and improves sampling precision compared with the traditional device by using data which can be used by the digital filter within equal sampling time and a continuous sampling non-resetting digital filter.
Description
Technical Field
The invention belongs to the technical field of clock synchronous sampling systems, and particularly relates to a sigma-delta type external synchronization device for continuous equal-interval sampling of AD.
Background
Currently, a sigma-delta type AD sampling system needs to design a synchronization system for synchronizing sampling time points of sampling channels, so as to reduce sampling aperture errors caused by sampling time point errors among multiple channels. The design of the synchronous system directly affects the sampling accuracy and time-efficiency of the sigma-delta type AD.
A traditional sigma-delta type AD external synchronization equal-gap sampling synchronization system is shown in fig. 1, wherein an external continuous clock is directly used as a clock, and a Y _ SYSN signal and a START signal and logic are used to form an external synchronization sampling system;
in the traditional sigma-delta type AD sampling, a continuous clock is used as a working clock of the sigma-delta type AD, and a synchronous signal is used for synchronous sampling start. Since the operating clock is not synchronized with the clock of the synchronization signal, for the sigma-delta type AD, the digital filter must be reset every time the synchronization is performed, which means that a complete digital filter setup time is required to perform normal sampling once, and compared with a digital filter that is not reset by continuous sampling, the data that can be utilized by the digital filter in the sampling time is only 2% of the latter, and the noise is increased by more than 4 times.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide an external synchronization device for continuous equal-interval sampling of sigma-delta type AD, wherein under the triggering of an external synchronization signal, the AD adopts a synchronous intermittent sampling clock to realize an external synchronization continuous sampling and a digital external synchronization system of the sampling clock.
To achieve the above object, an external synchronization apparatus for continuous equal interval sampling of sigma-delta AD according to the present invention includes: the clock pre-disciplining module, the intermittent synchronous clock generator, the synchronous triggering module and the AD sampling module;
the clock pre-disciplining module comprises a frequency discriminator, a feedback filter, a Voltage Controlled Oscillator (VCO) and a frequency divider; after the external synchronous clock signal Y-SYSN with equal gaps is input into the clock pre-tame module, the frequency discriminator counts the number of pulses of the sampling clock signal XF-CLK output by the frequency divider within a complete period T of the Y-SYSN, and the number is marked as f x (ii) a Then counting the number of pulses required by the AD sampling module to complete one-time complete sampling, and recording as f c (ii) a The number of pulses f x And the number of pulses f c When f is compared to the sum of the reserved values Δ x Is stabilized at f c ～(f c + delta), at this time, the loop is determined to be locked, the input signal is disciplined and completed, and therefore the disciplined clock signal XF-CLK is directly output; otherwise, the result of the comparison, namely the frequency error, is converted into a voltage signal and then input to a feedback filter, a stable direct-current voltage signal is formed after high-frequency components are filtered out, and the voltage signal is used as the control voltage of the voltage-controlled oscillator and is used for controlling the voltage-controlled oscillator to output a frequency division signal to the frequency divider, the frequency divider realizes frequency division output according to the frequency division signal, and the specific output process is as follows: if f is x >f c + delta, performing frequency division output on the XF-CLK through the frequency divider, reducing the clock frequency of the XF-CLK, and then outputting the XF-CLK; if f is x ＜f c Then, the frequency divider is used for carrying out frequency division output on the XF-CLK, the clock frequency of the XF-CLK is improved, and then the XF-CLK is output; after repeated discipline, the frequency of XF-CLK is stabilized at (T/f) c +Δ)～(T/f c ) In the middle of;
the intermittent synchronous clock generator comprises a counter and a selector; firstly, the number f of pulses c Inputting the value as a set value to a counter to complete the setting of the counter; when Y-SYSN is input to the counter, the counter is initialized to 0 and then turned onStarting counting; when XF-CLK is detected once, the counter value of the counter is increased by 1, the high level of the selector is enabled, and XJ-CLK is output, and when the counter value of the counter is increased to f c While the counter remains unchanged, the low level of the enable selector is asserted and the low level is output, thereby outputting f c A gap sampling clock XJ-CLK of each sampling pulse is transmitted to the AD sampling module; when the next Y-SYSN arrives, the counter restarts counting, and the process is repeated,
the synchronous trigger module comprises an AND gate and a trigger module; firstly, providing a starting signal for a synchronous trigger module through external equipment; Y-SYSN and a starting signal are simultaneously input into an AND gate, in the AND gate, when the Y-SYSN and the starting signal are simultaneously effective in high level, the Y-SYSN and the starting signal are input into a trigger module, when the trigger module detects that the rising edge of the starting signal arrives, the trigger module starts to receive and output the Y-SYSN to an AD sampling module, and after the rising edge, the trigger module is locked and does not output a synchronous signal SYSN; when the trigger module detects that the falling edge of the starting signal comes, the trigger module resets;
and the AD sampling module samples the synchronous signal SYSN when the XJ-CLK arrives to obtain sampling data.
The invention aims to realize the following steps:
the invention relates to an external synchronization device for continuous equal-interval sampling of sigma-delta type AD, which adopts an external synchronization intermittent sampling clock as a working clock of the sigma-delta type AD, the number of clock pulses between two times of synchronous signals is strictly consistent and is equal to the number of clock pulses required by one-time sampling, thus after the sigma-delta type AD is reset once by using a starting signal, each time of subsequent sampling can be synchronized with the synchronous signals without resetting a digital filter, and compared with the conventional device, the external synchronization device for continuous equal-interval sampling of sigma-delta type AD greatly reduces sampling noise and improves sampling precision.
Drawings
FIG. 1 is a diagram of a conventional sigma-delta type AD external synchronization equal interval sampling synchronization system;
FIG. 2 is a schematic diagram of an embodiment of a sigma-delta type AD external synchronizer with continuous equal-interval sampling according to the present invention;
FIG. 3 is a schematic diagram of a clock pre-discipline module;
FIG. 4 is a schematic diagram of a generator of intermittently synchronized clocks;
FIG. 5 is an intermittent sampling clock timing diagram;
FIG. 6 is a schematic diagram of a synchronization trigger module;
FIG. 7 is a timing diagram of a synchronization trigger;
fig. 8 is a timing diagram of the enable signal.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
Examples
Fig. 2 is an architecture diagram of an embodiment of an external synchronization apparatus for continuous equal-interval sampling of sigma-delta type AD according to the present invention.
In this embodiment, as shown in fig. 2, the external synchronization apparatus for continuous equal interval sampling of sigma-delta AD of the present invention includes: the clock pre-disciplining module, the intermittent synchronous clock generator, the synchronous triggering module and the AD sampling module.
As shown in fig. 3, the clock pre-discipline module includes a frequency discriminator, a feedback filter, a voltage controlled oscillator VCO, and a frequency divider; after the external synchronous clock signal Y-SYSN with equal gaps is input to the clock pre-disciplined module, the frequency discriminator counts the number of pulses of the sampling clock signal XF-CLK output by the frequency divider within a complete period T of the Y-SYSN, and the number is marked as f x (ii) a Then counting the number of pulses required by the AD sampling module to complete one-time complete sampling, and recording as f c (ii) a The number of pulses f x And the number of pulses f c When compared to the sum of the reserved values Δ when f x Is stabilized at f c ～(f c + delta), when the loop is deemed to be locked and the input signal has been tamed, the tamed clock signal is directly outputNumber XF-CLK; otherwise, the result of the comparison, namely the frequency error, is converted into a voltage signal and then input to a feedback filter, a stable direct-current voltage signal is formed after high-frequency components are filtered out, and the voltage signal is used as the control voltage of the voltage-controlled oscillator and is used for controlling the voltage-controlled oscillator to output a frequency division signal to the frequency divider, the frequency divider realizes frequency division output according to the frequency division signal, and the specific output process is as follows: if f is x >f c + delta, performing frequency division output on the XF-CLK through the frequency divider, reducing the clock frequency of the XF-CLK, and then outputting the XF-CLK; if f is x ＜f c Then, the frequency divider is used for carrying out frequency division output on the XF-CLK, the clock frequency of the XF-CLK is improved, and then the XF-CLK is output; after repeated discipline, the frequency of XF-CLK is stabilized at (T/f) c +Δ)～(T/f c ) In between.
The AD sampling clock is pre-disciplined by using the external synchronizing signal, so that the pre-disciplined clock is ensured to be slightly larger than the clock frequency of the pulse required by AD once sampling, and the precision problem caused by instability of the input clock due to overlong pause time can be prevented.
As shown in fig. 4, the intermittent synchronous clock generator includes a counter and a selector; after the sampling working clock is pre-disciplined, the pre-disciplined clock is slightly larger than the clock frequency of the pulse required by AD once sampling. The clock is unstable, has a certain time jitter, and cannot be directly synchronized with the external synchronization clock signal Y-SYSN. To achieve sampling synchronized with the Y-SYSN signal, an intermittent sampling clock may be employed. I.e. the number f of samples required to output an AD sample between two synchronization signals c Sampling clock pulse, the sampling clock keeps the low level unchanged until the next Y-SYSN arrival, and f is output again c A sampling clock pulse. Therefore, each sampling is strictly synchronous with Y-SYSN, AD works in a continuous mode, and data which can be utilized by the digital filter in equal sampling time is theoretically consistent with data which can not be reset by continuous sampling, so that the sampling precision is improved. The specific working principle is as follows:
firstly, the number f of pulses c Inputting the value as a set value to a counter to complete the setting of the counter; when Y-SYSN is input to the counter, the counter is initialized to 0 and then starts to count; when each timeDetecting XF-CLK once, adding 1 to the counter value to enable the high level of the selector, outputting XJ-CLK, and when the counter value is increased to f c While the counter remains unchanged, the low level of the enable selector is asserted and the low level is output, thereby outputting f c A gap sampling clock XJ-CLK of each sampling pulse is transmitted to the AD sampling module; when the next Y-SYSN arrives, the counter restarts counting, and the process is repeated;
thus, the external synchronization is triggered by the Y-SYSN signal to intermittently sample the clock, the timing of which is shown in FIG. 5.
As shown in fig. 6, the synchronous trigger module includes an and gate and a trigger module; after the intermittent sampling clock is used as the AD clock, the system can ensure that AD finishes one-time sampling between two times of synchronous signal pulses. However, the initialization time of the system is not synchronized with the sampling synchronization signal, so that synchronization triggering is also required. The synchronous trigger signal is synthesized by the start signal and the Y-SYSN signal. Firstly, providing a starting signal for a synchronous trigger module through external equipment; Y-SYSN and a starting signal are simultaneously input into an AND gate, in the AND gate, when the Y-SYSN and the starting signal are simultaneously effective in high level, the Y-SYSN and the starting signal are input into a trigger module, when the trigger module detects that the rising edge of the starting signal arrives, the trigger module starts to receive and output the Y-SYSN to an AD sampling module, and after the rising edge, the trigger module is locked and does not output a synchronous signal SYSN; when the trigger module detects that the falling edge of the starting signal comes, the trigger module resets; the timing sequence is shown in fig. 7.
And the AD sampling module samples the synchronous signal SYSN when the XJ-CLK arrives to obtain sampling data.
The following further description of the start signal, which is the envelope processing of the start signal, is also needed.
Generally, the start signal mainly has a delay level signal or a pulse signal, and the start signal required by AD synchronization is a high-level delay and a pulse of a falling edge, and the different forms of the start signal affect the operation of the system, so that the compatibility of two different signals needs to be processed. In this embodiment, the start signal is subjected to envelope processing and converted into a reasonable start signal.
If the start signal is a continuous pulse signal, the pulse signal needs to be integrated into high and low frequencies of the full frequency domain. Envelope detection of the signal is therefore employed to address this problem. The pulse type start signal needs to wait until the end of the pulse to start the synchronization of the system, so that all the pulses can be regarded as a high level until the end of the pulse band, and then the low level is restored again. Because it is necessary to determine whether the pulse signal is finished, the time t needs to be set, t is about 20 times the period of the pulse signal, t can be calculated by the system clock frequency, and can be replaced by system pulse counting. Therefore, all the two adjacent starting pulses with the time interval smaller than t are counted as pulses in the same starting signal, and when the next starting signal does not appear within the time t after the end of one starting pulse, the end of the starting signal can be regarded.
Since the system clock count can be used to calculate the time t after the end, the envelope detection can also be compatible with the start level signal which lasts at a high level, the effective time t of the new start signal is longer than the set start signal effective time, the synchronous start of the system is not affected, and therefore the new start signal can be directly input into the synchronous trigger module for use, and finally, the timing diagram is as shown in fig. 8.
Noise analysis example:
exemplified by AD7768, a product of adno semiconductors (ADI). The relation between the sampling ratio of the AD7768 chip and the noise is shown in Table 1, and the relation between the sampling ratio and the delay under different modes is shown in Table 2 (AD 7768 data manual).
TABLE 1
TABLE 2
In the fast mode, a broadband filter is built from synchronous signal input to data, the time delay built by the system adopting the invention is 9153 under the condition that the sampling coefficient is 1024, the sampling delay is similar to 9153 by adopting the traditional mode, and the sampling coefficient of the mode is only 32 and is far less than 1024. Since the sampling coefficient is inversely proportional to the square of the noise, compared with the conventional method, the noise is reduced by 5 times, and the method is very suitable for the external synchronization of continuous equal interval sampling of the sigma-delta type AD.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.
Claims (3)
1. An external synchronization apparatus for continuous equal interval sampling of sigma-delta type AD, comprising: the clock pre-disciplining module, the intermittent synchronous clock generator, the synchronous triggering module and the AD sampling module;
the clock pre-tame module comprises a frequency discriminator, a feedback filter, a Voltage Controlled Oscillator (VCO) and a frequency divider; after the external synchronous clock signal Y-SYSN with equal gaps is input into the clock pre-tame module, the frequency discriminator counts the number of pulses of the sampling clock signal XF-CLK output by the frequency divider within a complete period T of the Y-SYSN, and the number is marked as f x (ii) a Then counting the number of pulses required by the AD sampling module to complete one-time complete sampling, and recording as f c (ii) a The number of pulses f x And the number of pulses f c When f is compared to the sum of the reserved values Δ x Is stabilized at f c ～(f c + delta), at this time, the loop is considered to be locked, the input signal is disciplined and completed, and therefore the disciplined clock signal XF-CLK is directly output; otherwise, converting the comparison result, i.e. frequency error, into voltage signal, inputting the voltage signal into a feedback filter, filtering out high-frequency component to form stable DC voltage signal, and using the stable DC voltage signal as control voltage of the voltage-controlled oscillator for controllingThe voltage-controlled oscillator is made to output a frequency division signal to the frequency divider, the frequency divider realizes frequency division output according to the frequency division signal, and the specific output process is as follows: if f is x >f c + delta, performing frequency division output on the XF-CLK through the frequency divider, reducing the clock frequency of the XF-CLK, and then outputting the XF-CLK; if f is x ＜f c Then, the XF-CLK is subjected to frequency division output through a frequency divider, the clock frequency of the XF-CLK is improved, and then the XF-CLK is output; after repeated discipline, the frequency of XF-CLK is stabilized at (T/f) c +Δ)～(T/f c ) To (c) to (d);
the intermittent synchronous clock generator comprises a counter and a selector; firstly, the number f of pulses c Inputting the value as a set value to a counter to complete the setting of the counter; when Y-SYSN is input to the counter, the counter is initialized to 0, and then starts counting; when XF-CLK is detected once, the counter value of the counter is increased by 1, the high level of the selector is enabled, XJ-CLK is output, and when the counter value of the counter is increased to f c While the counter remains unchanged, the low level of the enable selector is asserted and the low level is output, thereby outputting f c A gap sampling clock XJ-CLK of each sampling pulse is transmitted to the AD sampling module; when the next Y-SYSN arrives, the counter restarts counting, and the process is repeated;
the synchronous trigger module comprises an AND gate and a trigger module; firstly, providing a starting signal for a synchronous trigger module through external equipment; Y-SYSN and a starting signal are simultaneously input to an AND gate, when the Y-SYSN and the starting signal are simultaneously effective in high level, the Y-SYSN and the starting signal are input to a trigger module, when the trigger module detects that the rising edge of the starting signal arrives, the trigger module starts to receive and output the Y-SYSN to an AD sampling module, and after the rising edge, the trigger module is locked and does not output a synchronous signal SYSN; when the trigger module detects that the falling edge of the starting signal comes, the trigger module resets;
and the AD sampling module samples the synchronous signal SYSN when the XJ-CLK arrives to obtain sampling data.
2. A sigma-delta type AD external synchronization apparatus for continuous equal interval sampling according to claim 1, wherein said enable signal is a delayed level signal or a pulse signal;
when the starting signal is a delay level signal, the signal is directly input into the synchronous trigger module for use;
when the starting signal is a pulse signal, the pulse signal is integrated into high and low electric frequencies of a full frequency domain through envelope detection, and then the high and low electric frequencies are converted into a level signal to be provided to the synchronous trigger module for use.
3. A sigma-delta AD external synchronization device for continuous equal interval sampling according to claim 2, wherein said converting the pulse signal into the level signal comprises:
calculating the set time t through the clock frequency of the device, wherein t is 20 times of the period of the pulse signal;
if the time interval between two adjacent pulses is less than t, the pulses are regarded as pulses in the same starting signal, and if the next starting signal does not appear within the time t after the certain starting signal is finished, the starting signal is regarded as finished; thus, all pulses before the end of the pulse band are regarded as a high level until the end, and then the low level is restored.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911293360.4A CN110971238B (en) | 2019-12-16 | 2019-12-16 | External synchronization device for continuous equal-gap sampling of sigma-delta type AD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911293360.4A CN110971238B (en) | 2019-12-16 | 2019-12-16 | External synchronization device for continuous equal-gap sampling of sigma-delta type AD |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110971238A CN110971238A (en) | 2020-04-07 |
| CN110971238B true CN110971238B (en) | 2023-04-18 |
Family
ID=70034396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911293360.4A Active CN110971238B (en) | 2019-12-16 | 2019-12-16 | External synchronization device for continuous equal-gap sampling of sigma-delta type AD |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110971238B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112379617B (en) * | 2020-11-05 | 2022-03-15 | 中国航空工业集团公司西安航空计算技术研究所 | Anti-interlocking circuit for preventing channel of fault-tolerant system from being locked and redundancy fault-tolerant system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0813321A2 (en) * | 1996-06-14 | 1997-12-17 | TEMIC TELEFUNKEN microelectronic GmbH | Method and control system for data transmission |
| JP2000295207A (en) * | 1999-04-07 | 2000-10-20 | Matsushita Electric Ind Co Ltd | Clock reproducing device in simplex satellite communication |
| CN109428598A (en) * | 2017-08-30 | 2019-03-05 | 北京智云芯科技有限公司 | The calibration method and system of data sampling |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3998532B2 (en) * | 2002-08-07 | 2007-10-31 | 株式会社ルネサステクノロジ | Data transfer device |
| CN101257303A (en) * | 2008-04-11 | 2008-09-03 | 天津大学 | Sigma-Delta modulator clock control circuit in Sigma-Delta decimal fraction frequency synthesizer |
| US8284888B2 (en) * | 2010-01-14 | 2012-10-09 | Ian Kyles | Frequency and phase acquisition of a clock and data recovery circuit without an external reference clock |
| CN107863967B (en) * | 2017-11-15 | 2021-04-30 | 中国电子科技集团公司第四十一研究所 | Multichannel synchronous output calibration device and method |
-
2019
- 2019-12-16 CN CN201911293360.4A patent/CN110971238B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0813321A2 (en) * | 1996-06-14 | 1997-12-17 | TEMIC TELEFUNKEN microelectronic GmbH | Method and control system for data transmission |
| JP2000295207A (en) * | 1999-04-07 | 2000-10-20 | Matsushita Electric Ind Co Ltd | Clock reproducing device in simplex satellite communication |
| CN109428598A (en) * | 2017-08-30 | 2019-03-05 | 北京智云芯科技有限公司 | The calibration method and system of data sampling |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110971238A (en) | 2020-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3217556B1 (en) | Synchronization of outputs from multiple digital-to-analog converters | |
| JP4754578B2 (en) | Phase comparator and phase adjustment circuit | |
| TWI535213B (en) | Clock and data recovery circuit and method | |
| CN102916693B (en) | All-digital phase-locked ring applicable to video signal processing | |
| US7676014B2 (en) | Digital lock detector for phase-locked loop | |
| CN105549379A (en) | Synchronous measurement apparatus based on high precision time reference triggering and method thereof | |
| CN108881718B (en) | Synchronous control method of multi-group TDI CMOS imaging system | |
| US9325487B1 (en) | Systems and methods for transferring a signal from a first clock domain to a second clock domain | |
| CN101051837B (en) | Frequency correcting device and its method USB interface built-in vibrator | |
| JPH08307250A (en) | Digital pll | |
| WO2006044123A1 (en) | Reducing metastable-induced errors from a frequency detector that is used in a phase-locked loop | |
| CN110971238B (en) | External synchronization device for continuous equal-gap sampling of sigma-delta type AD | |
| EP2815532B1 (en) | Audio receiver and sample rate converter without pll or clock recovery | |
| TWI556584B (en) | Phase detecting apparatus and phase adjusting method | |
| CN111262578B (en) | Multi-chip synchronization circuit, system and method for high-speed AD/DA (analog-to-digital/digital) chip | |
| CN107026647B (en) | Time-to-digital system and frequency synthesizer | |
| US7826581B1 (en) | Linearized digital phase-locked loop method for maintaining end of packet time linearity | |
| US4771442A (en) | Electrical apparatus | |
| CN102055469B (en) | Phase discriminator and phase locked loop circuit | |
| US20100019757A1 (en) | System and method for on-chip duty cycle measurement | |
| US11804921B2 (en) | Method and apparatus for high precision time stamping | |
| US20040124929A1 (en) | Frequency detector detecting variation in frequency difference between data signal and clock signal | |
| US7023944B2 (en) | Method and circuit for glitch-free changing of clocks having different phases | |
| US20040041947A1 (en) | Frequency controller | |
| US7359468B2 (en) | Apparatus for synchronizing clock and data between two domains having unknown but coherent phase |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |