CN101257303A - Sigma-Delta modulator clock control circuit in Sigma-Delta decimal fraction frequency synthesizer - Google Patents
Sigma-Delta modulator clock control circuit in Sigma-Delta decimal fraction frequency synthesizer Download PDFInfo
- Publication number
- CN101257303A CN101257303A CN 200810052703 CN200810052703A CN101257303A CN 101257303 A CN101257303 A CN 101257303A CN 200810052703 CN200810052703 CN 200810052703 CN 200810052703 A CN200810052703 A CN 200810052703A CN 101257303 A CN101257303 A CN 101257303A
- Authority
- CN
- China
- Prior art keywords
- sigma
- delta modulator
- divider
- frequency
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention relates to a sigma-delta modulator clock control circuit in sigma-delta decimal frequency synthesizer, comprising a sigma-delta modulator which receives VCO signal output by a voltage controlled oscillator connected outside, and a signal delay unit which receives the signal output by the sigma-delta modulator. The delay unit comprises a frequency divider and a delay circuit, wherein the input end of the frequency divider receives the VCO signal output by the outer voltage controlled oscillator, and is connected with the sigma-delta modulator to receive the signal of the sigma-delta modulator. The output ends of the frequency divider are respectively connected with an outer PFD and the delay circuit, and the delay circuit outputs sigma-delta modulator clock signal to the sigma-delta modulator. The invention has wide adaptability without the consideration of the structures of the frequency divider and DSM in decimal frequency synthesizer, and can ensure the correct reading of frequency dividing number for the frequency divider, eliminate the influence of overturn of the digital circuit switch on the PFD, thus guaranteeing the accuracy of phase comparison and enhancing the system performance.
Description
Technical field
The present invention relates to a kind of sigma-delta modulator clocking technique.The frequency divider that particularly relates in a kind of no matter decimal type frequency synthesizer adopts which kind of structure, DSM to adopt which kind of structure, can use to guarantee that frequency divider reads in correct divider ratio, and eliminate the influence of digital circuit switch upset, and then sigma-delta modulator clock control circuit in the ∑-Δ decimal fraction frequency synthesizer of raising systematic function to PFD.
Background technology
As shown in Figure 1, the frequency synthesizer based on phase-locked loop structures comprises: elementary cells such as phase frequency detector (PFD), charge pump, filter, voltage controlled oscillator (VCO) and frequency divider.Reference frequency of phase frequency detector input, simultaneously the output frequency of voltage controlled oscillator also is input to phase frequency detector after by the frequency divider frequency division, phase frequency detector is by comparing the difference of these two incoming frequency phase places, and then control voltage controlled oscillator change output frequency, thereby making output frequency reach the target frequency value---the reference frequency multiply by the frequency division multiple.On the basis of above-mentioned phase-locked loop structures, ∑-Δ decimal fraction frequency synthesizer has been realized fractional frequency division, and promptly the frequency division multiple can be a fractional value, and is not only limited to integer.This fractional frequency division is that the method that the integral frequency divisioil value by continuous change frequency divider makes its mean value reach the expectation decimal realizes, the variation of frequency division modulus is controlled by sigma-delta modulator (DSM) and finished.In the circuit, DSM needs a clock signal to trigger, and triggers along the quantification output of DSM at each to change, and divider ratio changes thereupon.Usually, the clock signal of DSM is reference clock Tref or the signal of voltage controlled oscillator output behind frequency division, just a road of phase frequency detector (PFD) input comparison signal Tdiv.But all there is certain problem in actual applications in above-mentioned two kinds of schemes, cause the degradation of frequency synthesizer, even can't lock.
Because the divider ratio of decimal fraction frequency synthesizer is constantly to change, so the counting unit in the frequency divider will read in next divider ratio behind each complete frequency division end cycle, adopts the spill over of counting unit to control reading in of next divider ratio usually.If being provided by reference clock Tref, the clock signal of DSM will produce following problem: if the periodic signal behind some frequency divisions is ahead of reference clock signal, that is to say at a complete frequency division week after date DSM and also do not export new divider ratio, the divider ratio that is still one-period that frequency counter reads in, thus average fractional frequency division value mistake caused.Usually divider ratio is more little, and this influence is obvious more.If divider ratio is very little, this deviation will cause output frequency significantly to be swung, and loop can't lock.
Signal Tdiv behind the selection frequency division can avoid top problem as the clock signal of DSM.But DSM belongs to digital circuit, clock is after triggering, will there be a large amount of metal-oxide-semiconductor generation switch upsets its inside, and also PFD moment of carrying out the phase bit comparison just this moment, after system reached lock-out state, it is extremely short that the signal that PFD compared successively differs, if this digital switch upset is coupled on the PFD by power supply or substrate, to make PFD error relatively occur, and cause extra phase deviation, therefore the overall noise of system also will reduce.Certain situation about providing by reference frequency for preceding a kind of DSM clock, except that aforementioned problem of reading in the divider ratio mistake exists, because phase frequency detector two-way input phase difference was little when loop reached locking, also can exist the upset of DSM digital switch to influence the problem of PFD phase bit comparison.
Summary of the invention
Technical problem to be solved by this invention is, provide the frequency divider in a kind of no matter decimal type frequency synthesizer to adopt which kind of structure, DSM to adopt which kind of structure, can use to guarantee that frequency divider reads in correct divider ratio, and eliminate the influence of digital circuit switch upset, and then sigma-delta modulator clock control circuit in the ∑-Δ decimal fraction frequency synthesizer of raising systematic function to PFD.
The technical solution adopted in the present invention is: sigma-delta modulator clock control circuit in a kind of ∑-Δ decimal fraction frequency synthesizer, include sigma-delta modulator, receive VCO signal that sends with the outside voltage controlled oscillator that is connected and the delay cell that receives the signal that sigma-delta modulator sent.
Described delay cell includes frequency divider and delay circuit, and wherein, the input of frequency divider receives the VCO signal that external voltage-controlled oscillators sends, and the input of frequency divider also is connected with sigma-delta modulator receives the signal that it sent; The output of frequency divider connects outside PFD and connection delay circuit respectively, and delay circuit is to sigma-delta modulator output sigma-delta modulator clock signal.
Described delay circuit is made of the phase-inverting chain that a plurality of not gate F form.
Described sigma-delta modulator is the sigma-delta modulator of MASH1-1-1 structure.
Described frequency divider includes the n/n+1 pre-divider and links to each other with the n/n+1 pre-divider and receive the P-S program counter of its signal, described delay circuit adopts the TSPC-D trigger, wherein, the input of n/n+1 pre-divider receives the VCO signal that voltage controlled oscillator sends, the n/n+1 pre-divider sends clock signal to the TSPC-D trigger, the TSPC-D trigger is to sigma-delta modulator output sigma-delta modulator clock signal, and the output of sigma-delta modulator links to each other with the P-S program counter; The output of described P-S program counter is respectively to outside PFD and TSPC-D trigger.
Described sigma-delta modulator is four three rank modulators of Single-loop.
Sigma-delta modulator clock control circuit in ∑ of the present invention-Δ decimal fraction frequency synthesizer, adopt delay technology and related circuit structure, solved the problem that exists in existing ∑-Δ decimal type frequency synthesizer, guarantee that frequency divider reads in correct divider ratio, and can effectively avoid the influence of digital circuit switch upset to the bit comparison of PFD phase, guaranteed the accuracy of phase bit comparison.The present invention has extensive applicability, no matter the frequency divider in the decimal type frequency synthesizer adopts which kind of structure, DSM to adopt which kind of structure, can use, and reads in correct divider ratio to guarantee frequency divider, and eliminate the influence of digital circuit switch upset, and then improve systematic function to PFD.
Description of drawings
Fig. 1 is the ∑ based on the phase-locked loop structures-Δ decimal type frequency synthesizer structure principle chart of prior art;
Fig. 2 is circuit theory diagrams of the present invention;
Fig. 3 is the circuit theory diagrams of a kind of embodiment of Fig. 2;
Fig. 4 is the circuit theory diagrams of another embodiment of Fig. 2.
1: delay cell 2: frequency divider
3: delay circuit 4: sigma-delta modulator
5:7/8 pre-divider 6:P-S program counter
The 7:TSPC-D trigger
Embodiment
Accompanying drawing below in conjunction with embodiment makes a detailed description sigma-delta modulator clock control circuit in ∑ of the present invention-Δ decimal fraction frequency synthesizer.
Sigma-delta modulator clock control circuit in ∑ of the present invention-Δ decimal fraction frequency synthesizer includes sigma-delta modulator 4 (DSM), receives the VCO signal that sends with the outside voltage controlled oscillator that is connected and receives sigma-delta modulator 4
(DSM) delay cell 1 of the signal that is sent.The present invention adds the technology of delay cell, guaranteed that promptly frequency divider reads in correct divider ratio, make simultaneously digital circuit switch upset and PFD mutually the bit comparison time stagger, thereby can effectively avoid digital circuit switch to overturn to the influence of PFD phase bit comparison, guaranteed the accuracy of phase bit comparison.Delay cell can utilize different circuit to realize, for example phase-inverting chain, trigger etc., and the selection of time of delay then wants the work characteristics of coupling system definite, will be enough to guarantee that PFD finishes the phase bit comparison time of delay.For decimal type frequency synthesizer, because divider ratio is in continuous variation, output frequency constantly changes, system may reach proper lock-out state never, the phase difference that is to say the two-way input comparison signal of PFD is changing all the time, and this also brings uncertainty for choosing of time of delay.But on macroscopic view, PFD phase of input signals difference is zero after through the long enough time integral.Based on this point, ignore the corrective action of the accumulation of phase difference and phase-locked loop systems to phase difference, think that approx the input phase difference of PFD is only relevant with the divider ratio of current period.(for example MASH1-1-1 structure output area is-3～4 because the divider ratio excursion of common ∑-Δ decimal fraction frequency synthesizer is less, four three stage structures of Single-loop are-1～2), therefore after system reaches lock-out state, PFD two-way input signal differs in time and can not exceed several VCO cycles, being slightly larger than this time time of delay can guarantee that frequency divider reads in correct divider ratio, the upset of phase bit comparison and digital circuit switch is staggered, thereby avoid the influence of digital circuit switch upset PFD.For example, the fractional frequency division value of expectation is 70.5, in a certain compare cycle/and the frequency dividing ratio of frequency divider is 70, the phase difference that then causes is 0.5 VCO cycle of oscillation, therefore makes half VCO cycle of DSM clock signal delay just can avoid digital switch to overturn to the influence of PFD.In side circuit, consider the influence of other factors, can be provided with time of delay slightly bigger.
As shown in Figure 2, described delay cell 1 includes frequency divider 2 and delay circuit 3, and wherein, the input of frequency divider 2 receives the VCO signal that external voltage-controlled oscillators sends, and the input of frequency divider 2 also is connected with sigma-delta modulator 4 receives the signal that it sent; The output of frequency divider 2 connects outside PFD (phase frequency detector) and connection delay circuit 3 respectively, and delay circuit 3 is to sigma-delta modulator 4 output sigma-delta modulator clock signals.
As shown in Figure 3, described delay circuit 3 can be made of the phase-inverting chain that a plurality of not gate F form.When the phase-inverting chain of being made up of a plurality of not gate F when delay circuit 3 constituted, described sigma-delta modulator 4 was the sigma-delta modulator of MASH1-1-1 structure.
The implementation method of above-mentioned delay technology is discussed under the situation of not considering the frequency divider concrete structure.Wherein, DSM uses the MASH1-1-1 structure, and delay cell adopts phase-inverting chain to realize.
The VCO output signal still is divided into two-way after by the frequency divider frequency division, and one the tunnel directly feeds back to PFD carries out the phase bit comparison, and another road input phase-inverting chain is delayed the clock signal of back as DSM.Phase-inverting chain should be even level, keeps output and input signal homophase.
The DSM output area of MASH1-1-1 structure is-3～4 in this programme, and according to the evaluation method of above-mentioned phase difference, actual frequency division value and desired value differ 4 under the worst condition, and the clock signal of DSM will postpone 4 VCO cycles at least so.Consider the influence of other factors in the side circuit, can be made as 6 VCO cycle times time of delay.With the VCO output frequency is that 2GHz is an example, the delay that needs the design phase-inverting chain to produce about 3ns.Consider the parameter of selected technology and the structure of side circuit, by the size of adjustment phase inverter and the progression control lag time of phase-inverting chain, can make the digital circuit switch upset of DSM occur in PFD and finish after the phase bit comparison, thereby guarantee the accuracy of phase bit comparison.
As shown in Figure 4, described frequency divider 2 can also be: include n/n+1 pre-divider 5 and link to each other with n/n+1 pre-divider 5 and receive the P-S program counter 6 of its signal, described delay circuit 3 adopts TSPC-D trigger 7, wherein, the input of n/n+1 pre-divider 5 receives the VCO signal that voltage controlled oscillator sends, n/n+1 pre-divider 5 sends clock signal to TSPC-D trigger 7, TSPC-D trigger 7 is to sigma-delta modulator 4 output sigma-delta modulator clock signals, and the output of sigma-delta modulator 4 links to each other with P-S program counter 6; The output of described P-S program counter 6 is respectively to outside PFD (phase frequency detector) and TSPC-D trigger 7.
Present embodiment is when situation as shown in Figure 4, and described sigma-delta modulator 4 adopts four three rank modulators, and pre-divider 5 adopts 7/8 pre-divider 5.
The foregoing description, pre-frequency division of frequency divider utilization (prescaler) and program counter realize, DSM adopts four three stage structures of Single-loop, and delay cell adopts TSPC (True Single Phase Clock, true single phase clock) structure high-speed d type flip flop to realize.
Because the output frequency of frequency synthesizer is higher, general program counter is difficult to need pre-frequency division to obtain the lower signal of frequency usually to its direct frequency division, carries out frequency division by program counter again.Reach the frequency synthesizer of GHz for output frequency, also in hundred order of megahertz, still higher, d type flip flop should adopt the high speed flip flop structure through the signal frequency behind the pre-frequency division.High speed flip flop commonly used mainly adopts TSPC and CML structures such as (Current Mode Logic, CMLs), and operating frequency can reach several GHz.Because CML structure d type flip flop needs differential input signal, the delay cell in this programme adopts the TSPC structure to realize, only needs single phase clock.The VCO output signal is divided into two-way after by the pre-divider frequency division, and one the tunnel directly feeds back to PFD carries out the phase bit comparison, i.e. Tdiv signal, and another road is through the clock signal of TSPC-D trigger as DSM.Compare with the Tdiv signal, the clock of DSM has been delayed the clock cycle of a d type flip flop, therefore choose suitable d type flip flop clock signal and can realize suitable delay, make the switch upset of DSM occur in PFD and finish after the phase bit comparison, thereby avoided the influence of switch upset PFD.
The output area of four three stage structure sigma-delta modulators of Single-loop is-1～2 in the present embodiment.Consider worst condition, actual frequency division value and desired value differ 2, then the delay of DSM clock is at least 2 VCO cycles, therefore as long as pre-divider can be finished twice or the above frequency division of twice, the delay that is produced by the TSPC-D trigger just can guarantee that the DSM switch overturns and avoid the time of PFD phase bit comparison so.Directly use the clock of the output signal of pre-divider as the TSPC-D trigger, its convenience is directly to utilize existing signal in the primary circuit structure, and without any need for additional circuit, make circuit structure simple, be easy to realize.
As being example with 7/8 pre-divider, promptly the clock of DSM has been delayed 7 or 8 VCO cycles, enough guarantees that the digital switch upset of DSM can not exert an influence to the bit comparison of PFD phase this time of delay, has avoided the phase error that may cause effectively.
Claims (6)
1. sigma-delta modulator clock control circuit in ∑-Δ decimal fraction frequency synthesizer, it is characterized in that, include sigma-delta modulator (4), receive the delay cell (1) of the signal that the VCO signal that sends with the outside voltage controlled oscillator that is connected and reception sigma-delta modulator (4) sent.
2. sigma-delta modulator clock control circuit in ∑ according to claim 1-Δ decimal fraction frequency synthesizer, it is characterized in that, described delay cell (1) includes frequency divider (2) and delay circuit (3), wherein, the input of frequency divider (2) receives the VCO signal that external voltage-controlled oscillators sends, and the input of frequency divider (2) also is connected with sigma-delta modulator (4) receives the signal that it sent; The output of frequency divider (2) connects outside PFD and connection delay circuit (3) respectively, and delay circuit (3) is to sigma-delta modulator (4) output sigma-delta modulator clock signal.
3. sigma-delta modulator clock control circuit in ∑ according to claim 2-Δ decimal fraction frequency synthesizer is characterized in that, described delay circuit (3) is made of the phase-inverting chain that a plurality of not gate F form.
4. sigma-delta modulator clock control circuit in ∑ according to claim 3-Δ decimal fraction frequency synthesizer is characterized in that, described sigma-delta modulator (4) is the sigma-delta modulator of MASH1-1-1 structure.
5. sigma-delta modulator clock control circuit in ∑ according to claim 2-Δ decimal fraction frequency synthesizer, it is characterized in that, described frequency divider (2) includes n/n+1 pre-divider (5) and links to each other with n/n+1 pre-divider (5) and receive the P-S program counter (6) of its signal, described delay circuit (3) adopts TSPC-D trigger (7), wherein, the input of n/n+1 pre-divider (5) receives the VCO signal that voltage controlled oscillator sends, n/n+1 pre-divider (5) sends clock signal to TSPC-D trigger (7), TSPC-D trigger (7) is to sigma-delta modulator (4) output sigma-delta modulator clock signal, and the output of sigma-delta modulator (4) links to each other with P-S program counter (6); The output of described P-S program counter (6) is respectively to outside PFD and TSPC-D trigger (7).
6. sigma-delta modulator clock control circuit in ∑ according to claim 5-Δ decimal fraction frequency synthesizer is characterized in that, described sigma-delta modulator (4) is four three rank modulators of Single-loop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810052703 CN101257303A (en) | 2008-04-11 | 2008-04-11 | Sigma-Delta modulator clock control circuit in Sigma-Delta decimal fraction frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810052703 CN101257303A (en) | 2008-04-11 | 2008-04-11 | Sigma-Delta modulator clock control circuit in Sigma-Delta decimal fraction frequency synthesizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101257303A true CN101257303A (en) | 2008-09-03 |
Family
ID=39891824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810052703 Pending CN101257303A (en) | 2008-04-11 | 2008-04-11 | Sigma-Delta modulator clock control circuit in Sigma-Delta decimal fraction frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101257303A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101635504B (en) * | 2009-08-20 | 2012-10-10 | 杭州士兰微电子股份有限公司 | Frequency dithering circuit and frequency dithering method as well as application thereof in switch power supply |
| CN102811052A (en) * | 2011-05-31 | 2012-12-05 | 比亚迪股份有限公司 | Phase-locked loop circuit |
| CN103051338A (en) * | 2012-11-29 | 2013-04-17 | 成都锐成芯微科技有限责任公司 | Fractional-N phase locked loop |
| CN103236841A (en) * | 2013-04-15 | 2013-08-07 | 北京大学 | Switching type phase frequency detector based on periodic comparison and digital phase-locked loop |
| CN103368567A (en) * | 2012-04-06 | 2013-10-23 | 联咏科技股份有限公司 | Frequency synthesizer |
| CN103560785A (en) * | 2013-10-28 | 2014-02-05 | 中国电子科技集团公司第四十一研究所 | Method and device for generating phase-coherent signals |
| CN103986457A (en) * | 2014-05-20 | 2014-08-13 | 硅谷数模半导体（北京）有限公司 | High-speed frequency divider |
| CN105656475A (en) * | 2014-12-02 | 2016-06-08 | 联发科技股份有限公司 | Fraction division circuit and related calibration method |
| CN109995360A (en) * | 2018-01-02 | 2019-07-09 | 珠海全志科技股份有限公司 | The phaselocked loop of disturbance suppression |
| CN110971238A (en) * | 2019-12-16 | 2020-04-07 | 电子科技大学 | External synchronization device for continuous equal-gap sampling of sigma-delta type AD |
| CN115150571A (en) * | 2021-03-30 | 2022-10-04 | 豪威科技股份有限公司 | Analog-to-digital converter clocking for extended analog gain and reduced noise |
-
2008
- 2008-04-11 CN CN 200810052703 patent/CN101257303A/en active Pending
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101635504B (en) * | 2009-08-20 | 2012-10-10 | 杭州士兰微电子股份有限公司 | Frequency dithering circuit and frequency dithering method as well as application thereof in switch power supply |
| CN102811052B (en) * | 2011-05-31 | 2015-08-26 | 比亚迪股份有限公司 | A kind of phase-locked loop circuit |
| CN102811052A (en) * | 2011-05-31 | 2012-12-05 | 比亚迪股份有限公司 | Phase-locked loop circuit |
| CN103368567B (en) * | 2012-04-06 | 2016-03-30 | 联咏科技股份有限公司 | Frequency synthesizer |
| CN103368567A (en) * | 2012-04-06 | 2013-10-23 | 联咏科技股份有限公司 | Frequency synthesizer |
| CN103051338A (en) * | 2012-11-29 | 2013-04-17 | 成都锐成芯微科技有限责任公司 | Fractional-N phase locked loop |
| CN103236841B (en) * | 2013-04-15 | 2016-06-15 | 北京大学 | Based on period ratio compared with switching regulator phase frequency detector and digital phase-locked loop |
| CN103236841A (en) * | 2013-04-15 | 2013-08-07 | 北京大学 | Switching type phase frequency detector based on periodic comparison and digital phase-locked loop |
| CN103560785A (en) * | 2013-10-28 | 2014-02-05 | 中国电子科技集团公司第四十一研究所 | Method and device for generating phase-coherent signals |
| CN103560785B (en) * | 2013-10-28 | 2017-05-10 | 中国电子科技集团公司第四十一研究所 | Method and device for generating phase-coherent signals |
| CN103986457A (en) * | 2014-05-20 | 2014-08-13 | 硅谷数模半导体（北京）有限公司 | High-speed frequency divider |
| CN103986457B (en) * | 2014-05-20 | 2016-08-24 | 硅谷数模半导体（北京）有限公司 | high-speed frequency divider |
| CN105656475A (en) * | 2014-12-02 | 2016-06-08 | 联发科技股份有限公司 | Fraction division circuit and related calibration method |
| CN105656475B (en) * | 2014-12-02 | 2018-12-11 | 联发科技股份有限公司 | Score division circuit and relevant bearing calibration |
| CN109995360A (en) * | 2018-01-02 | 2019-07-09 | 珠海全志科技股份有限公司 | The phaselocked loop of disturbance suppression |
| CN110971238A (en) * | 2019-12-16 | 2020-04-07 | 电子科技大学 | External synchronization device for continuous equal-gap sampling of sigma-delta type AD |
| CN115150571A (en) * | 2021-03-30 | 2022-10-04 | 豪威科技股份有限公司 | Analog-to-digital converter clocking for extended analog gain and reduced noise |
| CN115150571B (en) * | 2021-03-30 | 2023-11-28 | 豪威科技股份有限公司 | Analog-to-digital converter clocking for spreading analog gain and reducing noise |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101257303A (en) | Sigma-Delta modulator clock control circuit in Sigma-Delta decimal fraction frequency synthesizer | |
| US9270280B1 (en) | Half-integer frequency dividers that support 50% duty cycle signal generation | |
| CN101951260B (en) | Digital delay phase locked loop circuit | |
| US7365580B2 (en) | System and method for jitter control | |
| US8081018B2 (en) | Low power radio frequency divider | |
| Deng et al. | 14.1 a 0.048 mm 2 3mW synthesizable fractional-N PLL with a soft injection-locking technique | |
| CN102739239B (en) | High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider | |
| US9306585B1 (en) | Fractional-N multiplying injection-locked oscillation | |
| CN102594338B (en) | Counter control type delay-locked loop circuit with mistaken locking correction mechanism | |
| CN101277110A (en) | Clock generator method for generating clock signal and fractional phase lock loop thereof | |
| CN101908883B (en) | Programmable decimal frequency divider | |
| US8836391B2 (en) | Plesiochronous clock generation for parallel wireline transceivers | |
| CN101494457B (en) | Delay locked loop circuit and method for eliminating jitter and offset therein | |
| CN101465645B (en) | Decimals/integer frequency divider | |
| KR101611814B1 (en) | Wide range multi-modulus divider in fractional-n frequency synthesizer | |
| CN103312319B (en) | Be applied to the spurious reduction phase frequency detector circuit in integer-N PLL | |
| CN104579320A (en) | Clock delay method, clock delay device, delay-locked loop and digital clock management unit | |
| CN115378425A (en) | Half-integer step divider and divider including the same | |
| CN101841332B (en) | Digital phase-locked loop | |
| US20120161827A1 (en) | Central lc pll with injection locked ring pll or dell per lane | |
| CN101594147A (en) | Phase-locked loop circuit | |
| CN101478307B (en) | Dual mode 4/4.5 pre-divider | |
| CN102006065A (en) | Fractional phase-locked loop structure for reducing quantized noise of Sigma Delta modulator | |
| US7323913B1 (en) | Multiphase divider for P-PLL based serial link receivers | |
| CN101309082B (en) | Phase shifting multi-mode frequency dividing method based on clock frequency control and frequency divider |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20080903 |