CN109995360A - The phaselocked loop of disturbance suppression - Google Patents
The phaselocked loop of disturbance suppression Download PDFInfo
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- CN109995360A CN109995360A CN201810001974.XA CN201810001974A CN109995360A CN 109995360 A CN109995360 A CN 109995360A CN 201810001974 A CN201810001974 A CN 201810001974A CN 109995360 A CN109995360 A CN 109995360A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
Abstract
The present invention relates to a kind of phaselocked loops of disturbance suppression, it include: the first time delay module that input terminal is connect with reference clock signal and SDM modulator, the quantizing noise of phase adjustment is carried out for receiving reference clock signal and reference clock signal, the second time delay module that input terminal is connect with feedback clock signal and SDM modulator, for receiving the quantizing noise of feedback clock signal and the output of SDM modulator, the phase frequency detector being connect with the first time delay module and the second time delay module, for handling reference clock signal and feedback clock signal, obtain phase error information, and control signal is exported according to phase error information.Utilize the quantizing noise signal that SDM modulation generates in phaselocked loop, and quantizing noise is accessed into time delay module, phase adjustment is carried out to reference clock signal, so that reference clock signal is consistent with feedback clock signal phase, and control voltage controlled oscillator and make feedback clock signal frequency consistent with reference clock signal frequency, eliminate disturbance and noise.
Description
Technical field
The present invention relates to electronic technology fields, more particularly to a kind of phaselocked loop of disturbance suppression.
Background technique
Phase-locked loop is a kind of feedback control circuit, utilizes externally input reference signal control loop internal oscillation signal
Frequency and phase, be responsible for circuit and accurately clock signal be provided, be very important one in modern integrated circuits design
Module is usually made of phase frequency detector, filter and voltage controlled oscillator three parts, and wherein phase frequency detector is also known as phase ratio
Compared with device, effect is the phase difference for detecting input signal and output signal, and the phase signal that will test out is converted into voltage letter
Number output, forms the control voltage of voltage controlled oscillator, to voltage controlled oscillator output signal after the signal low-pass filtered device filtering
Frequency implement control.Phaselocked loop is in the process of work, defeated when the frequency of output signal is equal with the frequency of input signal
The phase difference value that voltage and input voltage are kept fixed, the i.e. phase of output voltage and input voltage are lockable out.
In order to generate the configurable clock of optional frequency, the most commonly used is the phaselocked loops of fractional frequency division, by locking phase
The frequency elimination coefficient of ring is modulated, so that output clock frequency is accurately preset decimal with input clock frequency ratio, in order to
Reduce influence of the modulation to the performance of entire phaselocked loop output clock, it will usually modulate using high-order sigma-delta.
In order to which the modulation for optimizing the phaselocked loop of fractional frequency division disturbs in industry, there are two class modes: first is that by adjusting loop
Parameter inhibits, and the method for adjusting bandwidth, which needs to disturb two factors in inhibition modulation disturbance and voltage controlled oscillator, compromises, no
The whole of disturbance are able to achieve to eliminate.Second is that usually being offset by additional circuit module to modulation disturbance, generally in frequency discrimination
Phase discriminator addition later is carried out by the data converter that quantizing noise controls, but frequency discrimination mirror is compensated using data converter
The mode of the noise of phase device is more demanding to Circuit Matching, and the effect of optimization modulation disturbance is also undesirable.
Summary of the invention
Based on this, it is necessary to there is disturbance in circuit, provide a kind of phaselocked loop of disturbance suppression.
A kind of phaselocked loop of disturbance suppression, comprising:
The first time delay module that input terminal is connect with reference clock signal and SDM modulator, for receiving reference clock
The quantizing noise of signal and the output of SDM modulator, the quantizing noise carry out phase adjustment to the reference clock signal；
The second time delay module that input terminal is connect with feedback clock signal and SDM modulator, for receiving feedback clock
The quantizing noise of signal and the output of SDM modulator, the quantizing noise carry out phase adjustment to the feedback clock signal；
The phase frequency detector being connect with first time delay module and second time delay module, when for the reference
Clock signal and the feedback clock signal are handled, and obtain phase error information, and export according to the phase error information
Control signal；
The voltage controlled oscillator being connect with the phase frequency detector, for generating output signal according to the control signal；
Connect with the phase frequency detector and SDM modulator connection frequency eliminator, for according to the voltage controlled oscillator
Output signal generates feedback clock signal.
Further include in one of the embodiments, connect with the output end of the phase frequency detector, with the voltage controlled oscillation
The filter of the input terminal connection of device, for being filtered to the control signal.
The voltage controlled oscillator is also used to the vibration according to the control signal control phaselocked loop in one of the embodiments,
Swing frequency.
The divisor factor of the frequency eliminator is by the phaselocked loop after SDM modulators modulate in one of the embodiments,
It generates.
The SDM modulator is modulated by sigma-delta and generates quantizing noise in one of the embodiments, and right
The reference clock signal and the feedback clock signal carry out phase adjustment, so that reference clock signal and feedback clock signal
Phase is consistent.
In one of the embodiments, when the output signal and output frequency that detect the voltage controlled oscillator do not go out
When the existing quantizing noise, the phase adjustment of the reference clock signal and the feedback clock signal is consistent.
The delay of the quantizing noise and first time delay module and the second time delay module in one of the embodiments,
Time, first time delay module carried out delay process to the reference clock signal there are fixed conversion relationship, and described second
Time delay module carries out delay process to the feedback clock signal, and the quantizing noise controls institute according to the fixed conversion relationship
It states the first time delay module and the second time delay module carries out the time span of delay process.
In one of the embodiments, the delay time of first time delay module and the second time delay module with it is described voltage-controlled
The cycle of oscillation of oscillator is consistent.
The phaselocked loop is fractional frequency-division phase-locked loop in one of the embodiments, passes through the frequency elimination coefficient to phaselocked loop
It is modulated through sigma-delta, so that output clock frequency and input clock frequency ratio are preset value.
In one of the embodiments, the SDM modulator include integrator, the comparator being connect with the integrator,
The digital analog converter being connect with the comparator and the decimation filter of digital being connect with the digital analog converter；
The input signal of the integrator is the ratio of the output clock frequency and the input clock frequency, the product
The output signal for dividing device is ramp signal, and the slope of the ramp signal and the input signal amplitude of integrator are directly proportional；
The integrator output is compared with the reference signal of the comparator, and the binary system for obtaining the comparator is defeated
Out；
The binary system output of the comparator is sent into decimation filter of digital based on digital analog converter；
The decimation filter of digital carries out digital decimation to the binary system output of the comparator, obtains the SDM tune
The output of device processed.
The phaselocked loop of above-mentioned disturbance suppression is made an uproar using the quantization that sigma-delta modulation generates in fractional frequency-division phase-locked loop
Acoustical signal, and by quantizing noise access reference clock path on delay unit and feedback clock signal path on delay list
Member is adjusted using phase of the quantizing noise to reference clock signal and feedback clock signal, eliminates disturbance and noise.
Detailed description of the invention
Fig. 1 is the structural block diagram of the phaselocked loop of the phaselocked loop of disturbance suppression in the present invention in one embodiment；
Fig. 2 is the SDM modulator structure block diagram in the present invention in phaselocked loop one embodiment of disturbance suppression.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 1 is the structural block diagram of the phaselocked loop of the phaselocked loop of disturbance suppression in the present invention in one embodiment, such as Fig. 1 institute
Show: the phaselocked loop of disturbance suppression includes: SDM modulator 10, the first time delay module 202, the second time delay module 204, frequency and phase discrimination
Device 30, filter 40, voltage controlled oscillator 50 and frequency eliminator 60.
Phaselocked loop is a kind of feedback control circuit for the purpose of eliminating frequency error, the basic principle is that using external defeated
The frequency and phase of the reference signal control loop internal oscillation signal entered go to eliminate frequency error using phase error voltage.
In the process of work, when the frequency of output signal is equal with the frequency of input signal, output voltage and input voltage are kept
Fixed phase difference value, so after circuit reaches equilibrium state, although frequency error can with the presence of residual phase error
To be reduced to zero, to realize frequency-tracking and Phase Tracking without frequency difference.
The input terminal of first time delay module 202 is connect with reference clock signal and SDM modulator 10, for receiving reference
The quantizing noise that clock signal and SDM modulator 10 export, quantizing noise carry out phase adjustment to reference clock signal.
Specifically, the first time delay module 202 carries out delay process to reference clock signal, and the first time delay module 202 can be with
Including etc. multiple delay units, delay unit be the important module of IC design, can pass through generate delay solve letter
The delay difference in number path, and clock signal is provided, to meet the particular requirement of system.
Quantization is exactly to send collected numerical value to quantizer to be encoded into number, and each number represents primary sampling and obtained
Voice signal instant value.For quantizing process there are quantization error, receiving end is arrived in reflection, and this error claims as noise regenerative
For quantizing noise.In the present embodiment, quantizing noise can be adjusted the phase of reference clock signal.
The input terminal of second time delay module 204 is connect with feedback clock signal and SDM modulator 10, for receiving feedback
The quantizing noise that clock signal and SDM modulator 10 export, quantizing noise carry out phase adjustment to feedback clock signal.
Specifically, the second time delay module 204 carries out delay process to feedback clock signal, and the second time delay module 204 can be with
Including etc. multiple delay units, delay unit be the important module of IC design, can pass through generate delay solve letter
The delay difference in number path, and clock signal is provided, to meet the particular requirement of system.
When quantization, entire amplitude is divided into several quantized levels i.e. quantized data digit, the sample value for falling into same level-one
It is classified as one kind, and gives a quantized value.Quantization series is more, and for quantization error with regard to smaller, sound quality is better.Quantizing process
There are quantization error, reflection arrives receiving end, becomes quantizing noise.In the present embodiment, quantizing noise can be to feedback clock signal
Phase be adjusted.
Phase frequency detector 30 is connect with the first time delay module 202 and the second time delay module 204, for reference clock signal
It is handled with feedback clock signal, obtains phase error information, and control signal is exported according to phase error information.
The circuit that phase discriminator is used to that the phase difference between output voltage and two input signals to be made to have determining relationship indicates defeated
The function of the phase difference relationship between voltage and two input signals is known as phase characteristic out, is also used for frequency modulation and phase-modulated signal
Demodulation.
Specifically, phase frequency detector 30 is a kind of digital phase discriminator, and reference clock signal and feedback clock signal are pulses
Sequence, forward position or rear along respective phase is respectively represented, can obtain by comparing the frequency and phase of the two pulse trains
To output related with phase difference to get the phase error information for arriving reference clock signal and feedback clock signal, because of its phase demodulation
Characteristic is zigzag, therefore also has both frequency discrimination effect.Wherein, reference clock signal is the clock signal for inputting phaselocked loop, when feedback
Clock signal is to be handled to obtain via frequency eliminator 60 by the output of voltage controlled oscillator 50.
Voltage controlled oscillator 50 is connect with phase frequency detector 30, for generating output signal according to control signal.
Specifically, output frequency and input control voltage have the oscillating circuit of corresponding relationship, and frequency is applied signal voltage
Oscillation of a function device, the control of the component parameters of the working condition of oscillator or oscillation circuit by input control voltage, so that it may
Constitute a voltage controlled oscillator 50.Voltage controlled oscillator 50 generates output signal according to the control signal that phase frequency detector 30 exports,
And using output signal as the input signal of frequency eliminator 60.
Frequency eliminator 60 is connect with phase frequency detector 30 and SDM modulator 10, for being believed according to the output of voltage controlled oscillator 50
Number generate feedback clock signal.
Specifically, frequency eliminator 60 using the output of voltage controlled oscillator 50 as input, and by the output of voltage controlled oscillator 50 into
Row frequency elimination handles to obtain feedback clock signal, then feedback clock signal is accessed phase frequency detector 30.
The phaselocked loop of above-mentioned disturbance suppression is made an uproar using the quantization that sigma-delta modulation generates in fractional frequency-division phase-locked loop
Acoustical signal, and by quantizing noise access reference clock path on delay unit and feedback clock signal path on delay list
Member is adjusted using phase of the quantizing noise to reference clock signal and feedback clock signal, eliminates disturbance and noise.
It in one of the embodiments, further include being connect with the output end of phase frequency detector 30, being with voltage controlled oscillator defeated
The filter 70 for entering end connection, for being filtered to control signal.
The filter circuit that filter 70 is made of capacitor, inductance and resistance, can be to the frequency of specific frequency in power supply line
Frequency other than point or the frequency point is effectively filtered out, and obtains the power supply signal of a specific frequency, or eliminate a specific frequency
Power supply signal after rate can also become a specific frequency for by a square wave group after filter 70 or compound wave of making an uproar
Sine wave.
In another embodiment, voltage controlled oscillator 50 is also used to the frequency of oscillation according to control signal control phaselocked loop.
Specifically, voltage controlled oscillator 50 is usually known as frequency modulator, to generate FM signal.In cycle of phase-locked loop,
Input control voltage is error voltage, and voltage controlled oscillator 50 is a controlled part in loop, therefore voltage controlled oscillator 50
Effect in phase-locked loop circuit is to generate frequency with the oscillating voltage of control voltage change, and control the oscillation frequency of phaselocked loop
Rate.
In a further embodiment, the divisor factor of frequency eliminator 60 carries out sigma- through SDM modulator 10 by phaselocked loop
It is generated after delta modulation.
Specifically, the divisor factor of frequency eliminator 60 is used to that the degree to the processing of signal frequency elimination to be arranged, and can pass through phaselocked loop
It is generated after SDM modulator 10 carries out sigma-delta modulation, wherein phaselocked loop can be fractional frequency-division phase-locked loop, decimal point
Frequency refers to output cycle accurate and input clock frequency in presupposition multiple, so that output cycle accurate and input clock frequency are presented
Presupposition multiple, the presupposition multiple that presents with input clock frequency of output cycle accurate is modulated via SDM modulator 10, obtains
To the divisor factor of frequency eliminator 60.
SDM modulator 10 is modulated by sigma-delta and generates quantizing noise in one of the embodiments, and to ginseng
It examines clock signal and feedback clock signal carries out phase adjustment, so that reference clock signal is consistent with feedback clock signal phase.
SDM modulation refers to that sigma-delta (Σ Δ) is modulated, and is a kind of turn based on oversampling technique and noise shaping techniques
Parallel operation, the over sampling sigma-delta switch technology in high-resolution A/D, D/A converter, its working principle is that: benefit
With negative-feedback concept in classical Theory of Automatic Control, improved by feedback loop the effective resolution of coarse quantization device and shaping its
Quantizing noise.After carrying out over sampling to signal, noise power spectrum amplitude reduction, and be in low pass to quantization to input by one
Noise is in the noise reshaper of high pass, and the overwhelming majority of quantization noise power is moved on to except signal band, so as to pass through filter
Wave effectively inhibits noise.By trying again narrow-band low pass filtering processing to the digital quantity carried out after analog-to-digital conversion, when
After analog quantity enters converter, quadrature processing is first done in the modulator, and analog quantity is switched into digital quantity, in this process can
A certain amount noise is generated, this noise will affect output result.
In the present embodiment, by modulating the quantizing noise signal generated using sigma-delta in fractional frequency-division phase-locked loop,
And phase adjustment is carried out to reference clock signal and feedback clock signal using quantizing noise, so that reference clock signal and feedback
Clock signal phase is consistent, achievees the effect that eliminate disturbance.
In another embodiment, when the output signal and output frequency that detect voltage controlled oscillator 50 are not measured
When changing noise, the phase adjustment of reference clock signal and feedback clock signal is consistent.
Specifically, because carrying out the first delay of quantizing noise access that sigma-delta modulation generates by SDM modulator 10
Module 202 and the second time delay module 204, therefore before reference clock signal and feedback clock signal access phase frequency detector 30,
Quantizing noise can be adjusted the phase of reference clock signal and feedback clock signal, while pass through two signal cancellation quantizations
Noise, therefore in the phase error information obtained after phase frequency detector 30, then the control voltage obtained by voltage controlled oscillator 50
And output frequency is not in quantizing noise, the phase adjustment of available reference clock signal and feedback clock signal is
Consistent conclusion.
In one of the embodiments, when the delay of quantizing noise and the first time delay module 202 and the second time delay module 204
Between there are fixed conversion relationship, the first time delay module 202 carries out delay process, the second time delay module 204 to reference clock signal
Delay process is carried out to feedback clock signal, quantizing noise controls the first time delay module 202 and second according to fixed conversion relationship
The time span of the progress delay process of time delay module 204.
Specifically, quantization is exactly to send collected numerical value to quantizer to be encoded into number, and each number, which represents, once adopts
The instant value of sample voice signal obtained.When quantization, entire amplitude is divided into several quantized levels i.e. quantized data digit,
The sample value for falling into same level-one is classified as one kind, and gives a quantized value.Quantization series is more, and quantization error is with regard to smaller, sound
Quality is better.For quantizing process there are quantization error, receiving end is arrived in reflection, and this error is made an uproar as noise regenerative, referred to as quantization
Sound.Noise can be reduced to the degree that can not be discovered by increasing quantization digit, but with the reduction of signal amplitude, quantizing noise with
Correlation between signal becomes readily apparent from.
Optionally, quantizing noise represents digital bit signal, there are fixed transforming relationship, such as 3 with delay time
Bit represents 8 information units, including 000,001,010,011,100,101,110 and 111, wherein settable 000 corresponding 1
A delay unit, 001 corresponding 2 delay units, 010 corresponding 3 delay units, can and so on.
In another embodiment, the delay time and voltage controlled oscillation of the first time delay module 202 and the second time delay module 204
The cycle of oscillation of device 50 is consistent.
Effect of the voltage controlled oscillator 50 in phase-locked loop circuit is oscillating voltage of the generation frequency with control voltage change, and
The frequency of oscillation of phaselocked loop is controlled, and sets consistent with the cycle of oscillation of voltage controlled oscillator for the delay time of time delay module,
The frequency that can control time delay module keeps the fixed frequency of phaselocked loop, reduces disturbance.
Phaselocked loop is fractional frequency-division phase-locked loop in one of the embodiments, is passed through by the frequency elimination coefficient to phaselocked loop
Sigma-delta modulation, so that output clock frequency and input clock frequency ratio are preset value.
Fractional frequency-division phase-locked loop can produce the configurable clock of optional frequency, by the frequency elimination coefficient to phaselocked loop into
Row modulation, so that output clock frequency is accurately preset decimal with input clock frequency ratio, in order to reduce modulation to entire
Phaselocked loop exports the influence of the performance of clock, it will usually be modulated using high-order sigma-delta.
Fig. 2 is the SDM modulator structure block diagram in the present invention in phaselocked loop one embodiment of disturbance suppression, such as Fig. 2 institute
Show, SDM modulator 10 includes integrator 102, the comparator 104 connecting with integrator 102, the digital-to-analogue connecting with comparator 104
Converter 106 and the decimation filter of digital 108 being connect with digital analog converter 106.
Specifically, integrator 102 is connect with comparator 104, and digital analog converter 106 is connect with comparator 104, and three is sequentially
It is arranged in a negative-feedback circulation.Input signal is added with the output of the digital analog converter 106 negated as integrator 102
Input signal.
The input signal of integrator 102 is the ratio of output clock frequency and input clock frequency, the output of integrator 102
Signal is ramp signal, and the slope of ramp signal is directly proportional to the input signal amplitude of integrator 102.
Specifically, integrator 102 is to realize the circuit that integral operation is carried out to input signal, for asking error voltage
With, the frequency of input signal is lower, and amplitude amplification factor is bigger, a low-pass filter is shown as input signal, and it is right
High-pass filtering is then shown as in quantizing noise.
The output of integrator 102 is compared with the reference signal of comparator 104, obtains the binary system output of comparator 104.
Specifically, comparator may be implemented to be compared two or more data item, to determine whether they are equal, or
It determines the size relation between them and puts in order.Comparator 104 is by an analog voltage signal and a reference voltage
The circuit to compare, two-way input are analog signal, and output is then binary signal 0 or 1, when the difference of input voltage increases
Or reduce and sign symbol it is constant when, output keep constant.
The binary system output of comparator 104 is sent into decimation filter of digital 108, digital decimation based on digital analog converter 106
Filter 108 carries out digital decimation to the binary system output of comparator 104, obtains the output of SDM modulator 10.
Specifically, SDM modulator requires good filtering performance and high-speed computation using extraction and filter function is completed
The decimation filter of digital 108 of ability, by the digital method for resampling to every output M data pick-up 1, realization makes to export
Data rate is lower than original over-sampling rate, obtains the output of SDM modulator, and wherein M is integer.
Above-mentioned SDM modulator carries out integrating meter by the ratio of output clock frequency and input clock frequency to input
It calculates, the output signal of integrator is compared with the reference signal of comparator, obtain the binary system output of comparator, number is taken out
It takes filter to carry out digital decimation to the binary system output of comparator, obtains the output of SDM modulator, while generating a certain amount
Change noise, phase adjustment is carried out to reference clock signal and feedback clock signal using quantizing noise, so that reference clock signal
It is consistent with feedback clock signal phase, it eliminates and disturbs and offset quantizing noise.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of phaselocked loop of disturbance suppression characterized by comprising
The first time delay module that input terminal is connect with reference clock signal and SDM modulator, for receiving reference clock signal
With the quantizing noise of SDM modulator output, the quantizing noise carries out phase adjustment to the reference clock signal；
The second time delay module that input terminal is connect with feedback clock signal and SDM modulator, for receiving feedback clock signal
With the quantizing noise of SDM modulator output, the quantizing noise carries out phase adjustment to the feedback clock signal；
The phase frequency detector being connect with first time delay module and second time delay module, for believing the reference clock
Number and the feedback clock signal handled, obtain phase error information, and export and control according to the phase error information
Signal；
The voltage controlled oscillator being connect with the phase frequency detector, for generating output signal according to the control signal；
Connect with the phase frequency detector and SDM modulator connection frequency eliminator, for the output according to the voltage controlled oscillator
Signal generates feedback clock signal.
2. the phaselocked loop of disturbance suppression according to claim 1, which is characterized in that further include and the phase frequency detector
The filter that output end is connected, connect with the input terminal of the voltage controlled oscillator, for being filtered place to the control signal
Reason.
3. the phaselocked loop of disturbance suppression according to claim 1, which is characterized in that the voltage controlled oscillator is also used to basis
The frequency of oscillation of the control signal control phaselocked loop.
4. the phaselocked loop of disturbance suppression according to claim 1, which is characterized in that the divisor factor of the frequency eliminator is by institute
Phaselocked loop is stated to generate after SDM modulators modulate.
5. the phaselocked loop of disturbance suppression according to claim 1, which is characterized in that the SDM modulator passes through sigma-
Delta modulation generates quantizing noise, and carries out phase adjustment to the reference clock signal and the feedback clock signal, so that
Reference clock signal is consistent with feedback clock signal phase.
6. the phaselocked loop of disturbance suppression according to claim 5, which is characterized in that when detecting the voltage controlled oscillator
When output signal and output frequency do not occur the quantizing noise, the reference clock signal and the feedback clock signal
Phase adjustment be consistent.
7. the phaselocked loop of disturbance suppression according to claim 1, which is characterized in that the quantizing noise prolongs with described first
When module and the delay time of the second time delay module there are fixed conversion relationships, first time delay module is to the reference clock
Signal carries out delay process, and second time delay module carries out delay process, the quantizing noise to the feedback clock signal
First time delay module is controlled according to the fixed conversion relationship and the second time delay module carries out the time span of delay process.
8. the phaselocked loop of disturbance suppression according to claim 6, which is characterized in that first time delay module and second prolongs
When module delay time it is consistent with the cycle of oscillation of the voltage controlled oscillator.
9. the phaselocked loop of disturbance suppression according to claim 1, which is characterized in that the phaselocked loop is fractional frequency division locking phase
Ring is modulated by the frequency elimination coefficient to phaselocked loop through sigma-delta, so that output clock frequency and input clock frequency ratio
For preset value.
10. the phaselocked loop of disturbance suppression according to claim 9, which is characterized in that the SDM modulator includes integral
Device, the comparator being connect with the integrator, the digital analog converter being connect with the comparator and with the digital analog converter connect
The decimation filter of digital connect；
The input signal of the integrator is the ratio of the output clock frequency and the input clock frequency, the integrator
Output signal be ramp signal, the slope of the ramp signal and the input signal amplitude of integrator are directly proportional；
The integrator output is compared with the reference signal of the comparator, obtains the binary system output of the comparator；
The binary system output of the comparator is sent into decimation filter of digital based on digital analog converter；
The decimation filter of digital carries out digital decimation to the binary system output of the comparator, obtains the SDM modulator
Output.
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| CN112688565A (en) * | 2019-10-18 | 2021-04-20 | 三垦电气株式会社 | Control device and method of current resonance circuit and current resonance power supply |
| CN113329200A (en) * | 2021-06-07 | 2021-08-31 | 广州市奥威亚电子科技有限公司 | Clock synchronization data transmission device based on coaxial cable |
| CN114401022A (en) * | 2022-01-19 | 2022-04-26 | 深圳清华大学研究院 | Signal processing circuit, chip and receiver |
| CN115378567A (en) * | 2022-08-19 | 2022-11-22 | 深圳市紫光同创电子有限公司 | Clock synchronization circuit, clock synchronization method and electronic equipment |
| CN116886093A (en) * | 2023-08-08 | 2023-10-13 | 深圳扬兴科技有限公司 | Piezoelectric real-time clock oscillator |
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| CN115378567B (en) * | 2022-08-19 | 2023-07-18 | 深圳市紫光同创电子有限公司 | Clock synchronization circuit, clock synchronization method and electronic equipment |
| CN116886093A (en) * | 2023-08-08 | 2023-10-13 | 深圳扬兴科技有限公司 | Piezoelectric real-time clock oscillator |
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