CN112994871A - Cascade multi-channel synchronous output device and method of synchronizer - Google Patents
Cascade multi-channel synchronous output device and method of synchronizer Download PDFInfo
- Publication number
- CN112994871A CN112994871A CN201911214948.6A CN201911214948A CN112994871A CN 112994871 A CN112994871 A CN 112994871A CN 201911214948 A CN201911214948 A CN 201911214948A CN 112994871 A CN112994871 A CN 112994871A
- Authority
- CN
- China
- Prior art keywords
- synchronous
- output
- signal
- signal source
- synchronous machine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0091—Transmitter details
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Numerical Control (AREA)
Abstract
The invention discloses a synchronous machine cascade multichannel synchronous output device and a method thereof, wherein the synchronous machine cascade multichannel synchronous output device comprises: the control module is used for generating a waveform signal; the synchronization module is connected with the control module, comprises at least two cascaded synchronizers and is used for synchronously transmitting the waveform signals; and the output module is connected with the synchronization module, comprises at least two signal source devices and is used for synchronously outputting the waveform signals. According to the cascade multi-channel synchronous output device of the synchronous machine, the multi-stage synchronous machine is cascaded and then connected with the signal source equipment to simultaneously output the preset waveform signals, the problems that in the prior art, the number of channels synchronously output by the multi-signal source equipment is small, the synchronous output precision is low are solved, and the effects of synchronous output of more channels and small synchronous output delay deviation are achieved.
Description
Technical Field
The embodiment of the invention relates to a test measurement technology, in particular to a cascade multi-channel synchronous output device and method of a synchronous machine.
Background
In the high-speed development of the electronic information industry, the requirements of various industries on the test measurement industry are higher and higher. In a large number of test measurement application requirements, how to realize synchronous output of signal sources of up to hundreds of channels is a very special requirement. For example, in the qubit control in the quantum computer, with the increase of the quantum bit number, the requirement on the number of synchronous output channels is greater and greater, for example, in a 72-bit quantum computer experiment, 218 channels are required to synchronously output test excitation signals. At present, no solution with high synchronization precision, and the number of synchronization channels reaching more than 200 channels, even more than 100 channels, has been seen in the market. Although the synchronous output of more signal sources can be realized by expanding the number of interfaces of a single synchronous machine, the 'hundreds of channels of synchronous output' is a rare requirement, and the design of an ultra-large-scale synchronous machine device is a design scheme which is not economic enough.
Disclosure of Invention
The invention provides a cascade multi-channel synchronous output device and method of a synchronizer, which are used for realizing the effects of synchronous output of more channels and low synchronous output delay deviation value.
In a first aspect, an embodiment of the present invention provides a cascade multichannel synchronous output device for a synchronous machine, including:
the control module is used for generating a waveform signal;
the synchronization module is connected with the control module, comprises at least two cascaded synchronizers and is used for synchronously transmitting the waveform signals;
and the output module is connected with the synchronization module, comprises at least two signal source devices and is used for synchronously outputting the waveform signals.
Optionally, the at least two cascaded synchronous machines include a first synchronous machine and at least one second synchronous machine, and the at least one second synchronous machine is connected to the first synchronous machine.
Optionally, the first synchronizer includes 1 to N first signal output ports, and the at least one second synchronizer is connected to the first signal output ports.
Optionally, the number of the second synchronous machines is in the range of 1-N.
Optionally, the at least two cascaded synchronous machines further include at least one third synchronous machine, and the at least one third synchronous machine is connected to the second synchronous machine.
Optionally, the first synchronizer includes 1 to N first signal output ports, each of the at least one second synchronizer includes 1 to Y second signal output ports, and the at least one third synchronizer is connected to the second signal output port of the at least one second synchronizer.
Optionally, the number of the second synchronous machines is in the range of 1-N, and the number of the third synchronous machines is in the range of 1-Y.
Optionally, the control module, the synchronization module, and the output module are connected via a network cable.
Optionally, the control module further generates a calibration signal for determining whether the overall delay deviation of the cascade multichannel synchronous output device of the synchronous machine is smaller than a first preset value.
In a second aspect, an embodiment of the present invention further provides a method for outputting cascade multichannel synchronization of a synchronizer, including:
generating a synchronous test signal and a waveform signal;
calculating the time reference of each signal source device according to the synchronous test signal, and adjusting the synchronization of each signal source device according to the time reference;
judging whether the synchronous output deviation value of each signal source device is smaller than a first threshold value or not; and if so, controlling each signal source device to synchronously output the waveform signal.
Optionally, the calculating a time reference of each signal source device according to the synchronous test signal, and adjusting synchronization of each signal source device according to the time reference includes:
generating a clock signal and a calibration signal according to the synchronous test signal;
and calculating the time reference of each signal source device according to the clock signal and the calibration signal, and adjusting the synchronization of each signal source device according to the time reference.
Optionally, the adjusting synchronization of each signal source device according to the time reference includes:
controlling the inside of each signal source device to calculate the loop time delay of each output channel according to the time reference;
and adjusting the loop time delay of each output channel to be consistent with the time reference, and finishing synchronous calibration.
The embodiment of the invention provides a cascade multi-channel synchronous output device of a synchronous machine, which comprises a control module, a first synchronous output module, a second synchronous output module and a control module, wherein the control module is used for generating a waveform signal; the synchronization module is connected with the control module, comprises at least two cascaded synchronizers and is used for synchronously transmitting the waveform signals; and the output module is connected with the synchronization module, comprises at least two signal source devices and is used for synchronously outputting the waveform signals. The multi-signal source equipment is connected with the multi-signal source equipment after cascade connection through the multi-stage synchronous machine and outputs the preset waveform signal at the same time, so that the problems of small number of channels synchronously output by the multi-signal source equipment and low synchronous output precision in the prior art are solved, and the effects of synchronous output of more channels and small synchronous output delay deviation are realized.
Drawings
Fig. 1 is a schematic block diagram of a cascade multi-channel synchronous output device of a synchronous machine according to a first embodiment of the present invention;
fig. 2 is a connection structure diagram of a cascade multi-channel synchronous output device of a synchronous machine provided in the first embodiment;
fig. 3 is a connection structure diagram of a cascade multi-channel synchronous output device of a synchronous machine according to a second embodiment of the present invention;
fig. 4 is a schematic step diagram of a method for outputting cascade multi-channel synchronization of a synchronizer according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may also include additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, a first synchronous machine may be referred to as a second synchronous machine, and similarly, a second synchronous machine may be referred to as a first synchronous machine, without departing from the scope of the present application. The first and second synchronizers are both synchronizers, but are not the same synchronizer. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Example one
Fig. 1 is a schematic block diagram of a cascade multichannel synchronous output device of a synchronous machine according to an embodiment of the present invention, where the cascade multichannel synchronous output device of the synchronous machine according to the embodiment of the present invention is applicable to a situation where a large number of synchronous output channels are required to be used and a two-stage cascade synchronous machine is used to synchronously output a preset waveform signal, and specifically includes:
and the control module 1 is used for generating a waveform signal. The control module 1 has the function of being responsible for managing and controlling all the synchronization modules 2 and the control module 3. The control module 1 further generates a calibration signal for judging whether the integral time delay deviation of the cascade multichannel synchronous output device of the synchronous machine is smaller than a first preset value.
In this embodiment, the control module 1 includes an upper computer and a network switch, and the upper computer and the network switch perform connection communication through a network cable (the communication mode may also be a communication transmission mode such as USB Hub). The upper computer in this embodiment is preferably a computer host, the computer host may receive a calibration signal generated by a signal source device or a synchronous machine, and notify each component in the synchronous module 2 to perform synchronous calibration, the calibration signal is output to each component of the synchronous module 2 after being shunted by a network switch, and after the calibration is completed, if each synchronous output channel meets a preset first preset value, the first preset value is a delay deviation threshold of synchronous output, generally, the first preset value is obtained from a large amount of experimental data, and a delay deviation value of synchronous output of a multistage cascade synchronous machine is smaller than 45ps-55ps, for example, smaller than 50ps, it is considered that a user requirement can be met, and then the synchronous output of a preset waveform signal may be started.
And the synchronization module 2 is connected with the control module 1 and comprises at least two cascaded synchronizers for synchronously transmitting the waveform signals. The at least two cascaded synchronous machines comprise a first synchronous machine and at least one second synchronous machine, and the at least one second synchronous machine is connected to the first synchronous machine. The first synchronizer includes 1-N first signal output ports, and the at least one second synchronizer is connected to the first signal output ports. The number of the second synchronous machines is in the range of 1-N.
In this embodiment, the synchronization module 2 includes a plurality of 2-level cascaded synchronizers. In a plurality of 2-stage cascaded synchronizers, 1 synchronizer serves as a Master synchronizer, and the other synchronizers serve as Slave synchronizers, because a certain number of synchronizers output ports N are limited, in this embodiment, the synchronizers output port N is taken as 8 as an example for explanation, at this time, the Master synchronizer is connected with at most 8 Slave synchronizers, similarly, the Slave synchronizer is connected with at most 7 signal source output devices, and one output port is connected to the Master synchronizer. Each synchronizer comprises an FPGA chip for receiving signals and processing the signals.
And the output module 3 is connected with the synchronization module 2, and comprises at least two signal source devices for synchronously outputting the waveform signals. The control module 1, the synchronization module 2 and the output module 3 are connected through a network cable.
In this embodiment, the output module 3 includes a plurality of signal source devices, and each signal source device includes 1-X output channels. In this embodiment, the number X of output channels is 8, and at this time, each signal source device may be provided with at most 8 output channels, and may be provided with at least 1 output channel. In this embodiment, except for the connection of the output ports, the computer host branches off a plurality of network cables through the network switch to be respectively connected to the Master synchronizer, each Slave synchronizer and each signal source device.
Referring to fig. 2, fig. 2 is a connection structure diagram of a cascade multi-channel synchronous output device of a synchronizer in the first embodiment, fig. 2 illustrates an example in which 9 synchronizers Z1 and S1-S8 form a 2-stage cascade, and 56 signal source devices a1-a56 and 448 output channels. The computer host is connected to the network switch through a network cable, and the network switch is connected to the Master synchronizer Z1 through a network cable. The Master synchronizer Z1 comprises 8 output ports M1 and M2 … … M8 which are respectively connected to 8 Slave synchronizers, the output port M1 is connected to the Slave synchronizer S1, the output port M2 is connected to the Slave synchronizer S2 … …, the output port M8 is connected to the Slave synchronizer S8. Each Slave synchronous machine also comprises 8 output ports M1 and M2 … … M8. An output port M1 of the Slave synchronous machine S1 is connected to the signal source equipment A1, an output port M2 is connected to the signal source equipment A2 … …, an output port M7 is connected to the signal source equipment A7, and an output port M8 is connected to the Master synchronous machine Z1. Each signal source device is connected with 8 output channels, and a total of 56 signal source devices, namely 448 output channels, are included.
The cascade multichannel synchronous output device of the synchronous machine provided by the embodiment comprises a control module, a first synchronous output module and a second synchronous output module, wherein the control module is used for generating a waveform signal; the synchronization module is connected with the control module, comprises at least two cascaded synchronizers and is used for synchronously transmitting the waveform signals; and the output module is connected with the synchronization module, comprises at least two signal source devices and is used for synchronously outputting the waveform signals. The two-stage synchronous machine is connected with the plurality of signal source devices after being cascaded and outputs the preset waveform signals at the same time, so that the problems of less number of channels synchronously output by the plurality of signal source devices and lower synchronous output precision in the prior art are solved, and the effects of more channels for synchronous output and small synchronous output delay deviation are realized.
Example two
Fig. 3 is a connection structure diagram of a cascade multichannel synchronous output device of a synchronous machine according to the present invention, where the cascade multichannel synchronous output device of a synchronous machine according to the present embodiment is applicable to a situation that a large number of synchronous output channels are required and a three-level cascade synchronous machine is used to synchronously output a preset waveform signal, and specifically includes:
and the control module 1 is used for generating a waveform signal. The control module 1 further generates a calibration signal for judging whether the integral time delay deviation of the cascade multichannel synchronous output device of the synchronous machine is smaller than a first preset value.
In this embodiment, the control module 1 includes an upper computer and a network switch, and the upper computer and the network switch are connected and communicated via a network cable. The upper computer in this embodiment is preferably a host computer, the host computer can produce a calibration signal to notify each component in the synchronization module 2 to perform synchronous calibration, the host computer provides the calibration signal, the calibration signal is shunted by the network switch and then output to each component of the synchronization module 2, after calibration is completed, if each synchronous output channel meets a preset first preset value, the first preset value is a delay deviation threshold of synchronous output, generally, the delay deviation value is obtained from a large amount of experimental data, the delay deviation value of synchronous output of the multistage cascade-connected synchronization machine is smaller than 45ps-55ps, for example, smaller than 50ps, it can be considered that user requirements can be met, and then synchronous output of a preset waveform signal can be started.
And the synchronization module 2 is connected with the control module 1 and comprises at least two cascaded synchronizers for synchronously transmitting the waveform signals. The at least two cascaded synchronous machines comprise a first synchronous machine and at least one second synchronous machine, and the at least one second synchronous machine is connected to the first synchronous machine. The at least two cascaded synchronous machines further comprise at least one third synchronous machine, and the at least one third synchronous machine is connected to the second synchronous machine. The first synchronizer comprises 1-N first signal output ports, each second synchronizer comprises 1-Y second signal output ports, and the at least one third synchronizer is connected to the second signal output ports of the at least one second synchronizer. The number of the second synchronous machines is in the range of 1-N machines, and the number of the third synchronous machines is in the range of 1-Y machines.
In this embodiment, the synchronization module 2 is formed by sequentially connecting a plurality of 3-level cascaded synchronizers. In a plurality of 2-level cascaded synchronizers, 1 synchronizer is used as a Master synchronizer, and the other synchronizers are used as Slave synchronizers. Since there is a certain number of limitations on the output ports N and Y of the 1-stage synchronous machine and the 2-stage synchronous machine, in this embodiment, it is described by taking an example that the output ports N and Y of the 1-stage synchronous machine are both 8, at this time, the number of the 1-stage Slave synchronous machines directly connected to the Master synchronous machine is at most 8, and the remaining Slave synchronous machines connected to the 1-stage Slave synchronous machine are 2-stage synchronous machines and 56.
And the output module 3 is connected with the synchronization module 2, and comprises at least two signal source devices for synchronously outputting the waveform signals. The control module 1, the synchronization module 2 and the output module 3 are connected through a network cable.
In this embodiment, the output module 3 includes a plurality of signal source devices, and each signal source device includes 1-X output channels. In this embodiment, the number X of output channels is 8, and at this time, each signal source device may be provided with at most 8 output channels, and may be provided with at least 1 output channel. In this embodiment, except for the connection of the output ports, the computer host branches off a plurality of network cables through the network switch to be respectively connected to the Master synchronizer, each Slave synchronizer and each signal source device.
Referring to fig. 3, fig. 3 is a connection structure diagram of a cascade multi-channel synchronous output device of a synchronizer in the second embodiment, fig. 3 illustrates an example in which 65 synchronizers Z1 and S1-S64 form 3-stage cascade, and 392 signal source devices a1-a392 and 3136 output channels. The computer host is connected to the network switch through a network cable, and the network switch is connected to the Master synchronizer Z1 through a network cable. The Master synchronizer Z1 comprises 8 output ports M1 and M2 … … M8 which are connected to 8 Slave synchronizers of 1 stage respectively, the output port M1 is connected to the Slave synchronizer S1, the output port M2 is connected to the Slave synchronizer S2 … …, and the output port M8 is connected to the Slave synchronizer S8. Each level 1 Slave synchronous machine also comprises 8 output ports M1 and M2 … … M8. The 2-stage Slave synchronous machines S9-S64 are respectively connected to 8 1-stage Slave synchronous machines. An output port M1 of the 2-stage Slave synchronous machine S9 is connected to the signal source device A1, an output port M2 is connected to the signal source device A2 … …, an output port M7 is connected to the signal source device A7, and an output port M8 is connected to the 1-stage Slave synchronous machine. Each signal source device is connected with 8 output channels, and a total of 392 signal source devices comprise 3136 output channels.
The cascade multichannel synchronous output device of the synchronous machine provided by the embodiment comprises a control module 1, a first synchronous output module and a second synchronous output module, wherein the control module is used for generating a waveform signal; the synchronization module is connected with the control module 1, comprises at least two cascaded synchronizers and is used for synchronously transmitting the waveform signals; and the output module is connected with the synchronization module, comprises at least two signal source devices and is used for synchronously outputting the waveform signals. The three-stage synchronous machine is connected with the plurality of signal source devices after being cascaded and outputs the preset waveform signals at the same time, so that the problems of less number of channels synchronously output by the plurality of signal source devices and lower synchronous output precision in the prior art are solved, and the effects of synchronous output of more channels and small synchronous output delay deviation are realized.
EXAMPLE III
Fig. 4 is a schematic step diagram of a method for synchronous output of cascaded multiple channels of a synchronous machine according to a third embodiment of the present invention, where the method for synchronous output of cascaded multiple channels of a synchronous machine according to the third embodiment is suitable for calibrating a delay offset of a synchronous machine cascaded multiple channel synchronous output device, and specifically includes:
In this embodiment, the synchronous test signal and the waveform signal are both generated by the host computer, the synchronous test signal is a signal for notifying the synchronous machine cascade multi-channel synchronous output device to start the calibration program, and the waveform signal is a signal to be synchronously output. After the computer host generates the synchronous test signal, the synchronous test signal is transmitted to the Master synchronizer through the network cable.
And 200, calculating the time reference of each signal source device according to the synchronous test signal, and adjusting the synchronization of each signal source device according to the time reference.
Wherein, the calculating the time reference of each signal source device according to the synchronous test signal and adjusting the synchronization of each signal source device according to the time reference comprises: generating a clock signal and a calibration signal according to the synchronous test signal; and calculating the time reference of each signal source device according to the clock signal and the calibration signal, and adjusting the synchronization of each signal source device according to the time reference. The adjusting the synchronization of each signal source device according to the time reference comprises: controlling the inside of each signal source device to calculate the loop time delay of each output channel according to the time reference; and adjusting the loop time delay of each output channel to be consistent with the time reference, and finishing synchronous calibration.
In this embodiment, the host computer sends a synchronization test signal to notify the Master synchronizer to start a synchronization calibration process, and the Master synchronizer provides clock signals to all Slave synchronizers and signal source devices, where the clock signals may be provided from the outside or from the device source devices. And all the Slave synchronous machines and the signal source equipment enter a synchronous calibration process, and all the synchronous machines and the signal source equipment start a system timer. In this embodiment, the clock signal may be a sampling clock signal. And randomly selecting one signal source device as a main signal source device, and informing the signal source device by the Master synchronizer to generate a calibration signal and sending the calibration signal to the Master synchronizer. And the Master synchronizer simultaneously sends the calibration signal to all the Slave synchronizers and all the signal source equipment, each signal source equipment receives the calibration signal, accurately calculates the link delay value of the Master signal source equipment- > Master synchronizer- > Slave synchronizers-and the signal source equipment, and records the delay value as the time reference of the AWG. And after all the signal source equipment calculate the time reference of the Master synchronization machine, the Master synchronization machine informs all the signal source equipment to enter an internal multi-channel synchronous calibration mode. And each signal source device calculates and adjusts the loop time delay of each channel internally, so that the loop time delay of each channel is consistent with the time reference of each signal source device. And after the synchronous calibration of the internal multi-channel of all the signal source equipment is finished, ending the test module and switching to a normal working mode to finish the synchronous calibration.
Step 300, judging whether the synchronous output deviation value of each signal source device is smaller than a first threshold value; and if so, controlling each signal source device to synchronously output the waveform signal.
In this embodiment, after the synchronous calibration of each signal source device is completed, it is determined whether the synchronous output deviation value of each signal source device is smaller than a first threshold, which can be obtained through a large amount of experimental data, and generally the first threshold may be 50ps, that is, when the synchronous output deviation value of each signal source device is smaller than 50ps, it is determined that each signal source device satisfies the synchronous output requirement. The error source in the cascade multichannel synchronous output device of the synchronizer and the Master synchronizer are connected with the joint consistency errors and cable errors of a plurality of Slave synchronizers, and the joint consistency errors and cable errors are also from a plurality of Slave synchronizers connected with a plurality of signal source devices. Generally, a wiring error is first defined, including: the error of a plurality of cables is maximum (2 m for customizing the equal delay cable) and is less than 10ps, and the consistency error of the connection of the multi-way connector and the PCB is less than 1.5 ps; the delay error of the internal power circuit of the synchronous machine is 1ps (according to the maximum welding error of 0.2 mm). And secondly, defining a single AWG calibration error of 10ps + 1-stage synchronous machine calibration error of 9 ps. When each signal source device meets the synchronous output requirement, the Master synchronizer can start to transmit the waveform signals and control all the signal source devices to synchronously output the waveform signals.
The method for synchronous output of the cascade multiple channels of the synchronous machine provided by the embodiment comprises the following steps: generating a synchronous test signal and a waveform signal; calculating the time reference of each signal source device according to the synchronous test signal, and adjusting the synchronization of each signal source device according to the time reference; judging whether the synchronous output deviation value of each signal source device is smaller than a first threshold value or not; and if so, controlling each signal source device to synchronously output the waveform signal. By calibrating the multi-level cascade synchronous machine cascade multi-channel synchronous output device, the problems of less number of channels synchronously output by multi-signal source equipment and lower synchronous output precision in the prior art are solved, and the effects of synchronous output of more channels and small synchronous output delay deviation are realized.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (12)
1. A synchronous machine cascade multi-channel synchronous output device is characterized by comprising:
the control module is used for generating a waveform signal;
the synchronization module is connected with the control module, comprises at least two cascaded synchronizers and is used for synchronously transmitting the waveform signals;
and the output module is connected with the synchronization module, comprises at least two signal source devices and is used for synchronously outputting the waveform signals.
2. The synchronous machine cascade multi-channel synchronous output device as claimed in claim 1, wherein the at least two cascaded synchronous machines comprise a first synchronous machine and at least a second synchronous machine, and the at least a second synchronous machine is connected to the first synchronous machine.
3. The synchronous machine-cascaded multi-channel synchronous output device of claim 2, wherein the first synchronous machine comprises 1-N first signal output ports, and the at least one second synchronous machine is connected to the first signal output ports.
4. The synchronous machine cascade multi-channel synchronous output device as claimed in claim 3, wherein the number of the second synchronous machines is in the range of 1-N.
5. The synchronous machine cascaded multi-channel synchronous output device of claim 2, wherein the at least two cascaded synchronous machines further comprise at least one third synchronous machine, the at least one third synchronous machine being connected to the second synchronous machine.
6. The cascade multi-channel synchronous output device of claim 5, wherein the first synchronizer includes 1-N first signal output ports, each of the at least one second synchronizer includes 1-Y second signal output ports, and the at least one third synchronizer is connected to the second signal output ports of the at least one second synchronizer.
7. The synchronous machine cascade multi-channel synchronous output device as claimed in claim 6, wherein the number of the second synchronous machines is in the range of 1-N machines, and the number of the third synchronous machines is in the range of 1-Y machines.
8. The cascade multi-channel synchronous output device of the synchronous machine as claimed in claim 1, wherein the control module, the synchronous module and the output module are connected through network cables.
9. The cascade multi-channel synchronous output device of claim 1, wherein the control module is further configured to generate a calibration signal, and the calibration signal is used to determine whether the overall delay deviation of the cascade multi-channel synchronous output device is smaller than a first preset value.
10. A synchronous machine cascade multi-channel synchronous output method is characterized by comprising the following steps:
generating a synchronous test signal and a waveform signal;
calculating the time reference of each signal source device according to the synchronous test signal, and adjusting the synchronization of each signal source device according to the time reference;
judging whether the synchronous output deviation value of each signal source device is smaller than a first threshold value or not; and if so, controlling each signal source device to synchronously output the waveform signal.
11. The method of claim 10, wherein the calculating a time reference for each signal source device according to the synchronization test signal and adjusting synchronization of each signal source device according to the time reference comprises:
generating a clock signal and a calibration signal according to the synchronous test signal;
and calculating the time reference of each signal source device according to the clock signal and the calibration signal, and adjusting the synchronization of each signal source device according to the time reference.
12. The method of claim 11, wherein the adjusting the synchronization of the signal source devices according to the time reference comprises:
controlling the inside of each signal source device to calculate the loop time delay of each output channel according to the time reference;
and adjusting the loop time delay of each output channel to be consistent with the time reference, and finishing synchronous calibration.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911214948.6A CN112994871A (en) | 2019-12-02 | 2019-12-02 | Cascade multi-channel synchronous output device and method of synchronizer |
| PCT/CN2020/091858 WO2021109486A1 (en) | 2019-12-02 | 2020-05-22 | Synchronous machine cascade-based multi-channel synchronous output apparatus and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911214948.6A CN112994871A (en) | 2019-12-02 | 2019-12-02 | Cascade multi-channel synchronous output device and method of synchronizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112994871A true CN112994871A (en) | 2021-06-18 |
Family
ID=76221490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911214948.6A Pending CN112994871A (en) | 2019-12-02 | 2019-12-02 | Cascade multi-channel synchronous output device and method of synchronizer |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN112994871A (en) |
| WO (1) | WO2021109486A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117278188A (en) * | 2023-11-21 | 2023-12-22 | 深圳市鼎阳科技股份有限公司 | Signal source synchronization system and synchronization method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040263207A1 (en) * | 2003-06-30 | 2004-12-30 | Sun Microsystems, Inc. | Synchronous clocked full-rail differential logic with single-rail logic and shut-off |
| CN101834714A (en) * | 2010-05-10 | 2010-09-15 | 淮阴工学院 | Synchronous dynamic tester capable of cascading with great amount of channels |
| CN101968730A (en) * | 2010-10-27 | 2011-02-09 | 广东威创视讯科技股份有限公司 | Interactive synchronous processing method and system for multiprocessor cascading signal transmission data |
| CN102025480A (en) * | 2009-09-14 | 2011-04-20 | 中兴通讯股份有限公司 | Method and device for realizing boundary clock in cascade base station |
| CN102739202A (en) * | 2012-07-06 | 2012-10-17 | 电子科技大学 | Cascadable multichannel DDS (direct digital synthesizer) signal generator |
| CN106961312A (en) * | 2017-05-06 | 2017-07-18 | 西北工业大学 | A kind of structure of network instrument clock synchronization system and method |
| CN107863967A (en) * | 2017-11-15 | 2018-03-30 | 中国电子科技集团公司第四十研究所 | A kind of multi-channel synchronous output calibrating installation and method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7672805B2 (en) * | 2003-11-26 | 2010-03-02 | Advantest Corporation | Synchronization of modules for analog and mixed signal testing in an open architecture test system |
| CN103888309B (en) * | 2012-12-20 | 2017-09-08 | 中国移动通信集团公司 | Synchronous regime monitoring method and device |
| CN103427977B (en) * | 2013-09-03 | 2016-05-25 | 上海聚星仪器有限公司 | A kind of single channel analog signal of utilizing realizes the method that many device synchronization gather |
| CN105811970B (en) * | 2016-04-21 | 2018-10-23 | 中国工程物理研究院激光聚变研究中心 | A kind of multichannel generating system |
-
2019
- 2019-12-02 CN CN201911214948.6A patent/CN112994871A/en active Pending
-
2020
- 2020-05-22 WO PCT/CN2020/091858 patent/WO2021109486A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040263207A1 (en) * | 2003-06-30 | 2004-12-30 | Sun Microsystems, Inc. | Synchronous clocked full-rail differential logic with single-rail logic and shut-off |
| CN102025480A (en) * | 2009-09-14 | 2011-04-20 | 中兴通讯股份有限公司 | Method and device for realizing boundary clock in cascade base station |
| CN101834714A (en) * | 2010-05-10 | 2010-09-15 | 淮阴工学院 | Synchronous dynamic tester capable of cascading with great amount of channels |
| CN101968730A (en) * | 2010-10-27 | 2011-02-09 | 广东威创视讯科技股份有限公司 | Interactive synchronous processing method and system for multiprocessor cascading signal transmission data |
| CN102739202A (en) * | 2012-07-06 | 2012-10-17 | 电子科技大学 | Cascadable multichannel DDS (direct digital synthesizer) signal generator |
| CN106961312A (en) * | 2017-05-06 | 2017-07-18 | 西北工业大学 | A kind of structure of network instrument clock synchronization system and method |
| CN107863967A (en) * | 2017-11-15 | 2018-03-30 | 中国电子科技集团公司第四十研究所 | A kind of multi-channel synchronous output calibrating installation and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117278188A (en) * | 2023-11-21 | 2023-12-22 | 深圳市鼎阳科技股份有限公司 | Signal source synchronization system and synchronization method thereof |
| CN117278188B (en) * | 2023-11-21 | 2024-02-23 | 深圳市鼎阳科技股份有限公司 | Signal source synchronization system and synchronization method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021109486A1 (en) | 2021-06-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI651941B (en) | Method for testing data packet signal transceiver using coordinated transmitted data packet signal power | |
| CN103020024B (en) | A kind of file layout change-over method | |
| CN111880603B (en) | Multi-chassis feedback result control trigger synchronization method, device, equipment and medium | |
| CN112994817B (en) | System, method and calibration method for realizing synchronization of multiple signal sources based on synchronizer | |
| WO2018090207A1 (en) | Multi-channel correction apparatus, amplitude correction method, phase correction method, transceiving system and base station | |
| US9841487B2 (en) | Calibration board for calibrating signal delays of test channels in an automatic test equipment and timing calibration method thereof | |
| CN112994871A (en) | Cascade multi-channel synchronous output device and method of synchronizer | |
| CN108919105B (en) | Microwave mechanical switch repeatability test method | |
| US20150161075A1 (en) | I2c router system | |
| JP2015226117A (en) | Synchronization control device and synchronization control method | |
| US7876118B2 (en) | Test equipment | |
| EP2367323A1 (en) | Audio signal processor and audio signal processing system | |
| CN106610911B (en) | Master control electronic device and communication method thereof | |
| TWI520052B (en) | Interface switching system and method for switching operation mode | |
| US9960886B2 (en) | Noise detection device | |
| CN213547494U (en) | Time sequence calibration device for multi-channel group | |
| US11392520B1 (en) | Timing adjustment to unused unit-interval on shared data bus | |
| CN113852438A (en) | Clock buckle plate, distributed system and clock synchronization method of distributed system | |
| CN108055100B (en) | Signal synchronization system and delay calibration method and device of synchronization signal | |
| CN104836754A (en) | Method and device for achieving backboard auto-negotiation function by means of high speed Serdes | |
| CN103220121A (en) | Multi-radio system and radio frequency module | |
| CN112596423B (en) | Cluster control method based on spatial light modulator and spatial light modulator | |
| US20050220237A1 (en) | Method and arrangement for sampling | |
| JP7380905B2 (en) | Communications system | |
| CN109391328A (en) | A kind of switching method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210618 |