KR101788256B1 - Digital receiver and method for collecting of streaming data in digital receiver - Google Patents

Abstract

The present invention relates to a digital receiver and a method for collecting streaming data, comprising: a plurality of ADCs for converting analog data to digital data; a collection start trigger connected to at least one ADC and synchronized to a clock; A plurality of signal converters for converting the channel data output from the ADC into phase data and storing the channel data output from the ADC by the ADC, generating a collection completion trigger upon completion of storage, and transmitting the generated collection trigger to the processor, And loading the corresponding phase data from the signal converter.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a digital receiver and a streaming data collecting method.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital receiver and a streaming data collection method thereof, and more particularly, to a digital receiver for synchronizing data between channels divided according to a signal conversion unit in a digital receiver having a plurality of signal conversion units, .

In general, radar is the primary task of tracking as many targets as possible under a given performance and tracking multiple targets using scan unit detection results.

The radar is divided into an airborne detection radar, a sea surface navigation radar, and a battlefield surveillance / control radar according to the target target. The radar is classified into a short distance / long distance and a long distance radar according to the detection distance. (Azimuth, distance) or three-dimensional (azimuth, distance, altitude) radar.

Such a radar requires an analog-to-digital converter (ADC) to convert the analog signal input to the receiver into a digital signal and a digital down-converter (DDC) to reduce the bandwidth of the digital signal to process the received signal Do.

Meanwhile, a digital receiver for signal measurement is a device for digitizing and processing an analog signal, and includes a plurality of ADCs and a plurality of signal converters for processing signals for a plurality of channels. Here, each of the signal converters may be implemented as an FPGA (Field Programmable Gate Array).

In such a digital receiver, a plurality of FPGAs receives a signal collecting instruction from the processor, individually recognizes the collecting instruction, and collects and transmits signals.

When configuring a digital receiver using multiple FPGAs in such a multi-channel environment, it is important to synchronize data between channels divided according to the FPGA.

However, since the conventional digital receiver does not synchronize the clocks used in a plurality of FPGAs with the processor, there is a problem in that the timing of recognizing the acquisition command differs for each FPGA, so that the data between the channels are not synchronized.

In addition, in systems where phase signal processing is important, there is a problem that phase discontinuity occurs due to asynchronous data.

Prior Art 1: Korean Patent Laid-Open No. 10-2009-0116112 (Published November 11, 2009)

It is an object of the present invention to provide a digital receiver and a method of collecting streaming data of the digital receiver that enable synchronization of inter-channel data divided according to a signal conversion unit by a digital receiver including a plurality of signal conversion units.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

According to an aspect of the present invention, there is provided an ADC circuit comprising: a plurality of ADCs for converting analog data into digital data; a collection start trigger connected to at least one ADC and synchronized to a clock; A plurality of signal converters for converting the channel data output from the ADC into phase data and storing the channel data output from the ADC by the ADC, generating a collection completion trigger upon completion of storage, and transmitting the generated collection trigger to the processor, And a processor for loading the corresponding phase data from the signal conversion unit when necessary.

Each of the plurality of signal converters may be implemented as a field-programmable gate array (FPGA).

Wherein the signal conversion unit comprises: a first clock distribution unit that receives an external clock synchronized with the clock of the at least one ADC and generates and distributes a clock used therein; a first clock distribution unit that receives, from the first clock distribution unit, A latch for latching the channel data input from the ADC using a clock distributed from the first clock distributor, a latch for latching the channel data received from the ADC using the clock distributed from the first clock distributor, A converter for converting the data output from the latch unit into phase data based on a collective start trigger transmitted from the control unit and transmitting the data to the buffer, a buffer for storing the phase data transmitted from the converter, And a second clock distributor for generating a clock to be used for loading the phase data stored in the buffer The latch unit, conversion unit and the buffer may be characterized as having a number corresponding to the number of the associated ADC.

The first clock distribution unit may transmit the input clock to the latch unit, the acquisition control unit, and the conversion unit, and may transmit the 'clock / decimation number' clock to the conversion unit.

The acquisition control unit sets a timing schedule of a collection start trigger and a collection completion trigger for phase data collection and synchronizes a collection start trigger and a collection completion trigger to a clock transmitted from the first clock distribution unit according to the set timing schedule Can be generated.

The conversion unit may operate based on a clock transmitted from the first clock distribution unit and a clock having a number of 'clock / decimation'.

The conversion unit includes a digital down-converter (DDC) for down-converting the data output from the latch unit to a digital baseband signal and outputting I-phase data and quadrature-phase data, And FFT means for performing FFT on the / Q data, and phase data generating means for converting the FFT-performed I / Q data at the time of receiving the acquisition start trigger from the acquisition control unit into phase data.

The I / Q data set at the time when the acquisition start trigger of each signal conversion unit is received may be synchronous data.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display, comprising the steps of: (a) converting analog data into digital data by an ADC; (b) latching digital data transmitted from the ADC by a latch, (c) converting the data output from the latch unit into phase data based on the acquisition start trigger transmitted from the acquisition control unit, and storing the phase data; (d) A method for collecting streaming data of a digital receiver is provided that includes transmitting a collection completion trigger to a processor.

The conversion unit may operate based on a clock transmitted from the first clock distribution unit and a clock having a number of 'clock / decimation'.

The step (c) includes the steps of outputting I / Q data by down-converting the data output from the latch unit to a digital baseband signal, performing FFT on the output I / Q data, And converting the FFT-performed I / Q data at the time of receiving the acquisition start trigger to phase data.

The method for collecting streaming data of the digital receiver may further include, after the step (d), a step of loading the stored phase data by the processor.

In addition, the method for collecting streaming data of the digital receiver may further include setting and storing a timing schedule of the acquisition start trigger and the collection completion trigger for the requested phase data acquisition, when the phase data acquisition is requested.

According to the present invention, interchannel data can be synchronized by generating an acquisition start trigger for each signal converter without receiving an acquisition start command from the processor.

In addition, it is possible to collect stable phase data in a digital receiver provided with a plurality of signal converters (FPGAs) in a multi-channel environment.

The effects of the present invention are not limited to the above-mentioned effects, and various effects can be included within the scope of what is well known to a person skilled in the art from the following description.

1 is a block diagram schematically showing a configuration of a digital receiver according to an embodiment of the present invention.
2 is a block diagram schematically showing the configuration of the signal converting unit shown in FIG.
3 is a diagram for explaining a timing schedule for a collection start trigger and a collection completion trigger generation according to the present invention.
4 is a diagram for explaining a streaming data collection method of a digital receiver according to the present invention.
5 is an exemplary diagram for explaining data collected by the signal conversion unit according to the present invention.
6 is an exemplary diagram for explaining data collected by a conventional signal conversion unit.

The foregoing and other objects, features, and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG.

Hereinafter, a digital receiver and a method for collecting streaming data according to the present invention will be described in detail with reference to the accompanying drawings. The embodiments are provided so that those skilled in the art can easily understand the technical spirit of the present invention, and thus the present invention is not limited thereto. In addition, the matters described in the attached drawings may be different from those actually implemented by the schematic drawings to easily describe the embodiments of the present invention.

In the meantime, each constituent unit described below is only an example for implementing the present invention. Thus, in other implementations of the present invention, other components may be used without departing from the spirit and scope of the present invention. In addition, each component may be implemented solely by hardware or software configuration, but may be implemented by a combination of various hardware and software configurations performing the same function. Also, two or more components may be implemented together by one hardware or software.

Also, the expression " comprising " is intended to merely denote that such elements are present as an expression of " open ", and should not be understood to exclude additional elements.

The data received by the following digital receiver may be streaming data.

1 is a block diagram schematically showing a configuration of a digital receiver according to an embodiment of the present invention.

Referring to FIG. 1, a digital receiver 100 includes an ADC unit 110 including N ADCs, M signal converters 120, and a processor 130.

The ADC unit 110 constitutes each channel of N ADCs, and converts the transferred analog signal into a digital signal. That is, the N ADCs individually sample analog signals to output clock and digital data. At this time, data having different delays are output from N channels composed of N ADCs.

For example, ADC1 outputs channel 1 digital data, ADC2 outputs channel 2 digital data, ..., and ADC (N) outputs channel N digital data.

Each signal converting unit 120 is connected to at least one ADC and generates an acquisition start trigger synchronized with an internal clock. The digital data received from the ADC by the acquisition start trigger is converted into phase data and stored. And transmits the generated trigger to the processor 130. [ That is, each signal converting unit 120 outputs channel data transmitted from the ADC unit 110 as I / Q data, converts the streaming I / Q data at the time of receiving the acquisition start trigger into phase data, and stores . At this time, the I / Q data set of each signal converter 120 may be the same data.

The signal conversion unit 120 may be implemented as a field-programmable gate array (FPGA), and the number of the signal conversion units 120 may be less than or equal to the number of ADCs.

The signal conversion unit 120 will be described in detail with reference to FIG.

When the acquisition completion trigger is received from the signal conversion unit 120, the processor 130 reads the phase data according to the necessity of the phase data, or ignores the acquisition completion trigger signal when not required.

The processor 130 may be configured to control the operation of various components of the digital receiver 100 and may include at least one computing device, which may be a general purpose central processing unit (CPU) Suitably implemented programmable device elements (CPLDs, FPGAs), application specific integrated circuits (ASICs), or microcontroller chips.

In each of the configurations of the digital receiver 100 described above, it may be implemented in the form of a software module or a hardware module executed by a processor, or a combination of a software module and a hardware module.

As such, any combination of software modules, hardware modules, or software modules and hardware modules executed by a processor may be implemented in a hardware system (e.g., a computer system).

FIG. 2 is a block diagram schematically showing the configuration of the signal conversion unit shown in FIG. 1, and FIG. 3 is a diagram for explaining a timing schedule for generating a collection start trigger and a collection completion trigger according to the present invention.

2, the signal conversion unit 120 includes a latch unit 121, a first clock distribution unit 122, a second clock distribution unit 123, a collection control unit 124, a conversion unit 125, (128).

Hereinafter, for convenience of description, a case where the signal conversion unit 120 is connected to one ADC will be described.

The latch unit 121 latches the inputted channel data using the clock distributed from the first clock distribution unit 122. [ Here, the clock is a clock commonly used in the signal converter 120, and may be a sampling clock of the ADCs connected to the signal converter 120 or a clock having the same frequency as the clock. For example, when the signal converter 120 is connected to the ADC 1, the clock may be any clock having the same frequency as the clock 1 or the clock 1, which is the sampling clock of the ADC 1.

The first clock distribution unit 122 receives an external clock synchronized with the ADC sampling clock, and generates and distributes a clock commonly used for signal processing in the signal conversion unit 120. Here, the clock input from the outside may be less than or equal to the number of ADCs.

That is, the first clock distribution unit 122 provides the clock received from the outside to the latch unit 121, the acquisition control unit 124, and the conversion unit 125, and generates a clock corresponding to the 'clock / decimation number' And provides it to the conversion unit 125.

For example, when receiving clock 1 from the outside, the first clock distribution unit 122 provides the clock 1 to the latch unit 121, the acquisition control unit 124, and the conversion unit 125, And supplies the generated clock to the conversion unit 125. [ Decimation refers to lowering the sampling rate of a signal. Decimation number is a rate at which the sampling rate is lowered, and may be an integer larger than 1 in general. For example, if the Decimation number is "4" and the ADC sampling rate is "160 MHz", the sampling rate of the baseband signal may be "160 MHz / 4 = 40 MHz".

The second clock distribution unit 123 receives the operation clock of the processor and generates a clock to be used when reading the phase data from the buffer in the signal conversion unit. The number of externally input clocks may vary depending on the number of processors.

The acquisition control unit 124 generates an acquisition start trigger synchronized with the clock transmitted from the first clock distribution unit 122 according to a predetermined timing schedule and transmits the generated acquisition start trigger to the conversion unit 125 and the buffer 128, , A collection completion trigger is generated and transmitted to the processor. That is, the acquisition control unit 124 generates a collection start trigger to collect the phase data from the streaming I / Q data, and transmits it to the conversion unit 125 and the buffer 128. At this time, the collection control unit 124 operates according to the timing schedule determined at the designing time. For example, if a timing schedule is set to generate a collection start trigger every 100 us, the collection control unit 124 generates a collection start trigger every 100 us by the timing schedule.

The acquisition control unit 124 sets the timing schedule of the acquisition start trigger and the acquisition completion trigger for the phase data acquisition when the phase data acquisition is requested and synchronizes the acquisition start trigger and the acquisition completion trigger to the clock according to the set timing schedule . For example, if 1000 phase data collection is requested, a timing schedule is set up to generate a collection start trigger and a collection completion trigger for 1000 phase data collection, and a collection start trigger and collection completion Create a trigger.

The method by which the collection control unit 124 generates the collection start trigger and the collection completion trigger will be described with reference to FIG. At this time, it is assumed that the generation start trigger and the collection completion trigger are generated in synchronization with the falling edge of the clock. Referring to FIG. 3, the acquisition control unit 124 generates a collection start trigger at the falling edge of the clock, such as 'A' according to a predetermined collection start trigger generation schedule, and transmits the collection start trigger to the conversion unit 125 and the buffer 128 . Then, the acquisition control unit 124 generates and outputs a trigger during collection as indicated by the instruction 'B' on the descent of the clock after 'A', and maintains the trigger during collection until the time of collection completion trigger generation. The acquisition control unit 124 generates an acquisition completion trigger and sends it to the processor as indicated by the instruction 'D' in the falling of the clock after 'C' at the time of the end of the acquisition trigger. Then, the acquisition control unit 124 generates a trigger during transmission as indicated by 'E' in the descent of the clock after 'D', and maintains the trigger during transmission. Here, the trigger during collection and the trigger during transmission can be omitted for debugging purposes.

In this manner, the collection control unit 124 generates a collection start trigger synchronized with the clock transmitted from the first clock distribution unit 122 according to a predetermined timing schedule, and transmits it to the conversion unit 125 and the buffer 128, Upon completion, a collection completion trigger is generated and sent to the processor.

When the acquisition start trigger is received from the acquisition control unit 124, the conversion unit 125 converts the data output from the latch unit into phase data and stores the data in the buffer 128. [ At this time, the conversion unit 125 operates based on the clock 1 transmitted from the first clock distribution unit 122 and the clock of 'clock 1 / decimation number'.

The conversion unit 122 includes a digital down-converter (DDC) 126 and a phase data conversion module 127.

The DDC 126 down-converts the data output from the latch unit 121 to a digital baseband signal and outputs I (In-phase) data and Q (Quadrature-phase) data. At this time, the DDC 126 uses a clock and a clock based on the number of decimations transmitted from the first clock distributor 122, that is, a clock / number of decimations.

The phase data conversion module 127 converts the I / Q data output from the DDC 126 into phase data. At this time, the phase data conversion module 127 converts the streaming I / Q data output from the DDC 126 at the time of receiving the acquisition start trigger from the acquisition control unit 124 into phase data, send.

The phase data conversion module 127 includes Fast Fourier Transform (FFT) means and phase data generation means.

The FFT means performs an FFT on the I / Q data output from the DDC 126. That is, the FFT unit performs an FFT on I / Q data at the time of receiving the acquisition start trigger from the acquisition control unit 124 to obtain accurate phase data.

The phase data generating means converts the FFT-performed I / Q data into phase data. At this time, the phase data generating means can convert into phase data using a Cordic algorithm, a lookup table, or the like.

The buffer 128 stores the phase data transmitted from the conversion unit 125. [ The phase data stored in the buffer 128 may be loaded by the processor.

An operation of the digital receiver 100 having M signal converters 120 and having N ADCs and collecting the streaming data will be described with reference to FIG.

FIG. 4 is a diagram for explaining a method of collecting streaming data of a digital receiver according to the present invention, FIG. 5 is an exemplary view for explaining data collected by the signal converter according to the present invention, and FIG. And Fig.

Hereinafter, a case where the signal conversion unit receives two channel data will be described as an example.

Referring to FIG. 4, the N ADCs 110 each sample an analog signal to output channel data. That is, ADC1 outputs channel 1 data, ADC2 outputs channel 2 digital, and ADC (N) outputs channel N data. Here, the channel data may be digital data.

The M signal converters 120a, .., 120m receive channel data from the respective ADCs. Although the M signal conversion units 120 are shown as M, the signal conversion units 120 perform the same operation, and therefore only the operation of the signal conversion unit 120a will be described below for convenience of description .

The signal converter 1 120a includes a latch unit 1 121a including a channel 1 latch unit and a channel 2 latch unit, a first clock distribution unit 1 122a, a collection controller 1 124a, a channel 1 converter 125a- A first buffer 125a including a channel 1 buffer and a channel 2 buffer and a second clock distributor 123a including a channel 1 converter 125a-2 and a channel 2 converter 125a-2.

The first clock distribution unit 122a receives clock 1 from the ADC and supplies clock 1 to the channel 1 latch unit and the channel 2 latch unit, the acquisition control unit 1 124a, the channel 1 conversion unit 125a-1, (125a-2). In addition, the first clock distribution unit 122a generates a clock corresponding to 'clock 1 / decimation number' and transmits it to the channel 1 conversion unit 125a-1 and the channel 2 conversion unit 125a-2. Here, clock 1 may be a clock commonly used by signal converter 1 120a.

The collection controller 1 124a generates a collection start trigger synchronized with the clock 1 transmitted from the first clock distributor 122a according to a predetermined timing schedule and transmits it to the converter 1 125a and the buffer 1 128a .

The channel 1 latch unit latches the channel 1 data based on the clock 1 and transmits it to the channel 1 conversion unit 125a-1. The channel 1 DDC of the channel 1 converter 125a-1 converts the channel 1 data output from the channel 1 latch unit into digital data using the clock transmitted from the first clock distributor 122a and the clock of 'clock / Down-conversion to the baseband signal, and outputs the channel 1 I / Q data.

The channel 1 FFT means performs an FFT on the I / Q data output from the channel 1 DDC.

The channel 1 phase data generating means converts the channel 1 I / Q data at the time of receiving the acquisition start trigger into channel 1 phase data and transmits the data to the channel 1 buffer when the acquisition start trigger is received from the acquisition control unit 1 (124a).

When the storage of the channel 1 phase data is completed according to the preset timing schedule, the acquisition control unit 124a generates an acquisition completion trigger and transmits it to the processor.

The operations of the channel 2 latch unit, the channel 2 DDC, the channel 2 FFT unit, and the channel 2 phase data generation unit of the signal conversion unit 1 120a are the channel 1 latch unit, the channel 1 DDC, the channel 1 FFT unit, And the description thereof will be omitted.

The signal converting unit 120a converts the channel 1 I / Q data into channel 1 phase data and the channel 2 I / Q data into channel 2 phase data. At this time, the channel 1 I / Q data and the channel 2 I / Q data are combined and can be referred to as a signal converting unit 1 I / Q data set.

The signal converter 2 120b, ..., and the signal converter M 120m of the digital receiver 100 are different from each other only in clocks, and are the same as those of the signal converter 1 (120a), and a description thereof will be omitted .

That is, the signal conversion unit 1 (120a) generates a collection start trigger and a collection completion trigger synchronized to clock 1, and the signal conversion unit 2 (120b) generates a collection start trigger and a collection completion trigger synchronized to clock 2. For example, when a timing schedule is set to generate a collection start trigger every 100 us, the time at which the collection control unit 1 124a and the collection control unit 2 120b generate the collection start trigger may be different by the difference between the clock 1 and the clock 2 However, generating a collection start trigger every 100us by the timing schedule is the same.

In conclusion, the signal converting unit 120a converts the I / Q data set of the signal converting unit 1 into the signal converting unit 1 phase data set, and the signal converting unit 2 120b converts the I / Q data set of the signal converting unit 2 The signal conversion section 3 120c converts the signal conversion section 3 I / Q data set into the signal conversion section 3 phase data set. This process is applied to each of the M signal converters. At this time, since the I / Q data set affects the phase with "phase = arctan (I / Q)", the I / Q data sets at the time when the acquisition start trigger of each signal conversion unit 120 is received must be synchronized do.

The I / Q data set at the time when the acquisition start trigger of each signal converter 120 is received will be described with reference to FIG. 5 for synchronization.

Referring to FIG. 5, the FPGA 1 I / Q data set at the rising edge of the "FPGA1 clock / Decimation number" signal after the acquisition start trigger of the signal conversion unit 1 120a is "B" The FPGA2 I / Q data set at the rising edge of the "FPGA2 clock / Decimation number" signal after the acquisition start trigger of 2 is "B" and valid data. Therefore, the I / Q data sets of the signal converter 1 120a are B, C and D in time order and the I / Q data sets of the signal converter 2 are B, C and D at the same time, The I / Q data sets at the time when the acquisition start trigger is received by the B & B, C & C, and D & D are in a synchronized state when the data of the conversion unit 1 120a and the signal conversion unit 2 120b are viewed.

This means that the data as shown in Table 1 is obtained and the data set does not mix depending on when the acquisition start trigger is received.

The digital receiver 100 configured as described above can use the stable phase data because it does not receive the acquisition start command by the processor and the timing schedule for generation of the acquisition start trigger is stored for each signal conversion unit.

However, conventionally, the processor transmits collection instruction examples 1, 2, and 3 to each signal conversion unit, and each signal conversion unit performs signal processing according to the collection instruction examples 1, 2, and 3. Referring to FIG. 6, the "FPGA1 I / Q data set" at the rising edge time of the "FPGA1 clock / Decimation number" signal after the collection instruction examples 1, 2 and 3 is valid data. Similarly, the "FPGA2 I / Q data set" at the rising edge of the "FPGA2 clock / Decimation number" signal of the collection instruction examples 1, 2, and 3 is valid data. The results are shown in Table 2. Referring to Table 2, it can be seen that the start of data at the same point in time is different according to the collection instruction examples 1, 2, and 3.

As a result, since the clock used in the plurality of signal converters is not synchronized with the processor in the conventional digital receiver, the timing of recognizing the acquisition command differs for each signal converter so that the data between the channels are not synchronized.

However, since the present invention does not receive an acquisition start command by a processor and a timing schedule for generation of a collection start trigger is stored for each signal conversion unit, interchannel data can be synchronized.

As such, the specification is not intended to limit the invention to the precise form disclosed. While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims. It is possible to apply a deformation. The scope of the present invention is defined by the appended claims rather than the foregoing description, and all changes or modifications derived from the meaning and scope of the claims and equivalents thereof are deemed to be included in the scope of the present invention. .

100: digital receiver 110: ADC section
120: signal conversion unit 121: latch unit
122: first clock distributor 123: second clock distributor
124: Collection control unit 125:
126: DDC 127: Phase data conversion module
128: buffer 130: processor

Claims (13)

A plurality of ADCs (Analog Digital Converters) for converting analog data into digital data;
And generates an acquisition start trigger synchronized with the clock, which is connected to at least one ADC, converts the channel data output from the ADC by the acquisition start trigger into phase data and stores the same, A plurality of signal converters for transmitting signals to the plurality of signal converters; And
And a processor for receiving the collection completion trigger from the plurality of signal converters and loading the corresponding phase data from the signal converter if necessary,
Wherein the signal conversion unit includes: a first clock distribution unit that receives an external clock synchronized with a clock of the at least one ADC, and generates and distributes a clock used therein;
A collection control unit for generating a collection start trigger and a collection completion trigger synchronized with a clock transmitted from the first clock distribution unit according to a predetermined timing schedule;
A latch for latching channel data input from the ADC using a clock distributed from the first clock distributor;
A conversion unit for converting the data output from the latch unit into phase data based on a collection start trigger transmitted from the collection control unit and transmitting the data to a buffer; Lt; / RTI >
Wherein the first clock distributor transmits the input clock to the latch, the acquisition controller, and the converter, and transmits the clock having the number of clock / decimation to the converter. The method according to claim 1,
Wherein the plurality of signal converters are each implemented as a field-programmable gate array (FPGA). The method according to claim 1,
Wherein the signal conversion unit comprises:
A buffer for storing the phase data transmitted from the conversion unit; And
And a second clock distribution unit for receiving an operation clock of the processor and generating a clock used for loading phase data stored in the buffer,
Wherein the latch unit, the conversion unit, and the buffer have a number corresponding to the number of the connected ADCs. delete The method according to claim 1,
The acquisition control unit sets a timing schedule of a collection start trigger and a collection completion trigger for phase data collection and synchronizes a collection start trigger and a collection completion trigger to a clock transmitted from the first clock distribution unit according to the set timing schedule And outputs the digital signal. The method according to claim 1,
Wherein the converting unit operates based on a clock transmitted from the first clock distribution unit and a clock having a number of clocks / decimation. The method according to claim 1,
The conversion unit may include a digital down-converter (DDC) for down-converting the data output from the latch unit to a digital baseband signal and outputting I (In-phase) / Q (Quadrature-phase) data;
FFT means for performing Fast Fourier Transform (FFT) on I / Q data output from the DDC; And
And phase data generating means for converting the FFT-performed I / Q data at the time of receiving the acquisition start trigger from the acquisition control section into phase data. 8. The method of claim 7,
And the I / Q data set at the time when the acquisition start trigger of each signal conversion unit is received is synchronous data. (a) converting the analog data to digital data by the ADC;
(b) latching the digital data transmitted from the ADC using a clock distributed from the first clock distributor;
(c) converting the data output from the latch unit into phase data and storing the data based on the acquisition start trigger transmitted from the acquisition control unit; And
(d) when the conversion unit has finished storing the phase data, transmitting a collection completion trigger to the processor,
Wherein the converting unit operates based on a clock transmitted from the first clock distributor and a clock having a number of clocks / decimation. delete 10. The method of claim 9,
The step (c)
Outputting I / Q data by down-converting the data output from the latch unit to a digital baseband signal;
Performing an FFT on the output I / Q data; And
And converting the FFT-performed I / Q data at the time of receiving the acquisition start trigger from the acquisition control unit to phase data. 10. The method of claim 9,
After the step (d)
Further comprising the step of the processor loading the stored phase data. 10. The method of claim 9,
Wherein the acquisition control further comprises setting and storing a timing schedule of the acquisition start trigger and the acquisition completion trigger for the requested phase data acquisition when phase data acquisition is requested.

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