CN114374414A - Digital beam forming method for reconfigurable interconnection between beam forming units and array elements - Google Patents
Digital beam forming method for reconfigurable interconnection between beam forming units and array elements Download PDFInfo
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- CN114374414A CN114374414A CN202111662160.9A CN202111662160A CN114374414A CN 114374414 A CN114374414 A CN 114374414A CN 202111662160 A CN202111662160 A CN 202111662160A CN 114374414 A CN114374414 A CN 114374414A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
- H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
- H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
- H04B7/0617—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal for beam forming
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention relates to a digital beam forming method for reconfigurable interconnection between beam forming units and array elements. The beam forming unit comprises an instruction analyzing module, a weight caching module, a beam synchronizing module, a magnitude and phase correcting module, a weight complex multiplication module, a beam synthesizing module and an input/output interface; the reconfigurable digital beam forming method between the array elements adopts the beam forming unit, a digital beam forming system is formed by a plurality of distributed beam forming units, and each beam forming unit supports beam forming through data interconnection between the array elements. The invention skillfully utilizes the array element channel layout, connects adjacent channels through reconfigurable interconnection and completes digital beam forming, supports the minimization of the transmission distance of high-speed digital signals, and reduces the driving capability of the high-speed digital signals, thereby reducing the power consumption of the system.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to a digital beam forming method for reconfigurable interconnection between beam forming units and array elements.
Background
The phased array technology is a technology for realizing electronic scanning beam pointing by controlling the phase of each array antenna, and the phased array beamforming method includes Analog Beamforming (ABF) and Digital Beamforming (DBF) technologies. Compared with analog beam forming, digital beam forming has the advantages of easy realization of multiple beams, low side lobe, convenient channel amplitude and phase error calibration, adaptive interference zero setting and the like, and is the mainstream technical scheme of wireless signal transmission at present.
The principle of digital beamforming is shown in fig. 1 (taking receive digital beamforming as an example). The basic principle is that each channel is digitized, amplitude and phase correction is carried out on each channel in a digital domain, and a weight W representing the beam angle is multiplied in a complex domainnThen, each channel complex multiplication data is added to synthesize one path of beam data.
The mathematical model of digital beamforming is represented as:
where D denotes the final shaped beam, DnFor each channel complex baseband signal, WnA corresponding beam weighting factor for each channel.
In the current design scheme, the ADC/DAC that completes channel digitization is an independent chip, and all beamforming amplitude-phase correction, weight complex multiplication, and multi-channel synthesis are implemented in another beamforming processor chip, such as an FPGA. High-speed signal lines and high-speed connectors are needed from the ADC/DAC to the FPGA, a star connection mode is formed between the N high-speed data channels in one sub-array and the beam forming processor, and the traditional digital beam forming system is structured as shown in FIG. 2. This digital beamforming architecture has the following limitations:
1. high-speed data signals between chips are long in wiring, strong signal driving capability is needed, and extra system power consumption overhead is finally caused.
2. In addition, because a series of problems such as Signal Integrity (SI) and the like are introduced to the high-speed signal lines through connector interconnection, additional equalization and pre-emphasis processing are required to be carried out in the chip to ensure the signal integrity, and the power consumption and the cost of the system are further increased.
3. The FPGA or the special beam forming processor chip has limited processing capacity, each chip can only process beam forming complex multiplication and synthesis operation of limited channels, and when the number of channels of the array surface is large, a plurality of FPGA chips or a plurality of special beam forming processor chips are needed to form a tree-shaped synthesis network, so that the system cost is increased, and the market popularization of the digital phased array is limited.
Disclosure of Invention
Aiming at the problems, the invention discloses a digital beam forming method based on reconfigurable interconnection among array elements.
The technical scheme of the invention is as follows:
one aspect of the present invention provides a beam forming unit, which includes an instruction parsing module, a weight caching module, a beam synchronization module, a magnitude and phase correction module, a weight complex multiplication module, a beam synthesis module, and an input/output interface;
the instruction analysis module is connected with the instruction input port of the upper computer, the amplitude and phase correction module, the weight cache module and the instruction output port of the upper computer;
the weight cache module is connected with the instruction analysis module and the beam synchronization module;
the beam synchronization module is connected with the weight caching module, the weight complex multiplication module and the beam synthesis module;
the amplitude and phase correction module is connected with the unit interface, the weight complex multiplication module and the instruction analysis module;
the weight complex multiplication module is connected with the amplitude and phase correction module, the beam synchronization module and the beam synthesis module;
the beam synthesis module is connected with the preceding-stage beam synthesis input port, the beam synthesis output port of the unit, the weight multiplication module and the beam synchronization module.
Furthermore, the instruction analysis module receives an instruction input by the upper computer, the instruction comprises channel correction data and a beam instruction, the instruction analysis module analyzes a channel correction value according to a known protocol format and outputs the channel correction value to the amplitude-phase correction module, and the beam instruction is analyzed and output to the weight cache module; and the instruction analysis module is used for driving and buffering an instruction input by the upper computer and then directly outputting the instruction to the instruction analysis module of the next-stage beam forming unit.
Furthermore, the weight caching module supports startup initialization to store the weights of all beam point locations at one time, in this way, the weight caching module is a RAM module, a weight lookup table is produced in the RAM module, and the weights of the current beam point locations can be output to the beam synchronization module according to the beam point location index numbers of the beam instructions.
Furthermore, the weight cache module is a module for storing data, and comprises a flash, an RRAM or an MRAM; the instruction analysis module analyzes the continuous beam weight and caches the continuous beam weight in the weight cache module, and the weight cache module is an FIFO mode in the mode and outputs the current beam weight to the beam synchronization module.
Furthermore, the beam synchronization module realizes the synchronization of multi-stage beam synthesis data and marks the current beam weight.
Further, when the beamforming unit receives beamforming:
the weight complex multiplication module for receiving beam forming performs complex multiplication on the received data and the beam weight, inherits the beam synchronization mark and transmits the complex multiplication result and the beam synchronization mark to the beam synthesis module;
and the synchronous synthesis module performs addition synthesis on the complex multiplication result of the unit and the beam synthesis result with the same beam synchronization mark input by the previous stage according to the beam synchronization mark, forms a data frame structure by the inherited beam synchronization mark and the synthesized data and outputs the data frame structure to the beam forming unit of the next stage.
Further, when the beamforming unit transmits beamforming:
for transmitting beam forming, the beam forming module distributes data, namely the input of the weight complex multiplication module of each beam forming unit is the same beam data;
after the data is distributed, transmitting the beam synchronization mark of the beam synchronization module, and outputting the data to the input of the weight multiplication module;
the weight value complex multiplication module performs complex multiplication according to the beam point location weight value and the beam data of the beam synchronization module, and the result is output to the amplitude and phase correction module;
and the amplitude and phase correction module performs channel amplitude and phase correction according to the channel correction value and outputs the channel amplitude and phase correction to a DAC (digital-to-analog converter) of the channel to finish channel digitization.
The invention also provides a reconfigurable digital beam forming method among array elements, which adopts the beam forming unit to form a digital beam forming system by a plurality of distributed beam forming units, and each beam forming unit supports beam forming through data interconnection among the array elements.
The invention has the beneficial effects that:
the invention skillfully utilizes the array element channel layout, connects adjacent channels through reconfigurable interconnection and completes digital beam forming, supports the minimization of the transmission distance of high-speed digital signals, and reduces the driving capability of the high-speed digital signals, thereby reducing the power consumption of the system.
In addition, the invention can reduce the complexity of system board-level wiring and the processing and debugging cost of the subarray component, and simultaneously supports the reconfigurable interconnection of instructions and data among array elements at the array surface level.
Furthermore, each beam forming unit of the invention has small scale, is very convenient to integrate with a front-stage ADC/DAC, and comprises but not limited to chip integration or SIP packaging integration and other modes, thereby reducing the dependence of the system on expensive chips such as large-scale beam forming processors such as FPGA and the like, and reducing the system cost.
Drawings
FIG. 1 is a schematic diagram of a digital beamforming technique;
fig. 2 is a conventional digital beamforming system architecture;
fig. 3 is a diagram of a beam forming unit serial daisy chain connection;
FIG. 4 is a 16 channel receive sub-array;
fig. 5 is a 48-element L-band transmitting sub-array plate.
Detailed Description
Each beam forming unit in the invention comprises an instruction analyzing module, a weight caching module, a beam synchronizing module, a magnitude and phase correcting module, a weight multiplying module, a beam synthesizing module and an input/output interface. The instruction analysis module is connected with the instruction input port of the upper computer, the amplitude-phase correction module, the weight cache module and the instruction output port of the upper computer; the weight cache module is connected with the instruction analysis module and the beam synchronization module; the beam synchronization module is connected with the weight caching module, the weight complex multiplication module and the beam synthesis module; the amplitude and phase correction module is connected with the unit interface, the weight multiplication module and the instruction analysis module; the weight complex multiplication module is connected with the amplitude and phase correction module, the beam synchronization module and the beam synthesis module; the beam synthesis module is connected with the preceding-stage beam synthesis input port, the beam synthesis output port of the unit, the weight multiplication module and the beam synchronization module.
Further, the instruction analysis module receives an instruction input by the upper computer, wherein the instruction comprises channel correction data and a beam instruction, the instruction analysis module analyzes a channel correction value according to a known protocol format and outputs the channel correction value to the amplitude-phase correction module, and the beam instruction is analyzed and output to the weight cache module; the instruction analysis module is used for driving and buffering the instructions of the upper computer and then directly outputting the instructions to the instruction analysis module of the next-stage beam forming module, namely the instructions of the upper computer form serial daisy chain connection among all the beam forming units.
The weight cache module supports startup initialization to store all beam point location weights in one time, in this way, the weight cache module can be a RAM module, a weight lookup table is produced in the RAM, and the current weight of the beam point location can be output to the beam synchronization module according to the beam point location index number of the beam instruction. The weight caching module can also be any module capable of storing and reading out the weight, such as a flash module, an RRAM module, an MRAM module and the like capable of storing data, and the form can be embedded or non-embedded; or the instruction analysis module can analyze continuous beam weight and buffer the continuous beam weight in the weight buffer module, and the weight buffer module is in an FIFO mode in the mode and outputs the current beam weight to the beam synchronization module.
The beam synchronization module realizes the synchronization of multi-stage beam synthesis data, marks the current beam weight, and the marking mode can be but not limited to a timestamp or a beam point index, and avoids the combination of different beam data by a post-stage pipeline synthesis module.
Further, the beamforming unit may be a receive beamforming or a transmit beamforming.
The weight complex multiplication module for receiving beam forming performs complex multiplication on the received data and the beam weight, inherits the beam synchronization mark and transmits the complex multiplication result and the beam synchronization mark to the beam synthesis module; and the synchronous synthesis module performs addition synthesis on the complex multiplication result of the unit and the beam synthesis result with the same beam synchronization mark input by the previous stage according to the beam synchronization mark, forms a data frame structure by the inherited beam synchronization mark and the synthesized data and outputs the data frame structure to the beam forming unit of the next stage. The data frame transmission mode between adjacent beam forming modules includes, but is not limited to, a parallel data interface, a parallel LVDS differential pair, or a serial high-speed interface such as a SERDES interface.
For transmit beamforming, the beamforming module distributes data, that is, the input of the weight multiplication module of each beamforming unit is the same beamforming data. After the data is distributed, transmitting the beam synchronization mark of the beam synchronization module, and outputting the data to the input of the weight multiplication module; the weight value complex multiplication module performs complex multiplication according to the beam point location weight value and the beam data of the beam synchronization module, and the result is output to the amplitude and phase correction module; and the amplitude and phase correction module performs channel amplitude and phase correction according to the channel correction value and outputs the channel amplitude and phase correction to a DAC (digital-to-analog converter) of the channel to finish channel digitization.
In the reconfigurable digital beam forming method based on array elements, a digital beam forming system is composed of N distributed beam forming units, each beam forming unit supports beam forming through data interconnection among the array elements, and a special example is serial daisy chain connection, as shown in fig. 3.
Example 1:
the technical scheme of the invention is concretely described by a 16-channel receiving subarray. A16-channel receiving subarray is composed of 4 receiving channel chips (Rx chips), each Rx chip comprises 4 receiving channels, each receiving channel converts an analog/radio frequency signal into a digital signal by an ADC, and a quadrature I/Q complex signal is generated by digital down-conversion DDC. The two parts are standard receiving circuits and the invention will not be described in detail here.
The upper computer instructions and the beam synthesis results of the 4Rx chips are connected in series by a daisy chain. The upper computer sends the amplitude and phase correction coefficient of each channel through an instruction, the instruction analysis module identifies whether the channel correction coefficient is the channel correction coefficient corresponding to the chip, if the channel correction coefficient is the corresponding channel, the channel correction coefficient is stored, and if the channel correction coefficient is not the corresponding channel, the channel correction coefficient is ignored, so that the distribution of the correction coefficient of each channel is completed in the initial correction stage of starting.
In this embodiment, the beam weight of each channel is sent by the upper computer in real time, each beam hopping interval is 1ms, a weight corresponding to the current beam point location is allocated to each channel through a serial upper computer instruction, the total data volume of the channel weights of each beam point location of 16 channels is 16 × 2 × 16 ═ 512bit, redundant characters such as address resolution and weight synchronization mark are considered, calculation is performed according to 1Kbit, it is assumed that parallel LVDS is used to transmit the upper computer instruction, the LVDS data rate is 500Mbps, 200ns is required for completing allocation of all beam weights, and the allocation time is much shorter than the beam forming multiplication and beam synthesis operation time.
The beam synchronization module marks the current beam point location information, and adds timestamp information to form a data frame header, wherein the frame header can adopt the following frame structure:
| start of frame bit | Time stamp | Beam point location index | Weight coefficient |
| 10000111 | T＝0 | X＝13 Y＝9 | 16b |
The beam synchronization module inputs frame data to the weight multiplication module, the weight multiplication module takes out a weight coefficient from the frame data, the weight coefficient and the channel correction data output by the amplitude and phase correction module are subjected to complex multiplication to obtain channel beam data, and beam synchronization mark information is added to form frame structure data for being added and synthesized with a previous-stage multiplication result.
Since the multi-channel data beam synthesis is synthesized by serial addition, as shown in this embodiment, 16 levels of pipelining are required to complete 16 final beam synthesis, and each beam synthesis addition is added to the complex multiplication result of the same timestamp and the same beam point location in order to ensure the synchronization of beam data among multiple channels.
In the embodiment, a total of 4Rx receiving chips, beam forming data between the chips is transmitted through the high-speed serial SERDES, in one sub-array board, the distance between adjacent Rx chips can be roughly determined by the arrangement of antenna array elements, for example, the vacuum wavelength of a 3GHz signal is 10cm, the distance between the antenna array elements is 5cm in half-wavelength, considering the dielectric constant of the PCB, the length of a high-speed SERDES signal line between two Rx chips is not more than 5cm, power consumption overhead such as equalization pre-emphasis of a SERDES interface can be reduced, and meanwhile, signal integrity is easier to ensure.
From the subarray layout, all upper computer instructions and beam forming input/output are connected with adjacent chips through serial connection, PCB wiring is simpler, and PCB design and debugging difficulty is reduced, as shown in figure 4.
Example 2:
a reconfigurable digital beam forming method between array elements is described by taking a 48-array-element L-band transmitting sub-array plate as an example.
As shown in fig. 5, an L-band transmitting sub-array board is composed of 48 array elements, a DAC of a 2-way integrated digital beam forming unit is a chip 1, and 24 transmitting chips (Tx chips) are used for the sub-array board.
The digital beam forming unit based on the reconfigurable interconnection among the array elements is integrated in each chip, so that the sub-array board is divided into 6 beam distribution areas 2. The former-stage DBF beamforming board transmits beam data to the 6 functional areas through the connector 3 at the middle position of the sub-array board.
One Tx chip of each beam distribution area receives beam data, and beam distribution transmission among 4 chips in the area is completed, as shown by black arrows in each area in the drawing. And each channel of each chip completes complex multiplication and channel correction, and the channel beam forming and transmitting function is completed through transmitting of the DUC and the DAC. This process is the reverse of the 4Rx chip in example 1 and will not be described further herein.
Claims (8)
1. A beamforming unit, characterized by: the system comprises an instruction analysis module, a weight cache module, a beam synchronization module, an amplitude and phase correction module, a weight complex multiplication module, a beam synthesis module and an input/output interface;
the instruction analysis module is connected with the instruction input port of the upper computer, the amplitude and phase correction module, the weight cache module and the instruction output port of the upper computer;
the weight cache module is connected with the instruction analysis module and the beam synchronization module;
the beam synchronization module is connected with the weight caching module, the weight complex multiplication module and the beam synthesis module;
the amplitude and phase correction module is connected with the unit interface, the weight complex multiplication module and the instruction analysis module;
the weight complex multiplication module is connected with the amplitude and phase correction module, the beam synchronization module and the beam synthesis module;
the beam synthesis module is connected with the preceding-stage beam synthesis input port, the beam synthesis output port of the unit, the weight multiplication module and the beam synchronization module.
2. A beamforming unit according to claim 1, wherein:
the instruction analysis module receives an instruction input by the upper computer, the instruction comprises channel correction data and a beam instruction, the instruction analysis module analyzes a channel correction value according to a known protocol format and outputs the channel correction value to the amplitude-phase correction module, and the beam instruction is analyzed and outputs the beam instruction to the weight cache module; and the instruction analysis module is used for driving and buffering an instruction input by the upper computer and then directly outputting the instruction to the instruction analysis module of the next-stage beam forming unit.
3. A beamforming unit according to claim 1, wherein:
the weight cache module supports startup initialization to store all beam point location weights once, in this way, the weight cache module is a RAM module, a weight lookup table is produced in the RAM module, and the weights of the current beam point location can be output to the beam synchronization module according to the beam point location index number of the beam instruction.
4. A beamforming unit according to claim 1, wherein:
the weight cache module is a module for storing data and comprises a flash, an RRAM or an MRAM; the instruction analysis module analyzes the continuous beam weight and caches the continuous beam weight in the weight cache module, and the weight cache module is an FIFO mode in the mode and outputs the current beam weight to the beam synchronization module.
5. A beamforming unit according to claim 1, wherein:
the beam synchronization module realizes the synchronization of multi-stage beam synthesis data and marks the current beam weight.
6. A beamforming unit according to claim 1, wherein:
when the beamforming unit receives beamforming:
the weight complex multiplication module for receiving beam forming performs complex multiplication on the received data and the beam weight, inherits the beam synchronization mark and transmits the complex multiplication result and the beam synchronization mark to the beam synthesis module;
and the synchronous synthesis module performs addition synthesis on the complex multiplication result of the unit and the beam synthesis result with the same beam synchronization mark input by the previous stage according to the beam synchronization mark, forms a data frame structure by the inherited beam synchronization mark and the synthesized data and outputs the data frame structure to the beam forming unit of the next stage.
7. A beamforming unit according to claim 1, wherein:
when the beamforming unit is transmitting beamforming:
for transmitting beam forming, the beam forming module distributes data, namely the input of the weight complex multiplication module of each beam forming unit is the same beam data;
after the data is distributed, transmitting the beam synchronization mark of the beam synchronization module, and outputting the data to the input of the weight multiplication module;
the weight value complex multiplication module performs complex multiplication according to the beam point location weight value and the beam data of the beam synchronization module, and the result is output to the amplitude and phase correction module;
and the amplitude and phase correction module performs channel amplitude and phase correction according to the channel correction value and outputs the channel amplitude and phase correction to a DAC (digital-to-analog converter) of the channel to finish channel digitization.
8. A reconfigurable digital beam forming method between array elements, which adopts a beam forming unit as claimed in any one of claims 1 to 7, and a digital beam forming system is formed by a plurality of distributed beam forming units, and each beam forming unit supports beam forming through data interconnection between array elements.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115664628A (en) * | 2022-10-24 | 2023-01-31 | 中国电子科技集团公司第二十九研究所 | Multi-channel digital synchronous frequency conversion method and system |
| CN116683965A (en) * | 2023-07-20 | 2023-09-01 | 之江实验室 | Digital beam forming device, method and storage medium |
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2021
- 2021-12-31 CN CN202111662160.9A patent/CN114374414A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115664628A (en) * | 2022-10-24 | 2023-01-31 | 中国电子科技集团公司第二十九研究所 | Multi-channel digital synchronous frequency conversion method and system |
| CN116683965A (en) * | 2023-07-20 | 2023-09-01 | 之江实验室 | Digital beam forming device, method and storage medium |
| CN116683965B (en) * | 2023-07-20 | 2023-10-20 | 之江实验室 | Digital beam forming device, method and storage medium |
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