CN101217042A - Clock signal extraction circuit of red light high-definition optical disk - Google Patents
Clock signal extraction circuit of red light high-definition optical disk Download PDFInfo
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Abstract
A clock signal extraction circuit of red light high-definition optical disk comprises a frequency discrimination loop and a phase discrimination loop, wherein the frequency discrimination loop is composed of a frequency discriminator, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency-halving circuit, and is characterized in that the frequency discriminator has the structure that: the output end of the first register is connected with the input end of the second register, the output end of the second register is connected with the input end of the third register, one output end of each of the first register and the second register is connected with the first comparator, the output end of the first comparator is connected with the control end of the second register, the output end of the first pulse width counter is connected with the input end of the first register, the output end of the frame pulse generator is connected with the control end of the third register, the output end of the third register is connected with the input end of an increase-decrease pulse generator, NVD optical disc signals are connected with the input end of the frame pulse generator, and the output end of the increase-decrease pulse generator is the output end of the frequency discriminator. The optical disc signal recovered by the invention has less jitter and better quality.
Description
Technical field
The present invention relates to integrated circuit, the clock signal extracting circuit of especially a kind of high-definition red-laser disc (being designated hereinafter simply as NVD).
Background technology
Along with the arrival in HDTV epoch, CD player also will update thereupon, and the high definition disc player will have great demand owing to the arrival in HDTV epoch.It is predicted, to high definition video disc player in 2010 and CD-ROM drive year an international market demand total amount will be above 5,000 ten thousand, high definition produce market demand summation will reach 20,800,000,000 U.S. dollars, domestic high definition video disc player sales volume will be above 2,000 ten thousand, market scale will reach 20,000,000,000 Renminbi, and the market annual growth will be above 40%.Heavy demand based on market, a large amount of R﹠D works have been carried out both at home and abroad: carried out high-resolution digital optic disk HD-DVD of system and the exploitation of Blu-ray Disc BD Study on Technology abroad, carried out the exploitation of the reinforcement high-density digital optic disk EVD of system Study on Technology at home based on the blue light technology to the CD disc player.But strengthening the high-density digital optic disk EVD of system other high definition disc player of level (comprising the HD digital optic disk HVD of system etc.) releases early, it can only select the compressed encoding of Digital Audio Compression Technology MPEG2, and the physical format aspect is identical with digital video disc DVD.This brings two problems: 1, under the code stream of the resolution of 1920*1080 and 22Mbps, the capacity that Digital Audio Compression Technology MPEG2 compressed encoding needs is 25GB, if in strict accordance with Blu-ray Disc BD quality standard, need the DVD capacity more than at least 5 layers so; 2, the premium of the physical format of digital video disc DVD has no idea to avoid.And external since 2004 just to have carried out the development research of Blu-ray Disc BD compact disk standards headed by the Sony, to have carried out the development research of the high-resolution digital optic disk HD-DVD of system compact disk standards headed by the Toshiba.These two kinds of optical disc standards all are based on the blue light technology, can play the high density compact disc more than 130 minutes high sharpness video programs.But blue-ray disc format is not suitable for the industry development of China, this be because:
1, similar to DVD CD industry development route, its patent all is controlled by abroad, and the CD industry of China is limited by external CD industry.
2, these the two kinds broadcast disc player costs based on blue light technology compact disk standards are too high.Estimate that according to market the price of a blue light player is the 800-1000 dollar.
3, this development course also is unfavorable for the lifting of the existing production technology of China.At present the existing compact disc production line of China all is based on the ruddiness technology but not the blue light technology, and the first-born product technology of dvd pickup that just grown up at present also is based on the ruddiness technology.
Because the existence of above-mentioned existing various problems, the rich meeting of in November, 2004 Wuhan light is done good fortune dawn academician and proposed the change physical format, improves the suggestion of capacity.Through the demonstration of Shanghai CD national center, Shanghai ray machine institute, Wuhan photoelectricity National Laboratory, Chinese Optical Valley, Wuhan Gao Ke group, determine that exploitation has the high-definition red-laser disc of new generation (NVD) of autonomous property right.This project implementation will be set up the independent intellectual property right system of China's high definition video disc player, the track of an overturned cart of optical disc on Intellectual Property Rights Issues before avoiding following, realize China's video disc player industry from " made in China " to " China create " historic leap, utilize existing technology of China and production equipment to greatest extent, realize making transition cheaply, from existing DVD seamless transitions to the high definition Age of Technology.
NVD is the series technique standard that a kind of high density with novelty is stored the high-resolution disc of physical format, file logging form and encoding and decoding technique.Adopt red-light source, realize that capacity of optical storage is not less than 12GB, satisfy the 1920*1080 high definition playing programs time greater than 2 hours, have encrypted antitheft and copyright protection technology, whole cost is low.Adopt and the different modulation code of ruddiness CD in the past the raising code efficiency on the physical format.Adopt and the different Error Correction of Coding of ruddiness CD in the past the raising code efficiency simultaneously.
More deeply comprehensive for research to NVD, be a very important aspect to its pulsewidth The Characteristic Study.The parameter of weighing the pulsewidth characteristic of NVD is exactly its quiver value, and this value is to write the comparative result of clock and the phase place of the data-signal of reading from disc, has reflected imprinting point length and the accuracy of imprinting time.That is to say the key component of NVD pulsewidth characteristic research of having write being extracted into of clock.The signal encoding mode of NVD signal encoding and traditional ruddiness CD---the limited length coding RLL of the distance of swimming (2,10) difference, what the NVD signal adopted is the limited length RLL of the distance of swimming (1,7) coding or RLL (2,7) coding.Extraction and traditional ruddiness CD that the difference of coded system has caused the NVD signal to write clock also exist difference.
Summary of the invention
The objective of the invention is to signal Processing, attempt a kind of clock signal extracting circuit is provided, make it can be applied to high-definition red-laser disc signal Processing of new generation high-definition red-laser disc.
Technical solution of the present invention is as follows:
A kind of clock signal extracting circuit of high-definition red-laser disc, comprise frequency discriminator, the increase output terminal of this frequency discriminator with reduce output terminal and link to each other with the input end of charge pump, the output of this charge pump connects the input end of voltage controlled oscillator through wave filter, the output terminal of this voltage controlled oscillator links to each other with the input end of frequency-halving circuit and an input end of phase detector respectively, another input termination NVD CD signal of this phase detector, the CD signal that the output terminal output of this phase detector recovers, the output terminal clock signal of described frequency-halving circuit, this clock signal is also imported described frequency discriminator simultaneously with the NVD CD signal, the structure that is characterized in described frequency discriminator is that the output terminal of first register links to each other with the input end of second register, the input end of output termination the 3rd register of second register, an output of each of described first register and second register termination first comparer, the output terminal of first comparer links to each other with the control end of second register, the input end of output termination first register of the first pulsewidth counter, the control end of output termination the 3rd register of a frame pulse generator, the input end of the output termination one increase and decrease pulse producer of the 3rd register, the NVD CD signal connects frame pulse generator input end, and the output terminal of this increase and decrease pulse producer is the output terminal of described frequency discriminator.
Described frame pulse generator is made up of the low-pass filter, the second pulsewidth counter and second comparer that connect successively.
Described increase and decrease pulse producer is made of subtracter, down counter, crystal oscillator and multi-way switch, the output terminal of this subtracter connects the control end of down counter and multi-way switch respectively, another input termination crystal oscillator of this down counter, the output termination multi-way switch input end of this down counter.
Described frequency-halving circuit is a d type flip flop, and its annexation is: the D end
End joins, the output terminal of CLK termination voltage controlled oscillator, and the Q end is output terminal, the CD signal that output recovers.
Described phase detector is a d type flip flop or J-K flip flop, and the annexation of this d type flip flop is: D termination NVD CD signal, the clock multiplier signal of the output of CIK termination voltage controlled oscillator, and the CD signal that the output of Q end recovers.
The clock signal extracting circuit of high-definition red-laser disc of the present invention is partly realized Clock Extraction by frequency discrimination, realizes signal extraction by phase demodulation, promptly the phase place of clock signal is revised.The CD signal of recovering is with respect to the signal that reads from CD, and wow and flutter is less, and quality is better.Recovering clock signals circuit of the present invention is simple.
Description of drawings
Fig. 1 is a clock signal extracting circuit structural drawing of the present invention,
Fig. 2 is the frequency discriminator synoptic diagram,
Fig. 3 is the synoptic diagram of frame pulse generator,
Fig. 4 is increase and decrease pulse producer synoptic diagram,
Fig. 5 is the phase-demodulating principle synoptic diagram;
Fig. 6 is the two divided-frequency principle schematic.
Wherein: 1-frequency discriminator, 2-charge pump, 3-loop filter, 4-voltage controlled oscillator, 5-phase detector, 6-frequency-halving circuit, 7-the first counter, 8-the first register, 9-the second register, 10-the three register, 11-the first pulsewidth counter, 12-frame pulse generator, 13-increase and decrease pulse producer, 14-low-pass filter, 15-the second pulsewidth counter, 16-the second comparer, 17-subtracter, 18-multi-way switch, 19-down counter, 20-crystal oscillator.
Embodiment
The present invention is further illustrated below in conjunction with accompanying drawing, but should not limit protection scope of the present invention with this.
See also Fig. 1 earlier, Fig. 1 is a clock signal extracting circuit structural drawing of the present invention, as seen from the figure, the clock signal extracting circuit of high-definition red-laser disc of the present invention, comprise frequency discriminator 1, the increase output terminal of this frequency discriminator 1 with reduce the input end of output terminal and link to each other with charge pump 2, the output of this charge pump 2 connects the input end of voltage controlled oscillator 4 through wave filter 3, the output terminal of this voltage controlled oscillator 4 links to each other with the input end of frequency-halving circuit 6 and an input end of phase detector 5 respectively, another input termination NVD CD signal of this phase detector 5, the CD signal that the output terminal output of this phase detector 5 recovers, the output terminal clock signal of described frequency-halving circuit 6, this clock signal is also imported described frequency discriminator 1 simultaneously with the NVD CD signal, the structure that is characterized in described frequency discriminator 1 as shown in Figure 2, the output terminal of first register 8 links to each other with the input end of second register 9, the input end of output termination the 3rd register 10 of second register 9, an output of each of described first register 8 and second register 9 termination first comparer 7, the output terminal of first comparer 7 links to each other with the control end of second register 9, the input end of output termination first register 8 of the first pulsewidth counter 11, the control end of output termination the 3rd register 10 of a frame pulse generator 12, the input end of the 3rd register 10 output terminations one increase and decrease pulse producer 13, the NVD CD signal connects frame pulse generator 12 input ends, and the output terminal of this increase and decrease pulse producer 13 is the output terminal of described frequency discriminator 1.
Described frame pulse generator 12 is made up of the low-pass filter 14, the second pulsewidth counter 15 and second comparer 16 that connect successively.
Described increase and decrease pulse producer 13 is made of subtracter 17, down counter 19, crystal oscillator 20 and multi-way switch 18, the output terminal of this subtracter 17 connects the control end of down counter 19 and multi-way switch 18 respectively, another input termination crystal oscillator 20 of this down counter 19, output termination multi-way switch 18 input ends of this down counter 19.
The clock signal extracting circuit of high-definition red-laser disc of the present invention is the loop of a band feedback, and the clock signal that extracts is feedback signal.High-definition red-laser disc NVD signal generates by frequency discriminator 1 with the clock signal that extracts increases and reduces pulse signal, drive charge pump circuit 2 and form current impulse, this electric current generates the voltage signal of drive pressure controlled oscillator 4 by loop filter 3, this voltage controlled oscillator 4 is the controlled square-wave signal of generated frequency under the control of voltage signal, this signal is the clock multiplier signal, and this clock multiplier signal just obtains the clock signal of our required extraction through frequency-halving circuit 6.
Because the NVD CD signal is the limited length coding RLL (1 of the distance of swimming, 7) or RLL (2,7) coding, if its clock period is T, the long pulse of its signal is wide so is 8T, and short pulse duration is that (RLL (2 for 2T (RLL (1,7) coding) or 3T, 7) encode), and a 8T signal must be arranged in each frame.Detect in each frame long pulse by the first pulsewidth counter 11, first register 8, second register 9, the 3rd register 10, and it is stored in the 3rd register 10 as the 8T signal.The relation that compares duration t with the clock signal period T ' that extracts of this signal by increase and decrease pulse producer 13: if t-8T ' value is bigger than 0, illustrate that the clock frequency of extracting is too big, these increase and decrease pulse producer 13 output " reducing " pulse signals drive charge pump 2 and reduce output current; If this difference is greater than 0, increase and decrease pulse producer 13 will be exported " increase " pulse signal and drive charge pump 2 increase output currents; If this difference equals 0 just, increase and decrease pulse producer 13 will not have pulse signal output, and charge pump 2 output rated current no longer change.
The structure of described frequency discriminator 1 as shown in Figure 2, the output terminal of first register 8 links to each other with the input end of second register 9, the input end of output termination the 3rd register 10 of second register 9, an output of each of described first register 8 and second register 9 termination first comparer 7, the output terminal of first comparer 7 links to each other with the control end of second register 9, the input end of output termination first register 8 of the first pulsewidth counter 11, the control end of output termination the 3rd register 10 of a frame pulse generator 12, the input end of the 3rd register 10 output terminations one increase and decrease pulse producer 13, the NVD CD signal connects frame pulse generator 12 input ends, and the output terminal of this increase and decrease pulse producer 13 is the output terminal of described frequency discriminator 1.
First register, 8, the second registers, 9, the three registers, 10 equal initializes are 0.The width of each pulse of NVD CD signal of the first pulsewidth counter, 11 metering inputs, and deposit first register 8 in; The value that compares first register 8 and second register 9 at each pulse falling edge by first comparer 7, if the value of first register 8 is greater than the value of second register 9, the value of then upgrading second register 9 is the value of first register 8, otherwise the value of second register 9 is constant;
Described frame pulse generator 12 is made up of the low-pass filter 14, the second pulsewidth counter 15 and second comparer 16 that connect successively as shown in Figure 3.Beginning in each frame signal of NVD CD signal all has a frame synchronizing signal, the short pulse of this signal is less than 2T, obtain pulsewidth greater than the 8T frame synchronizing signal by low-pass filter 14 (cutoff frequency between CD-disc clock signal frequency one times between the twice), can obtain frame pulse signal by this characteristic.The NVD signal is passed through low-pass filter 14, measure the pulse width of signal after the filtering then by the second pulsewidth counter 15, if a certain signal pulse width is greater than 8T, illustrate that this signal is a frame synchronizing signal, this moment second comparer 16 output frame pulse signals 1, otherwise 16 outputs 0 of second comparer.
The value that the signal controlling that the NVD CD signal produces by frame pulse generator 12 is upgraded the 3rd register 10 is the value of second register 9: when frame pulse generator 12 output signals are zero, illustrate that this is not the beginning of a frame, the value of the 3rd register 10 remains unchanged and does not upgrade; Otherwise, illustrate that this is the beginning of a frame, the value of the 3rd register 10 will be updated in second register 9 value and as the duration of long pulse in the middle of this frame.
Increase and decrease pulse producer 13 is exported " increase " and " reducing " signal according to the value of the 3rd register (10).
Increase and decrease pulse producer 13 as shown in Figure 4, described increase and decrease pulse producer 13 is made of subtracter 17, down counter 19, crystal oscillator 20 and multi-way switch 18, the output terminal of this subtracter 17 connects the control end of down counter 19 and multi-way switch 18 respectively, another input termination crystal oscillator 20 of this down counter 19, output termination multi-way switch 18 input ends of this down counter 19.Described increase and decrease pulse producer 13 is a pwm generator essentially, and it modulates the width of output pulse according to the size of input value.Its course of work is: subtracter 17 subtracts each other value t and the 8T ' in the 3rd register 10, and the result who obtains takes absolute value as the initial value of down counter 19.The output signal of crystal oscillator 20 is as the clock signal of down counter 19: pulse of crystal oscillator 20 every outputs, down counter 19 just subtracts one.Output is as the input signal of multi-way switch 18 after the value binaryzation of down counter 19: binaryzation, promptly when the value of down counter 19 greater than zero the time, down counter 19 outputs 1, on the contrary down counter 19 exports 0.Subtracter 17 output results' sign bit is as the control signal of multi-way switch 18 simultaneously.If subtracter 17 obtains negative value (sign bit is 1), illustrating needs to increase oscillation frequency, then controls these multi-way switch 18 " increase " signal output part output down counter 19 two-value signals as pulse-width signal, " reducing " signal output part output 0; Otherwise " reduce " signal output part output down counter 19 two-value signals as pulse-width signal, " increase " signal output part output 0.
The phase detector that is used for non-return-to-zero signal (NRZ signal) that traditional phase detector has Hogge and Alexander to propose.In theory, the process of the phase demodulation rejuvenation of signal just.The present invention utilizes the characteristic of d type flip flop, can simplify phase detector, as shown in Figure 5.Described phase detector 5 is a d type flip flop or J-K flip flop, and the annexation of this d type flip flop is: D termination NVD CD signal, the clock multiplier signal of the output of CIK termination voltage controlled oscillator 4, and the CD signal that the output of Q end recovers.
With the output clock multiplier signal of voltage controlled oscillator 4 input end of clock before two divided-frequency as d type flip flop, promptly NVD clock multiplier signal is imported as the d type flip flop clock, the NVD signal is as the input of d type flip flop D end, in fact, because NVD signal pulsewidth is always 2N times (N is a positive integer) of NVD clock multiplier signal pulsewidth, each pulse of NVD signal can obtain by the sampling of d type flip flop, just there is fixing phase difference value with original signal, we just can hold the NVD CD signal that is restored at Q like this, the CD signal of this recovery is with respect to the signal that reads from CD, wow and flutter is less, be the CD signal that quality is higher than read output signal, finish the function of phase detector 5.
Fig. 6 is the frequency-halving circuit of the classics that adopt of the present invention, promptly the D of d type flip flop end with
End joins, the output terminal of CLK termination voltage controlled oscillator 4, and then the frequency of Q end output is held half of frequency for clock CLK.
Through testing and the analysis showed that, the CD signal of this recovery that the clock signal extracting circuit of high-definition red-laser disc of the present invention obtains is with respect to the signal that reads from CD, and wow and flutter is less, and quality is better.Recovering clock signals circuit of the present invention is simple.
Claims (5)
1. the clock signal extracting circuit of a high-definition red-laser disc, comprise frequency discriminator (1), the output terminal of this frequency discriminator (1) links to each other with the input end of charge pump (2), the output of this charge pump (2) connects the input end of voltage controlled oscillator (4) through wave filter (3), the output terminal of this voltage controlled oscillator (4) links to each other with the input end of frequency-halving circuit (6) and an input end of phase detector (5) respectively, another input termination NVD CD signal of this phase detector (5), the CD signal that the output terminal output of this phase detector (5) recovers, the output terminal clock signal of described frequency-halving circuit (6), this clock signal is also imported described frequency discriminator (1) simultaneously with the NVD CD signal, the structure that it is characterized in that described frequency discriminator (1) is: the output terminal of first register (8) links to each other with the input end of second register (9), the input end of output termination the 3rd register (10) of second register (9), an output of each of described first register (8) and second register (9) termination first comparer (7), the output terminal of first comparer (7) links to each other with the control end of second register (9), the input end of output termination first register (8) of the first pulsewidth counter (11), the control end of output termination the 3rd register (10) of frame pulse generator (12), the input end of the 3rd register (10) output termination one increase and decrease pulse producer (13), the NVD CD signal connects frame pulse generator (12) input end, and the output terminal of this increase and decrease pulse producer (13) is the output terminal of described frequency discriminator (1).
2. the clock signal extracting circuit of high-definition red-laser disc according to claim 1 is characterized in that described frame pulse generator (12) is made up of the low-pass filter (14), the second pulsewidth counter (15) and second comparer (16) that connect successively.
3. the clock signal extracting circuit of high-definition red-laser disc according to claim 1, it is characterized in that described increase and decrease pulse producer (13) is made of subtracter (17), down counter (19), crystal oscillator (20) and multi-way switch (18), the output terminal of this subtracter (17) connects the control end of down counter (19) and multi-way switch (18) respectively, another input termination crystal oscillator (20) of this down counter (19), output termination multi-way switch (18) input end of this down counter (19).
4. the clock signal extracting circuit of high-definition red-laser disc according to claim 1 is characterized in that described frequency-halving circuit (6) is a d type flip flop, and its annexation is: its D end with
End joins, the output terminal of CLK termination voltage controlled oscillator (4), and the Q end is output terminal, clock signal.
5. the clock signal extracting circuit of high-definition red-laser disc according to claim 1, it is characterized in that described phase detector (5) is a d type flip flop or J-K flip flop, the annexation of this d type flip flop is: D termination NVD CD signal, the clock multiplier signal of CIK termination voltage controlled oscillator (4) output, and the CD signal that the output of Q end recovers.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100328044A CN101217042B (en) | 2008-01-18 | 2008-01-18 | Clock signal extraction circuit of red light high-definition optical disk |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100328044A CN101217042B (en) | 2008-01-18 | 2008-01-18 | Clock signal extraction circuit of red light high-definition optical disk |
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| CN101217042A true CN101217042A (en) | 2008-07-09 |
| CN101217042B CN101217042B (en) | 2010-06-02 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315927A (en) * | 2011-06-30 | 2012-01-11 | 大唐移动通信设备有限公司 | Clock synchronization device and method |
| CN103095622A (en) * | 2011-11-01 | 2013-05-08 | 上海华虹集成电路有限责任公司 | Binary phase shift keying (BPSK) signal recovery circuit suitable for ISO14443 protocol |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1853222A (en) * | 2003-09-19 | 2006-10-25 | 株式会社理光 | Wobble signal demodulating method, wobble signal demodulating circuit, and optical disk device |
| CN1961482A (en) * | 2004-05-26 | 2007-05-09 | 罗姆股份有限公司 | System clock generator circuit |
| JP2006134530A (en) * | 2004-11-09 | 2006-05-25 | Sanyo Electric Co Ltd | Optical disk device and optical disk evaluation method |
-
2008
- 2008-01-18 CN CN2008100328044A patent/CN101217042B/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315927A (en) * | 2011-06-30 | 2012-01-11 | 大唐移动通信设备有限公司 | Clock synchronization device and method |
| CN103095622A (en) * | 2011-11-01 | 2013-05-08 | 上海华虹集成电路有限责任公司 | Binary phase shift keying (BPSK) signal recovery circuit suitable for ISO14443 protocol |
| CN103095622B (en) * | 2011-11-01 | 2016-12-28 | 上海华虹集成电路有限责任公司 | A kind of bpsk signal restoring circuit being applicable to ISO14443 agreement |
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| CN101217042B (en) | 2010-06-02 |
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