CN201146036Y - The clock signal extraction circuit of red light high-definition disc - Google Patents

Abstract

A clock signal extraction circuit for a red-light high-definition optical disc, comprising a frequency discrimination and phase discrimination dual loop, wherein the frequency discrimination loop is composed of a frequency discriminator, a charge pump, a low-pass filter, a voltage-controlled oscillator and a two-frequency division circuit, and is characterized in that the structure of the frequency discriminator is: the output end of the first register is connected to the input end of the second register, the output end of the second register is connected to the input end of the third register, one output end of each of the first register and the second register is connected to the first comparator, the output end of the first comparator is connected to the control end of the second register, the output end of the first pulse width counter is connected to the input end of the first register, the output end of the frame pulse generator is connected to the control end of the third register, the output end of the third register is connected to the input end of an increase-decrease pulse generator, the NVD optical disc signal is connected to the input end of the frame pulse generator, and the output end of the increase-decrease pulse generator is the output end of the frequency discriminator. The optical disc signal restored by the utility model has less jitter and better quality.

Description

The clock signal extraction circuit of red light high-definition disc

technical field

The utility model relates to an integrated circuit, in particular to a clock signal extraction circuit of a red light high-definition disc (hereinafter referred to as NVD).

Background technique

With the advent of the era of high-definition television, disc players will also be updated accordingly, and high-definition disc players will have a huge market demand due to the advent of the era of high-definition television. It is predicted that by 2010, the total annual international market demand for high-definition video disc players and optical drives will exceed 50 million units, the total market demand for high-definition products will reach 20.8 billion US dollars, the domestic sales of high-definition video disc players will exceed 20 million units, and the market size will reach 200 million. billion yuan, and the annual growth rate of the market will exceed 40%. Based on the large demand of the market, a lot of research and development work on optical disc players has been carried out at home and abroad: the research and development of high-resolution digital video disc system HD-DVD and Blu-ray disc BD technology based on Blu-ray technology have been carried out abroad, and the intensive high-end technology has been carried out domestically. Research and development of density digital video disk system EVD technology. However, high-definition disc players (including high-definition digital video disc system HVD, etc.) that strengthen the high-density digital video disc system EVD level were launched earlier, and it can only choose the compression coding of the digital audio compression technology MPEG2, and the physical format is the same as the digital versatile disc DVD . This brings two problems: 1. Under the resolution of 1920*1080 and the code stream of 22Mbps, the digital audio compression technology MPEG2 compression encoding requires a capacity of 25GB. If the quality standard of Blu-ray disc BD is strictly followed, at least 5 layers are required 2. There is no way to avoid the royalties of the physical format of digital versatile disc DVD. Since 2004, foreign countries have carried out research on the development and research of Blu-ray disc BD disc standards led by Sony Corporation, and carried out research on the development and research of high-resolution digital video disc system HD-DVD disc standards led by Toshiba Corporation. Both disc technology standards are high-density discs based on Blu-ray technology that can play more than 130 minutes of high-definition video programs. But the Blu-ray disc format is not suitable for the industrial development of our country, because:

1. Similar to the development path of the DVD disc industry, its patents are all controlled by foreign countries, and my country's disc industry is subject to foreign disc industries.

2. The cost of these two disc players based on the Blu-ray technology disc standard is too high. According to market estimates, the price of a Blu-ray player is 800-1000 US dollars.

3. This development route is also not conducive to the improvement of my country's existing production technology. At present, my country's existing optical disc production lines are based on red light technology rather than blue light technology, and the newly developed DVD optical head production technology is also based on red light technology.

Due to the existence of the above-mentioned existing problems, Academician Qian Fuxi at the Wuhan Optical Expo in November 2004 proposed to change the physical format and increase the capacity. After the demonstration of Shanghai Optical Disc National Center, Shanghai Institute of Optics and Mechanics, Wuhan National Laboratory of Optoelectronics, and Wuhan China Optics Valley Hi-Tech Group, it is determined to develop a new generation of red light high-definition optical disc (NVD) with independent property rights. The implementation of this project will establish the independent intellectual property system of my country's high-definition video disc players, avoid repeating the mistakes of previous optical disc technology on intellectual property issues, and realize the historic leap of my country's video disc player industry from "Made in China" to "Created in China". The use of my country's existing technology and production equipment to achieve low-cost manufacturing transformation, seamless transition from the existing DVD to the era of high-definition technology.

NVD is a series of technical specifications for high-definition optical discs with innovative high-density storage physical format, file recording format and codec technology. Red light source is used to achieve a CD storage capacity of not less than 12GB, and the playback time of 1920*1080 high-definition programs is more than 2 hours. It has encryption anti-theft and copyright protection technology, and the overall cost is low. The physical format adopts a modulation code different from that of the previous red-ray discs to improve the coding efficiency. At the same time, it adopts an error correction code different from that of the previous red-ray discs to improve the coding efficiency.

In order to study NVD more deeply and comprehensively, the study of its pulse width characteristics is a very important aspect. The parameter to measure the pulse width characteristics of NVD is its jitter value, which is the comparison result of the write clock and the phase of the data signal read from the disc, reflecting the accuracy of the recording point length and recording time. That is to say, the extraction of write clock has become a key part of the study of NVD pulse width characteristics. NVD signal encoding is different from the signal encoding method of traditional red-ray discs - run-length limited length encoding RLL (2, 10). NVD signals use run-length limited length RLL (1, 7) encoding or RLL (2, 7) coding. The difference in the encoding method causes the difference between the extraction of the writing clock of the NVD signal and that of the traditional red optical disc.

Contents of the invention

The purpose of this utility model is to provide a clock signal extraction circuit of a red light high-definition disc, which can be applied to the signal processing of a new generation of red light high-definition discs. Smaller, better quality features.

The technical solution of the utility model is as follows:

A clock signal extraction circuit for a red light high-definition disc, including a frequency discriminator, the increasing output terminal and the decreasing output terminal of the frequency discriminator are connected to the input terminal of a charge pump, and the output of the charge pump is connected to a voltage-controlled oscillation through a filter The input terminal of the voltage controlled oscillator, the output terminal of the voltage controlled oscillator is connected with the input terminal of the two frequency division circuit and an input terminal of the phase detector respectively, and the other input terminal of the phase detector is connected with the NVD disc signal, and the phase detector The output end of the output terminal outputs the recovered disc signal, and the output end of the two-frequency division circuit outputs a clock signal, and the clock signal is also input into the discriminator simultaneously with the NVD disc signal, which is characterized in that the discriminator The structure is that the output terminal of the first register is connected with the input terminal of the second register, the output terminal of the second register is connected with the input terminal of the third register, and each output terminal of the first register and the second register is connected with the first comparison device, the output terminal of the first comparator is connected with the control terminal of the second register, the output terminal of the first pulse width counter is connected with the input terminal of the first register, the output terminal of a frame pulse generator is connected with the control terminal of the third register, The output end of the third register is connected to the input end of an increase/decrease pulse generator, the NVD disc signal is connected to the input end of the frame pulse generator, and the output end of the increase/decrease pulse generator is the output end of the frequency discriminator.

The frame pulse generator is composed of a low-pass filter, a second pulse width counter and a second comparator connected in sequence.

Described increase-decrease pulse generator is made of subtracter, subtraction counter, product shaker and multi-way switch, and the output end of this subtractor is respectively connected the control terminal of subtraction counter and multi-way switch, and the other input end of this subtraction counter is connected A crystal oscillator, the output terminal of the subtraction counter is connected to the input terminal of the multi-way switch.

The two-frequency division circuit is a D flip-flop, and its connection relationship is: the D terminal is connected to the Q terminal, the CLK terminal is connected to the output terminal of the voltage-controlled oscillator, and the Q terminal is the output terminal, which outputs the recovered optical disc signal.

The phase detector is a D flip-flop or a J-K flip-flop, and the connection relationship of the D flip-flop is: the D terminal is connected to the NVD disc signal, the CIK terminal is connected to the output clock multiplication signal of the voltage-controlled oscillator, and the Q terminal Outputs the recovered disc signal.

The clock signal extraction circuit of the red-light high-definition optical disc of the utility model realizes clock extraction through the frequency discrimination part, and realizes signal extraction through phase discrimination, that is, corrects the phase of the clock signal. The recovered disc signal has less jitter and better quality than the signal read from the disc. The clock signal recovery circuit of the utility model is simple and easy to operate.

Description of drawings

Fig. 1 is the utility model clock signal extracting circuit structural diagram,

Figure 2 is a schematic diagram of a frequency discriminator,

Figure 3 is a schematic diagram of a frame pulse generator,

Figure 4 is a schematic diagram of the increase and decrease pulse generator,

Fig. 5 is a schematic diagram of phase detection principle;

Fig. 6 is a schematic diagram of the principle of frequency division by two.

Among them: 1-Frequency discriminator, 2-Charge pump, 3-Loop filter, 4-Voltage controlled oscillator, 5-Phase detector, 6-12 frequency division circuit, 7-First counter, 8-First Register, 9-second register, 10-third register, 11-first pulse width counter, 12-frame pulse generator, 13-increase and decrease pulse generator, 14-low pass filter, 15-second pulse width Counter, 16-second comparator, 17-subtractor, 18-multiplexer, 19-subtraction counter, 20-crystal oscillator.

Detailed ways

The utility model will be further described below in conjunction with the accompanying drawings, but the protection scope of the utility model should not be limited with this.

First please refer to Fig. 1, Fig. 1 is the structural diagram of the clock signal extraction circuit of the present utility model, as can be seen from the figure, the clock signal extraction circuit of the red light high-definition disc of the present utility model includes a frequency discriminator 1, and the increased output of the frequency discriminator 1 end and reduce the output end are connected to the input end of the charge pump 2, the output of the charge pump 2 is connected to the input end of the voltage-controlled oscillator 4 through the filter 3, and the output end of the voltage-controlled oscillator 4 is respectively connected to the two frequency division circuit The input end of 6 is connected with an input end of phase detector 5, and the other input end of this phase detector 5 is connected with NVD optical disc signal, and the output end of this phase detector 5 outputs the optical disc signal that restores, and described two frequency division The output terminal output clock signal of circuit 6, this clock signal also inputs described frequency discriminator 1 simultaneously with NVD disc signal, it is characterized in that the structure of described frequency discriminator 1 is as shown in Figure 2, the first register 8 The output terminal is connected to the input terminal of the second register 9, the output terminal of the second register 9 is connected to the input terminal of the third register 10, and each output terminal of the first register 8 and the second register 9 is connected to the first comparator 7. The output terminal of the first comparator 7 is connected to the control terminal of the second register 9, the output terminal of the first pulse width counter 11 is connected to the input terminal of the first register 8, and the output terminal of a frame pulse generator 12 is connected to the third The control terminal of the register 10, the output terminal of the third register 10 is connected to the input terminal of an increase and decrease pulse generator 13, and the NVD disc signal is connected to the input terminal of the frame pulse generator 12, and the output terminal of the increase and decrease pulse generator 13 is the above-mentioned The output of discriminator 1.

The frame pulse generator 12 is composed of a low-pass filter 14 , a second pulse width counter 15 and a second comparator 16 connected in sequence.

Described increase and decrease pulse generator 13 is made of subtractor 17, subtraction counter 19, crystal oscillator 20 and multi-way switch 18, and the output end of this subtractor 17 is respectively connected the control end of subtraction counter 19 and multi-way switch 18, and this subtraction The other input terminal of the counter 19 is connected to the crystal oscillator 20 , and the output terminal of the subtraction counter 19 is connected to the input terminal of the multi-way switch 18 .

The clock signal extracting circuit of the red-light high-definition disc of the utility model is a loop with feedback, and the extracted clock signal is the feedback signal. The NVD signal of the red light high-definition disc and the extracted clock signal generate increasing and decreasing pulse signals through the frequency discriminator 1, and drive the charge pump circuit 2 to form a current pulse, and the current is generated through the loop filter 3 to drive the voltage-controlled oscillator 4 Voltage signal, the voltage-controlled oscillator 4 generates a frequency-controlled square wave signal under the control of the voltage signal, this signal is the clock frequency multiplication signal, the clock frequency multiplication signal passes through the two frequency division circuit 6 to obtain what we need to extract the clock signal.

Since the NVD disc signal is run-length limited-length coded RLL (1, 7) or RLL (2, 7) coded, if its clock period is T, the longest pulse width of its signal is 8T, and the shortest pulse width is 2T ( RLL (1, 7) encoding) or 3T (RLL (2, 7) encoding), and there must be an 8T signal in each frame. The longest pulse in each frame is detected by the first pulse width counter 11 , the first register 8 , the second register 9 , and the third register 10 , and stored in the third register 10 as an 8T signal. The relationship between the duration t of this signal and the extracted clock signal cycle T' is compared by the increase and decrease pulse generator 13: if the t-8T ' value is larger than 0, it indicates that the extracted clock frequency is too large, and the increase and decrease pulse generator 13 Output "decrease" pulse signal to drive charge pump 2 to reduce the output current; if the difference is greater than 0, the increase and decrease pulse generator 13 will output "increase" pulse signal to drive charge pump 2 to increase the output current; if the If the difference is exactly equal to 0, the increase/decrease pulse generator 13 will have no pulse signal output, and the output rated current of the charge pump 2 will not change.

The structure of described frequency discriminator 1 is as shown in Figure 2, and the output end of the first register 8 is connected with the input end of the second register 9, and the output end of the second register 9 is connected with the input end of the third register 10, described Each output terminal of the first register 8 and the second register 9 is connected to the first comparator 7, the output terminal of the first comparator 7 is connected to the control terminal of the second register 9, and the output terminal of the first pulse width counter 11 is connected to The input terminal of the first register 8, the output terminal of a frame pulse generator 12 is connected to the control terminal of the third register 10, the output terminal of the third register 10 is connected to the input terminal of an increase and decrease pulse generator 13, and the NVD disc signal is connected to the frame pulse The input terminal of the generator 12, the output terminal of the increase and decrease pulse generator 13 is the output terminal of the frequency discriminator 1 described above.

The initial value of the first register 8 , the second register 9 and the third register 10 is 0. The first pulse width counter 11 measures the width of each pulse of the NVD disc signal input, and is stored in the first register 8; compares the first register 8 and the second register 9 by the first comparator 7 at the falling edge of each pulse. Value, if the value of the first register 8 is greater than the value of the second register 9, then update the value of the second register 9 to be the value of the first register 8, otherwise the value of the second register 9 remains unchanged;

The frame pulse generator 12 is shown in FIG. 3 and consists of a low-pass filter 14 , a second pulse width counter 15 and a second comparator 16 connected in sequence. There is a frame synchronization signal at the beginning of each frame signal of the NVD optical disc signal, the shortest pulse of this signal is less than 2T, and the pulse width is obtained by the low-pass filter 14 (the cut-off frequency is between one and two times the frequency of the optical disc clock signal) Greater than 8T frame synchronization signal, frame pulse signal can be obtained through this feature. The NVD signal is passed through the low-pass filter 14, and then the pulse width of the filtered signal is measured by the second pulse width counter 15. If the pulse width of a certain signal is greater than 8T, it indicates that the signal is a frame synchronization signal. At this time, the second comparator 16 The frame pulse signal 1 is output, otherwise the second comparator 16 outputs 0.

The NVD disc signal is controlled by the signal generated by the frame pulse generator 12 to update the value of the third register 10 to the value of the second register 9: when the frame pulse generator 12 output signal is zero, it means that this is not the beginning of a frame, the third The value of the register 10 remains unchanged and is not updated; on the contrary, it indicates that this is the beginning of a frame, and the value of the third register 10 will be updated to the value in the second register 9 as the duration of the longest pulse in this frame.

The increase and decrease pulse generator 13 outputs "increase" and "decrease" signals according to the value of the third register (10).

Increase-decrease pulse generator 13 as shown in Figure 4, described increase-decrease pulse generator 13 is made up of subtractor 17, subtraction counter 19, product vibration 20 and multi-way switch 18, and the output terminal of this subtractor 17 is connected subtraction method respectively. The control end of the counter 19 and the multi-way switch 18 , the other input end of the subtraction counter 19 is connected to the crystal oscillator 20 , and the output end of the down-counter 19 is connected to the input end of the multi-way switch 18 . The increase and decrease pulse generator 13 is fundamentally a pulse width modulation generator, which modulates the width of the output pulse according to the magnitude of the input value. Its working process is: the subtractor 17 subtracts the value t in the third register 10 and 8T', and the result obtained takes the absolute value as the initial value of the subtracting counter 19. The output signal of the crystal oscillator 20 is used as the clock signal of the down counter 19: every time the crystal oscillator 20 outputs a pulse, the down counter 19 will decrease by one. The value binarization of the subtraction counter 19 is output as the input signal of the multiplexer 18: binarization, that is, when the value of the subtraction counter 19 was greater than zero, the output of the subtraction counter 19 was 1, otherwise the output of the subtraction counter 19 was 0. At the same time, the subtractor 17 outputs the sign bit of the result as the control signal of the multiplexer 18 . If the subtractor 17 obtains a negative value (the sign bit is 1), it indicates that the oscillation frequency needs to be increased, and then the multiplexer 18 is controlled to "increase" the signal output terminal to output the binary signal of the subtraction counter 19 as a pulse width modulation signal, " The output terminal of the "decrease" signal outputs 0; otherwise, the output terminal of the "decrease" signal outputs the binarized signal of the subtraction counter 19 as a pulse width modulation signal, and the output terminal of the "increase" signal outputs 0.

The traditional phase detector includes the phase detector for non-return-to-zero signal (NRZ signal) proposed by Hogge and Alexander. Theoretically speaking, the phase identification process is also the signal recovery process. The utility model utilizes the characteristics of the D flip-flop to simplify the phase detector, as shown in FIG. 5 . Described phase detector 5 is a D flip-flop or J-K flip-flop, and the connection relation of this D flip-flop is: D terminal connects NVD disc signal, CIK terminal connects the clock multiplication signal of the output of voltage-controlled oscillator 4, and The Q terminal outputs the recovered disc signal.

The output clock frequency multiplication signal of the voltage-controlled oscillator 4 is used as the clock input terminal of the D flip-flop before the frequency division by two, that is, the NVD clock frequency multiplication signal is used as the D flip-flop clock input, and the NVD signal is used as the D flip-flop D terminal input, In fact, since the pulse width of the NVD signal is always 2N times the pulse width of the NVD clock multiplier signal (N is a positive integer), each pulse of the NVD signal can be obtained by sampling the D flip-flop, but there is a fixed difference with the original signal. The phase difference value, so that we can get the recovered NVD disc signal at the Q terminal. Compared with the signal read from the disc, the recovered disc signal has less jitter and is a disc signal with higher quality than the read signal. Complete The function of phase detector 5.

Fig. 6 is the classic two frequency division circuit that the utility model adopts, promptly the D end of D flip-flop is connected with Q end, and CLK end is connected with the output end of voltage-controlled oscillator 4, then the frequency of Q end output is clock CLK half of the terminal frequency.

Experiments and analysis show that the recovered optical disc signal obtained by the clock signal extraction circuit of the red light high-definition optical disc of the utility model has less jitter and better quality than the signal read from the optical disc. The clock signal recovery circuit of the utility model is simple and easy to operate.

Claims (5)

1, a kind of clock signal extracting circuit of high-definition red-laser disc, comprise frequency discriminator (1), the output terminal of this frequency discriminator (1) links to each other with the input end of charge pump (2), the output of this charge pump (2) connects the input end of voltage controlled oscillator (4) through wave filter (3), the output terminal of this voltage controlled oscillator (4) links to each other with the input end of frequency-halving circuit (6) and an input end of phase detector (5) respectively, another input termination NVD CD signal of this phase detector (5), the CD signal that the output terminal output of this phase detector (5) recovers, the output terminal clock signal of described frequency-halving circuit (6), this clock signal is also imported described frequency discriminator (1) simultaneously with the NVD CD signal, the structure that it is characterized in that described frequency discriminator (1) is: the output terminal of first register (8) links to each other with the input end of second register (9), the input end of output termination the 3rd register (10) of second register (9), an output of each of described first register (8) and second register (9) termination first comparer (7), the output terminal of first comparer (7) links to each other with the control end of second register (9), the input end of output termination first register (8) of the first pulsewidth counter (11), the control end of output termination the 3rd register (10) of frame pulse generator (12), the input end of the 3rd register (10) output termination one increase and decrease pulse producer (13), the NVD CD signal connects frame pulse generator (12) input end, and the output terminal of this increase and decrease pulse producer (13) is the output terminal of described frequency discriminator (1).

2, the clock signal extracting circuit of high-definition red-laser disc according to claim 1 is characterized in that described frame pulse generator (12) is made up of the low-pass filter (14), the second pulsewidth counter (15) and second comparer (16) that connect successively.

3, the clock signal extracting circuit of high-definition red-laser disc according to claim 1, it is characterized in that described increase and decrease pulse producer (13) is made of subtracter (17), down counter (19), crystal oscillator (20) and multi-way switch (18), the output terminal of this subtracter (17) connects the control end of down counter (19) and multi-way switch (18) respectively, another input termination crystal oscillator (20) of this down counter (19), output termination multi-way switch (18) input end of this down counter (19).

4, the clock signal extracting circuit of high-definition red-laser disc according to claim 1, it is characterized in that described frequency-halving circuit (6) is a d type flip flop, its annexation is: its D end joins with the Q end, the output terminal of CLK termination voltage controlled oscillator (4), and the Q end is output terminal, clock signal.

5, the clock signal extracting circuit of high-definition red-laser disc according to claim 1, it is characterized in that described phase detector (5) is a d type flip flop or J-K flip flop, the annexation of this d type flip flop is: D termination NVD CD signal, the clock multiplier signal of CIK termination voltage controlled oscillator (4) output, and the CD signal that the output of Q end recovers.

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