WO2011153776A1

WO2011153776A1 - Phase locked loop, voltage control device and voltage control method

Info

Publication number: WO2011153776A1
Application number: PCT/CN2010/078000
Authority: WO
Inventors: 彭勇
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-06-12
Filing date: 2010-10-22
Publication date: 2011-12-15
Also published as: CN101841329A

Abstract

A phase locked loop (PLL), voltage control device and voltage control method are provided. The PLL comprises a phase detector (402), a filter (404), a voltage control module (406) and an oscillator (408). The voltage control module (406) comprises: a pulse width modulation generator (4062) for generating modulation signals with different pulse widths according to phase difference signals filtered by the filter; and a demodulator (4064) for converting the modulation signals with different pulse widths into analog voltage control error signals, and outputting the analog voltage control error signals to the oscillator (408). The present invention lowers the requirement of the digital-to-analog converter (DAC) for the high-precision reference voltage source, thus reducing the implementation cost of the hardware of the DAC and the PLL.

Description

TECHNICAL FIELD The present invention relates to the field of communications, and in particular to a phase locked loop, a voltage control device, and a voltage control method. Background Art In a communication system, communication between base stations requires a high-precision clock frequency. The frequency accuracy required for frequency synchronization under various standards requires 0.05ppm (or 50ppb) accuracy. For CDMA (Code Division Multiple Access) and TD (Time Division) systems that require phase synchronization, Then the phase difference is required to be within 3 us. This high-precision clock source uses a high-stability oscillator as a local oscillator, but since the oscillator has an aging characteristic, its frequency drifts in one direction over time. In order to overcome this drift characteristic, it is necessary to calibrate the oscillator by using another long-term stable clock source as a reference. This calibration device is called a phase-locked loop. The phase-locked loop is a closed-loop automatic control system that tracks the phase of the input signal. A typical phase-locked loop consists of a phase detector, a loop filter, and a voltage-controlled oscillator, as shown in Figure 1. Wherein, the phase detector is used to compare the reference frequency with the frequency or phase of the output of the voltage controlled oscillator, and output the frequency difference or phase difference between the two. The loop filter is actually a low-pass filter that filters out the high-frequency components generated by the phase detector, the output ripple, and limits the out-of-band noise. On the other hand, it is also an important parameter adjustment of the phase-locked loop. The device can change the important performance specifications of the phase-locked loop by changing the parameters of the loop filter. It is the size of the loop capture band, the capture time of the loop, the tracking time, the stability of the loop, and the noise figure. Etc. The voltage controlled oscillator is controlled by the loop filter output voltage to generate an oscillating signal, which is then shaped and outputs the final stable signal. According to the composition of the loop, the phase-locked loop can be divided into an analog phase-locked loop and a digital phase-locked loop. The digital phase-locked loop is shown in Figure 2. A voltage control module is added after the filter circuit. The voltage control module is implemented by a DAC (Digital-to-Analog Converter) and will be filtered by the filter. The digital signal is converted to an analog signal. Since the DAC is sensitive to reference voltage variations (Vout=Vref *(x/65536), Vout is the DAC output voltage, Vref is the DAC reference voltage, x is the digital signal for each write to the DAC, and 65536 is the 16-bit DAC maximum digital signal. ), the voltage accuracy of the output after digital-to-analog conversion is closely related to the stability of the reference voltage, and the instability of the reference voltage may be The voltage accuracy that causes the DAC output drops significantly. Therefore, when the DAC is used to implement the voltage control module, the related art provides a high-precision reference voltage for the DAC, which causes an increase in the hardware cost of the phase-locked loop. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a phase-locked loop, a voltage control device, and a voltage control method to solve the above-mentioned problem that when a voltage control module is implemented using a DAC, a high-precision reference voltage needs to be provided for the DAC, thereby causing a lock. The problem of increasing the cost of phase loop hardware. According to an aspect of the invention, a voltage control apparatus is provided, comprising: a pulse width modulation generator for generating a modulated signal of different pulse widths according to a filtered phase difference signal; a demodulator for using different pulses The modulated signal of the width is converted into an analog voltage control error signal, and an analog voltage control error signal is output. Preferably, the pulse width modulation generator comprises: a high resolution counter for counting the difference of the filtered phase difference signal; and a generating module for generating a modulated signal of different pulse width according to the counting. Preferably, the demodulator is an integral filter circuit for integrating and filtering the modulated signals of different pulse widths to generate different analog voltage control error signals, and outputting the analog voltage control error signals. According to another aspect of the present invention, a phase locked loop is provided, including a phase detector, a filter, a voltage control module, and an oscillator, wherein the voltage control module includes: a pulse width modulation generator, configured to filter according to The filtered phase difference signal generates modulated signals of different pulse widths; the demodulator is configured to convert the modulated signals of different pulse widths into analog voltage controlled error signals, and output analog voltage control error signals to the oscillator. Preferably, the phase locked loop further comprises: a reference clock divider and an oscillating clock divider; wherein, the reference clock divider is configured to divide the clock frequency of the reference clock source, and divide the frequency reference The clock frequency of the clock source is sent to the phase detector; the oscillator clock divider is used to divide the clock frequency generated by the oscillator, and the clock frequency generated by the divided oscillator is sent to the phase detector. Preferably, the pulse width modulation generator of the phase locked loop comprises: a high resolution counter for counting the difference of the filtered phase difference signal of the filter; and a generating module for generating different pulse widths according to the counting Modulated signal. Preferably, the demodulator of the phase-locked loop is an integral filter circuit for integrating and filtering the modulated signals of different pulse widths to generate different analog voltage-controlled error signals, and outputting an analog voltage-controlled error signal to the oscillator. According to another aspect of the present invention, a voltage control method is further provided, including: generating modulated signals of different pulse widths according to the filtered phase difference signals; and converting modulated signals of different pulse widths into analog voltage controlled error signals, And output analog voltage control error signal. Preferably, the step of generating the modulated signals of different pulse widths according to the filtered phase difference signals comprises: generating a modulated signal of different pulse widths using the high resolution counter according to the filtered phase difference signals; and modulating signals of different pulse widths The steps of converting into an analog voltage control error signal include: integrating filtering the modulated signals of different pulse widths to generate different analog voltage control error signals. Preferably, before the step of generating the modulated signals of different pulse widths according to the filtered phase difference signals, the method further includes: comparing the second pulses of the reference clock source with the second pulses divided by the clock frequency generated by the phase locked loop oscillator Phase, obtain phase difference analog signal; filter phase difference analog signal and convert it into digital signal. The invention replaces the original DAC voltage control mode by using a Pulse Width Modulation (PWM) voltage control method, converts the signal reflecting the phase difference into a modulation signal of different pulse width, and demodulates the analog control voltage pair communication. The clock of the device is calibrated, making full use of the pulse width modulation method to keep the output voltage of the power supply constant when the operating conditions change. This solves the related problem that the DAC realizes the voltage control module when the DAC realizes the voltage control module, because the instability of the reference voltage leads to the DAC output. The voltage accuracy is reduced, and a high-precision reference voltage needs to be provided for the DAC, which causes an increase in the hardware cost of the phase-locked loop, reduces the requirement of the DAC for a high-precision reference voltage source, and further reduces the hardware implementation of the DAC and the phase-locked loop. cost. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, In the drawings: FIG. 1 is a schematic diagram of a phase locked loop circuit according to the related art; FIG. 2 is a schematic diagram of a digital phase locked loop circuit according to the related art; 3 is a structural block diagram of a voltage control device according to an embodiment of the present invention; FIG. 4 is a schematic structural diagram of a PWM voltage control phase-locked loop according to an embodiment of the present invention; FIG. FIG. 6 is a flow chart of steps of a voltage control method according to an embodiment of the present invention; FIG. 7 is a flow chart of steps of another voltage control method according to an embodiment of the present invention; . BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. Referring to FIG. 3, a block diagram of a voltage control device according to an embodiment of the present invention is shown, including: a pulse width modulation generator 302, configured to generate modulated signals of different pulse widths according to the filtered phase difference signals. The demodulator 304 is configured to convert the modulated signals of different pulse widths into analog voltage control error signals, and output the analog voltage control error signals. Preferably, the pulse width modulation generator 302 includes: a high resolution counter for counting the difference of the filtered phase difference signal; and a generating module for generating a modulated signal of different pulse width according to the counting. Preferably, the demodulator 304 is an integral filter circuit for integrating and filtering the modulated signals of different pulse widths to generate different analog voltage control error signals. For example, the pulse width modulation generator 302 generates modulated signals of different pulse widths according to the phase difference signals filtered by the phase locked loop filter, and the demodulator 304 converts the modulated signals of different pulse widths into analog voltage controlled error signals, and outputs the signals to the analog voltage control signals. The oscillator, so that the oscillator controls the output frequency. Preferably, the pulse width modulation generator 302 counts the difference of the filtered phase difference signals using a high resolution counter, and then the generating module generates modulated signals of different pulse widths according to the counting. The demodulator 304 uses an integral filter circuit to integrate and filter the modulated signals of different pulse widths to generate different analog voltage control error signals. Then, the analog voltage control error information is output to the oscillator of the phase locked loop. In the related art, when a voltage control module is implemented using a DAC, the reference voltage is unstable. The voltage accuracy of the DAC output is reduced, so it is necessary to provide a high-precision reference voltage for the DAC, resulting in an increase in the hardware cost of the phase-locked loop. In this embodiment, the PWM voltage control method is used instead of the DAC voltage control method, and the pulse width modulation method is utilized to make the output voltage of the power supply maintain a constant characteristic when the operating conditions are changed, thereby reducing the requirement of the DAC for the high-precision reference voltage source. , which reduces the hardware implementation cost of D AC and phase-locked loop. In addition, the current mature commercial DAC has a bit number of 16 bits and its control accuracy is 1/65536. Such accuracy requires high specifications for oscillators such as OCXO or TCXO. To reduce the requirements of this specification, it is necessary to improve the control precision of the DAC, that is, the number of bits of the DAC, and the improvement of the DAC control accuracy is subject to the development of its hardware; On the one hand, the improvement of the DAC control accuracy will inevitably lead to a corresponding increase in the price, and thus the hardware cost of the digital phase-locked loop is improved. In the embodiment, in the process of generating a modulated signal with different pulse widths, software can be used to set the number of bits when the pulse width modulated signal is converted from an digital signal to an analog signal, for example, 20 bits, and the control precision thereof is 1/1048576. While improving control accuracy, it is not necessary to be subject to hardware. The higher the DAC number is, the more expensive the price is; the lower the number of bits, the lower the control of the crystal oscillator such as OCXO or TCXO. At the same time, after the control precision is improved, the post-stage oscillator, such as the OCXO index, can be reduced by one order of magnitude, which saves the hardware cost while ensuring the accuracy of the clock control. Referring to FIG. 4, a schematic diagram of a PWM voltage-controlled phase-locked loop according to an embodiment of the present invention is shown, including: a phase detector 402, a filter 404, a voltage control module 406, and an oscillator 408. The phase detector 402 is configured to compare the second pulse of the reference clock source with the phase of the second pulse divided by the clock frequency generated by the oscillator 408 to obtain a phase difference analog signal; and the filter 404 is configured to simulate the phase difference The signal is filtered and converted into a digital signal; the voltage control module 406 includes: a pulse width modulation generator 4062, configured to generate modulated signals of different pulse widths according to the filtered phase difference signals; and a demodulator 4064 for different The pulse width modulated signal is converted into an analog voltage control error signal, and the analog voltage control error signal is output to the oscillator 408. The oscillator 408 is configured to generate and output different oscillation frequencies according to the analog voltage control error signal. Preferably, the pulse width modulation generator 4062 includes: a high resolution counter for counting the difference of the phase difference signal filtered by the filter 404; and a generating module for generating a modulated signal of different pulse widths according to the counting. Preferably, the demodulator 4064 is an integral filter circuit for integrating and filtering the modulated signals of different pulse widths to generate different analog voltage control error signals, and outputting the analog voltage control error signals to the oscillator 408. Preferably, the PWM voltage-controlled phase-locked loop of this embodiment may further include: a reference test clock divider 410 and an oscillating clock divider 412. The reference clock divider 410 is configured to divide a clock frequency of the reference clock source, and send a clock frequency of the divided reference clock source to the phase detector 402. The oscillation clock divider 412 is configured to The clock frequency generated by the oscillator 408 is divided, and the clock frequency generated by the divided oscillator 408 is sent to the phase detector 402. Referring to Figure 5, there is shown a flow chart of the steps for applying the phase locked loop of Figure 4 for oscillator calibration. In this embodiment, an optional clock reference source includes a satellite clock, a line clock, a network clock, and the like. The pulse width modulation signal of the embodiment is implemented by a counting method; the integral filtering circuit is implemented by charging or discharging a capacitor or an inductor. Wherein, the reference source is used to reference the clock source; the reference clock divider is used to divide the reference clock; the phase detector is used to phase-detect the phase; the filter filters the phase difference after phase discrimination; pulse width modulation The generator generates modulation signals of different pulse widths according to the filtered signals; the integral filter circuit converts the pulse width modulation signals into analog voltage control voltages; the oscillator generates different oscillation frequencies according to different voltage control voltages; the oscillation clock frequency divider, Used to divide the oscillation frequency. In this embodiment, the satellite clock type global positioning system GPS signal is taken as an example, and the following steps are included: Step S502: The GPS receiver parses the GPS second pulse PP1S as a reference clock source; The clock is not a second ^ ^ rush, such as a 2MHz line clock, then the reference clock needs to be divided by the reference clock divider, the reference clock source is divided to the second pulse. Step S504: the frequency generated by the oscillator is converted into a second pulse by the field programmable gate array FPGA; in this step, the FPGA has an oscillation clock divider (or has an oscillation clock divider function), and the frequency generated by the oscillator is performed by the FPGA. After dividing, the second pulse of the oscillator is generated. Step S506: The phase detector compares the second pulse of the GPS with the phase of the second pulse after the frequency division generated by the oscillator to obtain a phase difference. Step S508: the phase difference between the second pulse of the GPS and the second pulse of the oscillator is filtered by the filter. Converting to a digital signal; Step S510: The pulse width modulation generator generates a corresponding one according to the filtered digital signal Preferably, the high-resolution counter of the pulse width modulation generator counts the difference of the filtered phase difference signals, and the generating module generates modulated signals of different pulse widths according to the counting. Step S512: The pulse width modulation signal is converted into an analog voltage control error signal by an integral filter circuit. Preferably, the integrator of the integral filter circuit integrates the modulation signals of different pulse widths, and the conversion module filters the integrated modulation signal. And generate different analog voltage control error signals, and output analog voltage control error signals to the oscillator. Step S514: The voltage control signal controls the oscillator frequency output. Referring to FIG. 6, a flow chart of steps of a voltage control method according to an embodiment of the present invention is shown, including the following steps: Step S602: The communication device generates modulations of different pulse widths according to the filtered phase difference signals. Signals: To implement the voltage control method of the present embodiment, the communication device of this embodiment includes a processor module, a logic module, and an integral filter circuit. The processor module is responsible for filtering and controlling the voltage control process, the logic module is responsible for generating a pulse width modulation signal, and the integral filter circuit is responsible for demodulating the analog voltage control error signal, that is, the voltage control voltage. In this step, the logic signal of the communication device may generate a modulated signal of different pulse width according to the filtered phase difference digital signal, and transmit the modulated signal to the integral filter circuit. The pulse width modulated signal can be implemented by counting or by other means, such as hardware modulation. A person skilled in the art can also appropriately set the implementation of the pulse width modulation signal as needed, which is not limited in the present invention. Step S604: The communication device converts the modulated signals of different pulse widths into analog voltage control error signals, and outputs analog voltage control error signals. In this step, the modulation signal of different pulse widths can be converted into an analog voltage control error signal by integration by the integral filter circuit of the communication device. The integral filter circuit is used to charge and discharge the capacitor, or other methods, such as charging and discharging the inductor. Those skilled in the art can also appropriately set the product according to the needs. The implementation of the sub-filtering circuit is not limited in the present invention. Referring to FIG. 7, a flow chart of steps of another voltage control method according to an embodiment of the present invention is shown, including the following steps: Step S702: Comparing the second pulse of the reference clock source with the phase-locked loop oscillator The phase of the second pulse divided by the generated clock frequency is obtained to obtain a phase difference analog signal; Step S704: The processor filters the phase difference analog signal obtained by the phase detector and converts the digital signal to the logic module for feedback; Step S706: The logic module generates a modulated signal of different pulse widths by counting according to the digital signal of the phase difference of the feedback, and transmits the modulated signal to the integrated filter circuit; the modulated signals of different pulse widths are generated by the counting method, which is simple to implement and saves the implementation cost. Step S708: The integral filter circuit demodulates different pulse width signals into different analog control voltages by integrating, and outputs the signals to the oscillator; and demodulates the modulated signals of different pulse widths by integrating, which is simple to implement and saves realization cost. Step S710: The oscillator generates different oscillation frequency outputs according to different analog control voltages. Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. The steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claim

A voltage control device, comprising: a pulse width modulation generator, configured to generate a modulation signal of different pulse width according to the filtered phase difference signal;

And a demodulator, configured to convert the modulated signals of different pulse widths into analog voltage control error signals, and output the analog voltage control error signals.

2. The apparatus according to claim 1, wherein the pulse width modulation generator comprises:

a high-resolution counter for counting the difference of the filtered phase difference signal; and a generating module, configured to generate a modulated signal of a different pulse width according to the counting.

3. The apparatus according to claim 1, wherein the demodulator is an integral filter circuit for performing integral filtering on the modulated signals of different pulse widths to generate different analog voltage control error signals, and The analog voltage control error signal is output.

A phase-locked loop, comprising a phase detector, a filter, a voltage control module, and an oscillator, wherein the voltage control module comprises:

a pulse width modulation generator, configured to generate a modulated signal of different pulse width according to the phase difference signal filtered by the filter;

And a demodulator, configured to convert the modulated signal of the different pulse width into an analog voltage control error signal, and output the analog voltage control error signal to the oscillator.

5. The phase locked loop of claim 4, further comprising: a reference clock divider and an oscillating clock divider;

The reference clock divider is configured to divide a clock frequency of the reference clock source, and send the divided clock frequency of the reference clock source to the phase detector;

The oscillating clock divider is configured to divide a clock frequency generated by the oscillator, and send a clock frequency generated by the divided oscillator to the phase detector.

6. The phase locked loop of claim 4, wherein the pulse width modulation generator comprises:

a high resolution counter for counting a difference value of the phase difference signal filtered by the filter;

And a generating module, configured to generate a modulated signal of different pulse widths according to the counting.

The phase locked loop of claim 4, wherein the demodulator is an integral filter circuit for integrating and filtering the modulated signals of different pulse widths to generate different analog voltage control error signals. And outputting the analog voltage control error signal to the oscillator.

8. A voltage control method, comprising: generating modulated signals of different pulse widths according to the filtered phase difference signals; converting the modulated signals of different pulse widths into analog voltage control error signals, and outputting The analog voltage control error signal is described.

9. The method according to claim 8, wherein the step of generating modulated signals of different pulse widths according to the filtered phase difference signals comprises:

Generating the modulated signals of different pulse widths using a high resolution counter according to the filtered phase difference signal;

The steps of converting the modulated signals of different pulse widths into analog voltage controlled error signals include:

The modulated signals of different pulse widths are integrated and filtered to generate different analog voltage control error signals.

The method according to claim 8, wherein before the step of generating the modulated signals of different pulse widths according to the filtered phase difference signals, the method further includes:

Comparing the second pulse of the reference clock source with the phase of the second pulse divided by the clock frequency generated by the phase locked loop oscillator to obtain a phase difference analog signal;

The phase difference analog signal is filtered and converted into a digital signal.