JP2004152361A - System clock generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data demodulation circuit decreased in a chip size by simplifying a circuit configuration and reducing a circuit mount area. <P>SOLUTION: This invention is provided with the following units. A 1st PLL circuit: a wobble signal and a 1st reference clock signal are clocked in frequency and phase. A frequency/phase comparator (FPC): a 1st output signal from the 1st PLL circuit is compared with a system clock signal, and a 2nd output signal is outputted based on the difference between the frequencies and phases.A PLL filter: a 3rd output signal is outputted by setting a predetermined cut-off for the 2nd output signal. A pulse width modulation circuit: a pulse wave having a 2nd reference clock signal as the carrier frequency is generated, and a 4th output signal is generated wherein the wave is pulse-width-modulated by the 3rd output signal. A low-pass filter: the 4th output signal is smoothed to output a 5th output signal. A VCO circuit: the 5th output signal is used as a control voltage. A 1st frequency divider circuit: an output signal of the VCO circuit is frequency divided by N to be output as a system clock signal. A 2nd frequency divider circuit: the system clock signal is frequency divided by M to be fed back to the frequency/phase comparator. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a system clock generation circuit, and in particular, can reproduce data of a wobble signal at a CAV (constant rotation speed), has a small jitter in the obtained system clock signal, and is stable even when the wobble signal is lost. The present invention relates to a digitized system clock generation circuit capable of generating a system clock signal.
[0002]
[Prior art]
In order to record write data on an optical disk such as a CD-R / RW or DVD-RAM, the write data is EFM-modulated, and a predetermined track of the optical disk is irradiated using a laser beam controlled for writing by a laser controller. Then, data is written.
In such an optical disk, a synchronization signal for rotation control and address information (absolute time information) are recorded as a wobble signal by forming a groove (groove) in a meandering manner.
[0003]
The wobble signal is a signal FSK-modulated with a bi-phase code modulation signal (BIDATA), and the wobble frequency f _WBL becomes 22.05 ± 1 kHz (at the time of 1 × speed reproduction) when the disk rotation is at a prescribed linear velocity. .
An ATIP (absolute time in pregroove) signal including absolute time information reproduced from a wobble signal is composed of a synchronization signal, address data (absolute time data), and an error detection code CRC as BIDATA. The unit is 42 bits.
The repetition frequency of the synchronization signal is 75 Hz. To reproduce such data recorded as a wobble signal on an optical disc, a demodulation circuit for demodulating the data of the wobble signal is required.
A circuit described in Patent Document 1 is known as this type of system clock generation circuit.
[0004]
[Patent Document 1]
JP 2001-143404 A
FIG. 5 is a diagram showing a schematic configuration of a system clock generating circuit synchronized with a wobble signal introduced in Patent Document 1 and the like.
The system clock generation circuit shown in FIG. 5 is configured as a PLL circuit, and operates so that the wobble signal WBL detected from the optical disc is locked to the system clock signal WPCLK. It comprises a phase comparison circuit 10, a speed (frequency) comparison circuit 20, charge pump circuits 30, 40, a low-pass filter (LPF) 50, a voltage controlled oscillation circuit (VCO) 60, and an N (N is an integer) frequency dividing circuit 70. ing.
[0006]
A synchronization signal and an ATIP signal are detected by inputting a system clock (WPCLK) generated by the PLL system clock generation circuit to a wobble signal FM demodulation circuit (not shown) or a digital PLL (DTLL).
In order to perform data recording by CAV driving the optical disc, a spindle motor for driving the optical disc is driven to rotate at a constant speed.
Here, assuming that the constant rotational speed is a specified speed, that is, a single speed, the wobble frequency f _WBL becomes 22.05 ± 1 kHz in the inner peripheral portion of the track of the optical disc.
[0007]
On the outer side of the inner track, the wobble frequency f _WBL is higher than 22.05 ± 1 kHz. As described above, the frequency change range of the wobble frequency f _WBL is, for example, about 22 kHz to 53 kHz. The wobble signal WBL is input to one input terminal A of the phase comparison circuit 10 and the speed (frequency) comparison circuit 20. To the other input terminal B, the output of the VCO 60 is divided by N by the frequency divider 70 and input.
[0008]
The phase comparison circuit 10 outputs a charge-up signal that is high during a period corresponding to a phase difference from the rise of the input pulse at the input terminal A to the rise of the input pulse at the input terminal B, It is sent to the circuit 30.
Further, the phase comparison circuit 10 sends to the charge pump circuit 30 a charge-down signal that is high during a period corresponding to a phase difference from the rise of the input pulse at the input terminal B to the rise of the input pulse at the input terminal A.
[0009]
Similarly, the speed comparison circuit 40 also generates a signal based on the speed (frequency) difference, supplies a charge-up signal to the p-channel transistor 43 via the inverting buffer amplifier 41, and supplies a charge-down signal to the n-channel transistor 44. I do. The charge pump circuit 30 includes an inverting buffer amplifier 31, a constant current source 32, a p-channel transistor 33, an n-channel transistor 34, and a constant current source 35.
The charge pump circuit 40 includes an inversion buffer circuit 41, a constant current source 42, a p-channel transistor 43, an n-channel transistor 44, and a constant current source 45.
[0010]
A constant current I ₀ based on the charge-up signal from the phase comparator 10 is supplied to a low-pass filter 50, a constant current I ₀ is sucked into the charge pump circuit 30 as a sink current from the low pass filter 50 on the basis of a charge-down signal . Similarly, the constant current I ₁ is supplied to the low-pass filter 50 by the charge-up signal from the speed comparison circuit 20, and the constant current I ₁ is drawn out to the charge pump circuit 40 as a sink current based on the charge-down signal. The low-pass filter (LPF) 50 includes a resistor R and capacitors C1 and C2. The potential of the signal line 51 changes due to the inflow of the charge-up current and the outflow of the charge-down current, and the smoothed voltage controls the VCO 60. It is supplied as a voltage. The VCO 60 outputs an oscillation output signal having a frequency that can follow the wobble signal WBL according to the control voltage.
As a result, the 1 / N frequency-divided signal is fed back and supplied to the phase comparison circuit 10 and the speed comparison circuit 20 to enter a PLL loop control state. As a result, the wobble signal WBL and the system clock signal WPCLK are locked.
[0011]
[Problems to be solved by the invention]
In the system clock generation circuit as shown in FIG. 5, two comparison circuits, ie, a phase comparison circuit 10 for performing a phase comparison and a speed comparison circuit 20 for performing a speed (frequency) comparison are required. To operate the system clock WPCLK in a wide range from 1 × to 56 ×, it is necessary to change the values of the constant currents I ₀ and I ₁ or the value of the resistor R.
In order to change the analog values such as I ₀ , I ₁ , and R, it is necessary to separately mount an analog circuit for that purpose, and there is a problem that the circuit mounting area increases. Further, the low-pass filter circuit 50 requires two external capacitors C1 and C2.
[0012]
As described above, the system clock generation circuit used in the conventional data demodulation circuit has a problem that the area for mounting the analog circuit is large and the chip area is large when a one-chip integrated circuit is manufactured. In addition, since two external capacitors are used, the adjustment is complicated.
The present invention has been made to solve the above-described problem, and can reduce the number of external capacitors, make a low-pass filter having a simple configuration, and at the same time, stop using a charge pump circuit and reduce the circuit scale. And a data demodulation circuit for a wobble signal.
[0013]
[Means for Solving the Problems]
A system clock generating circuit according to the present invention rotates an optical disc at a constant rotation speed (CAV) and generates a system clock signal locked to the wobble signal for performing CAV recording on the optical disc based on the extracted wobble signal. A first PLL circuit for frequency and phase clocking the wobble signal and the first reference clock signal; a first output signal from the first PLL circuit and the system clock signal; And a frequency / phase comparator (FPC) that outputs a second output signal based on the difference between the frequency and the phase, and outputs a third output signal by giving a predetermined cutoff to the second output signal. And a pulse wave having a carrier frequency of the second reference clock signal, and generating the third output signal. A pulse width modulation circuit for outputting a fourth output signal in which the pulse width of the pulse wave is modulated, and a low pass for applying a predetermined cutoff to the fourth output signal and smoothing the fourth output signal to output a fifth output signal A filter, a VCO circuit that generates a sixth output signal having an oscillation frequency in a predetermined frequency range using the fifth output signal as a control voltage, and divides the sixth output signal by N (N is an integer). A first frequency divider circuit for outputting the system clock signal, and a second frequency divider circuit for dividing the system clock signal by M (M is an integer) and feeding it back to the frequency / phase comparator (FPC). It is characterized by having.
[0014]
Further, the present invention provides a system clock generation circuit based on a phase difference between a sub-synchronization signal (SUB _sync ) output from an encoder of CAV recording information and an ATIP synchronization signal (ATIP _sync ) obtained from the wobble signal. The frequency division ratio M of the second frequency dividing circuit is changed to lock the sub-synchronization signal and the ATIP synchronization signal.
Further, according to the present invention, in the system clock generation circuit, a selection circuit for selectively inputting either the wobble signal or the third reference clock signal is provided to the first PLL circuit.
Further, the invention is characterized in that in the system clock generation circuit, the first PLL circuit is configured as a PI type digital filter.
Further, according to the present invention, in the system clock generation circuit, the third output signal is divided and supplied to the pulse width modulation circuit so that a variation of the carrier frequency of the pulse width modulation circuit within one cycle is minimized. It is characterized by the following.
For example, the present invention is characterized in that in a system clock generating circuit, the first, second and third reference clock signals are obtained by selecting a reference clock signal near 203 MHz and dividing the reference clock signal. And
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a diagram showing a data demodulation circuit for a wobble signal according to one embodiment of the present invention.
In the present invention, unlike the conventional circuit configuration shown in FIG. 5, a pulse width modulation (PWM) circuit 111 is employed without using a charge pump circuit, a phase error is obtained by an FPC 109, and a PWM circuit is obtained based on the phase error signal. By changing the pulse width of the pulse 111, the configuration is such that a function equivalent to the charge pump circuit is equivalently exhibited.
[0016]
The wobble signal WBL 302 rotates at a constant rotation speed in the case of CAV driving, and a wobble signal WBL having an FSK-modulated wobble frequency f _WBL of 22 kHz to 53 kHz is output to one terminal of the multiplexer 105 in the case of 1 × speed. Supplied to A reference signal 304 is input to the other terminal of the multiplexer 105. The reference signal 304 having a range of 22 kHz to 53 kHz in which the wobble frequency f _WBL changes in CAV driving at 1 × speed is input to the multiplexer 105. Supplied.
[0017]
In the present embodiment, 33.8688 MHz is oscillated by the crystal oscillator 101, which is hexadecimally multiplied to generate a reference signal having a frequency of 203.2128 MHz (about 203 MHz). The frequency is divided and used as a reference signal 304. The reference signal 304 and the wobble signal (WBL) 302 can be selectively switched by a selection signal 310, and the reference signal 304 is selected until the wobble signal WBL having a predetermined frequency is obtained from the optical disc. When the wobble signal WBL can be obtained, the multiplexer 105 is switched by the selection signal 310 to operate so that the wobble signal WBL is selected.
[0018]
The output from the multiplexer 105 is input to the PLL circuit 107, and is locked in phase and frequency with the reference signal 306 obtained from the PLL circuit 107. When the multiplexer 105 selects the wobble signal and the PLL circuit 107 locks the phase, the wobble signal and the PLL circuit 107 maintain the phase locked state. The reference signal 306 can be supplied by dividing the above-mentioned signal of about 34 MHz. The output of the PLL 107 is supplied to one input of a frequency phase comparator (FPC) 109. A signal obtained by dividing the system clock signal WPCLK by 1 / M is input to the other input of the FPC 109, the frequency and the phase are compared, and an output signal based on the difference is supplied to the PLL filter 200.
[0019]
The PLL filter 200 can be configured as a PI digital filter. That is, it comprises multipliers 201 and 203 having coefficients K ₀ and K ₁ , adders 202 and 205 and a delay circuit 204.
The PLL filter 200 gives a predetermined cutoff to the output from the FPC 109, and can easily change the cutoff frequency by changing the cases K ₀ and K ₁ of the multipliers 201 and 203.
[0020]
The output signal from the PLL filter 200 is input to the PWM circuit 111. The PWM circuit 111 generates a pulse wave having the reference clock signal 308 as a carrier frequency, and the pulse width of the pulse wave is modulated by a signal from the PLL filter 200. In this embodiment, a reference signal having a frequency of 25.4 MHz obtained by dividing the above-described approximately 203 MHz by ８ is used as the reference signal 308.
The output of the PWM circuit 111 is supplied to a low-pass filter 113 composed of R and C. The low-pass filter 113 smoothes the output of the PWM circuit 111 by giving a predetermined cutoff, and supplies a control voltage to the subsequent VCO 115.
[0021]
In the low-pass filter 113 used in the present embodiment, the values of R and C are selected so as to give a cutoff of 10 kHz. The VCO 115 is configured to output an oscillation frequency having a frequency change of about 200 MHz when the control voltage changes by 1 volt.
The output from the VCO 115 is frequency-divided by N (N is an integer) by a frequency divider 117, further frequency-divided by M (M is an integer) by a frequency divider 119, and fed back to the FPC 109 and supplied. As a result, the FPC 109 compares the frequency and phase of the output signal of the PLL 107 with the output signal of the frequency divider 119, and outputs a signal based on the difference.
[0022]
By such a closed loop PLL operation, the system clock signal WPCLK is output as a signal whose frequency and phase are locked with the wobble signal WBL.
The frequency division ratio N of the frequency divider 117 is selected from 1, 2, and 4 according to the rotation speed of the optical disk. The frequency division ratio M of the frequency divider 119 is normally set to 686.
[0023]
FIG. 2 shows a sub synchronization signal SUB _sync output from an encoder of CAV recording information and an ATIP synchronization signal ATIP _sync obtained from a wobble signal WBL. The sub synchronization signal is rotating at 1 × speed. Sometimes it outputs a 75 Hz synchronization signal.
The ATIP synchronization signal is a signal read from the optical disc by the data demodulation circuit, and it is necessary to lock the leading edge within ± 2 frames of the synchronization signal.
[0024]
In the circuit of the present invention, the phase difference between the sub synchronization signal 310 and the ATIP synchronization signal 312 is detected by the phase difference comparison circuit 121, and the frequency division ratio M of the frequency divider 119 is changed based on the detected value. , And make the sub-synchronization signal coincide with the ATIP synchronization signal.
Specifically, this can be realized by changing the frequency division ratio 686 to 688 or 684.
[0025]
The system clock WPCLK created in this way is used as a channel clock for CAV recording, but can also be used as a channel clock for constant linear velocity (CLV) recording.
Further, by changing the coefficient _{K 0} of the multiplier 201 of the PLL filter 200, it is possible to easily adjust the loop gain of CAVPLL. Similarly, the coefficient _{K 1} of the multiplier 203 determines the cutoff frequency of the PLL filter 200. Therefore, stabilization of the PLL loop can be easily achieved by properly selecting the coefficients K ₀ and K ₁ .
[0026]
It is desirable that the data for changing the pulse width of the carrier frequency of the PWM circuit 111 based on the output from the PLL filter 200 be divided and supplied so that the fluctuation within one cycle of the carrier frequency is minimized. In this manner, the oscillation is stably obtained without greatly changing the control voltage applied to the VCO 115 by dividing and supplying the power so as to minimize the fluctuation within one cycle.
FIG. 3 is a diagram showing an example in which the output voltage from the PLL filter is divided and applied to the PWM circuit 111.
[0027]
By performing such control, the standard deviation of the fluctuation of the system clock signal WPCLK could be controlled to 1% or less. Further, a PWM carrier attenuation rate of -60 dB was obtained.
In this embodiment, the reference signal having a clock frequency of about 203 MHz is used to generate the reference signal. However, in order to reduce the fluctuation of the VCO 115 due to the carrier of the PWM circuit 111, it is necessary to use the PWM. It is necessary to increase the frequency of the carrier signal supplied to the power supply. Therefore, it is preferable to set the reference signal 308 as high as possible within the range of the driving frequency of the element.
FIG. 4 shows the output waveform of the VCO 60, and it can be seen that the state has shifted to the stable state in a very short time (about 150 μs).
[0028]
【The invention's effect】
As described above, the present invention has been described in detail based on the embodiment. However, in the present invention, since the digital FPC in which the phase comparison circuit and the speed comparison circuit are integrated is adopted, the frequency control and the phase control can be performed simultaneously. Became possible.
Further, since the digital FPC can be easily configured with two JK flip-flops and a gate, there is an advantage that the circuit configuration is simplified.
Further, since the PLL filter is constituted by a digital PI filter, the cutoff frequency can be easily changed.
Further, the PWM circuit used in place of the charge pump circuit can be configured as a counter, and thus has an advantage that the circuit can be simplified.
Further, since the entire circuit has a double PLL configuration, a stable clock signal can be obtained even when the wobble signal is lost.
[Brief description of the drawings]
FIG. 1 is a data demodulation circuit for a wobble signal according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a relationship between a phase difference between a sub-synchronization signal output from an encoder and an ATIP synchronization signal obtained from a wobble signal.
FIG. 3 is a diagram illustrating an example of a signal supplied to a PWM circuit.
FIG. 4 is a diagram showing a change in VCO.
FIG. 5 is a diagram showing a schematic configuration of a system clock generation circuit used in a wobble signal data demodulation circuit introduced in Patent Document 1 and the like.
[Explanation of symbols]
101 Crystal oscillator 103 Divider circuit 105 Multiplexer 107 PLL circuit 109 Frequency phase comparator (FPC)
111 Pulse width modulation (PWM) circuit 113 Low pass filter 115 VCO
117, 119 frequency divider 121 phase difference comparison circuit 200 PLL filter 201, 203 multiplier 202, 205 adder 204 delay circuit 302 wobble signal WBL
304, 306, 308 Reference signal 310 Sub synchronization signal 312 ATIP synchronization signal

Claims (6)

A system clock generating circuit for rotating an optical disk at a constant rotation speed (CAV) and generating a system clock signal locked to the wobble signal for performing CAV recording on the optical disk based on the extracted wobble signal;
A first PLL circuit for frequency and phase clocking the wobble signal and a first reference clock signal;
A frequency / phase comparator (FPC) that compares a first output signal from the first PLL circuit with the system clock signal and outputs a second output signal based on a difference in frequency and phase;
A PLL filter for giving a predetermined cutoff to the second output signal and outputting a third output signal;
A pulse width modulation circuit that generates a pulse wave having a second reference clock signal as a carrier frequency and outputs a fourth output signal in which the pulse width of the pulse wave is modulated by the third output signal;
A low-pass filter that applies a predetermined cutoff to the fourth output signal, smoothes the fourth output signal, and outputs a fifth output signal;
A VCO circuit that generates a sixth output signal having an oscillation frequency in a predetermined frequency range using the fifth output signal as a control voltage;
A first frequency dividing circuit for dividing the sixth output signal by N (N is an integer) and outputting the system clock signal;
A second frequency divider circuit for dividing the system clock signal by M (M is an integer) and feeding back to the frequency / phase comparator (FPC);
A system clock generating circuit comprising: The system clock generating circuit according to claim 1,
The dividing ratio M of the second frequency dividing circuit is based on the phase difference between the sub-synchronizing signal (SUB _sync ) output from the encoder of the CAV recording information and the ATIP synchronizing signal (ATIP _sync ) obtained from the wobble signal. , And the sub-synchronization signal and the ATIP synchronization signal are locked. The system clock generating circuit according to claim 1,
A system clock generation circuit, wherein a selection circuit for selectively inputting either the wobble signal or the third reference clock signal is provided in the first PLL circuit. The system clock generating circuit according to claim 1,
A system clock generating circuit, wherein the first PLL circuit is configured as a PI type digital filter. The system clock generating circuit according to claim 1,
A system clock generation circuit, wherein the third output signal is divided and supplied to the pulse width modulation circuit so that a variation of the carrier frequency of the pulse width modulation circuit within one cycle is minimized. The system clock generating circuit according to claim 3,
A system clock generating circuit, wherein a reference clock signal is selected near 204 MHz, and the first, second, and third reference clock signals are obtained by dividing the frequency of the reference clock signal.

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