200539111 九、發明說明： 【發明所屬之技術領域】 ， 本發明係關於系統時脈產生電路（system clock generating circuit)，尤有關於一種經數位化之系統時脈 產生電路，係以CAV(固定旋轉速度）可再生抖動（wobble) 信號之數據，且可使所獲得的系統時脈信號跳動（j i tter) 較少’而且相對抖動信號的損失仍可產生穩定的系統時脈 鲁信號。 【先前技術】 為了於CD-R/RW、dvd-ram等光碟記錄寫入數據，係 將寫入數據予以EFM調變，並採用藉由雷射控制器控制寫 入用之雷射光，照射於光碟之預定的執道（track)而寫入數 據0 a此種光碟係藉由使溝槽（groove)蛇行形成，將用以控 制旋轉之同步信號及位址資訊（絕對時間資訊）與以記 抖動信號。 抖動信號係為雙相編碼（biphase code)之調變信號 (I DATA): FSK调變之信號，當光碟旋轉為規定的線性速 度時，頻率fWBL即成為22 〇5± lkHz(1倍速再生時）。 包含從抖動信號再生數據之絕對時間資訊的ATIP ==luteTime inPre_Gr〇〇ve，預刻槽絕對時間）信號， 虎與位址數據(絕對時間數據)、錯誤檢測符 號CRC*構成_ΤΑ，通常以42位元為單位。 再者，以同步信號之重複頻率而言係為75Ηζ。為了將 315887 6 200539111 口己錄在光碟作為抖動信號的此種數據予以再生，必須要有 解凋I路用以將抖動信號之數據予以解調。 此種系統時脈產生電路例如已有如揭示於專利文獻！ 者。 .200539111 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a system clock generating circuit, and more particularly to a digitized system clock generating circuit based on CAV (fixed rotation) Speed) can regenerate the data of wobble signals, and make the obtained system clock signal jitter less, and the loss of relative jitter signals can still produce stable system clock signals. [Prior technology] In order to record and write data on CD-R / RW, dvd-ram and other optical discs, the write data is modulated by EFM, and the laser light used for writing control by the laser controller is irradiated on The data is written to a predetermined track of the optical disc. 0 This type of optical disc is formed by serpentine grooves. The synchronization signal and address information (absolute time information) used to control the rotation are recorded with the memory. Jitter signal. The jitter signal is a modulation signal (I DATA) of biphase code: the signal of FSK modulation. When the disc rotates at a predetermined linear speed, the frequency fWBL becomes 22 005 ± lkHz (at 1x speed reproduction) ). ATIP == luteTime inPre_Gr〇〇ve (absolute time of pre-groove) signal containing absolute time information of data reproduced from the jitter signal, tiger and address data (absolute time data), error detection symbol CRC * constitute _ΤΑ, usually with 42-bit units. In addition, the repetition frequency of the synchronization signal is 75Ηζ. In order to reproduce the data of 315887 6 200539111 recorded on the disc as the jitter signal, it is necessary to have a solution to demodulate the data of the jitter signal. Such a system clock generating circuit has been disclosed, for example, in patent literature! By. .
[專利文獻1] · 特開2001-143404號公報 第5圖係顯示上述專利文獻1所揭示之與抖動信號同 步之系統時脈產生電路之概略構成圖。 ^第5圖所示系統時脈產生電路係構成為PLL電路，其 係動作以使自光碟檢測之抖動信號WBL鎖定於系統時脈俨 號WPCLK。由相位比較電路1〇、速度（頻率）比較電路2〇^ 電荷泵（charge purap)電路30、4〇、低通濾波器（LpF)5〇、 電壓控制振盪電路（VCO)60、N(N為整數）分頻電路7〇所構 成。 猎由將該PLL系統時脈產生電路所產生之系統時脈 (WPCLK) ’輸入至未圖示之抖動信號之蹭解調電路及數位 PLL(DTLL)，檢測同步信號與ATIp信號。 為了將光碟作CAV驅動以進行數據記錄，而驅動用以 驅動光碟之主軸電動機（spindle mot〇r)以使其成為一 a 之旋轉。 八”、、一定 在此，將固定的旋轉速度設為規定速度亦即—倍亲 說明’則在光碟軌道之内周部’抖動頻率、即成為心 ± 1kHz 〇 β 在較内周執道更為外周側，抖動頻率【飢係成為較 315887 7 200539111 22· 05± 1kHz更南的頻率。如此，抖動頻率f飢之頻率變 化範圍係例如為22kHz至53kHz程度。抖動信號WBL係輸 入至相位比較電路1 〇以及速度（頻率）比較電路2〇之其中 一方輸入端子A。至於另一方之輸入端子β，則藉由分頻器 70將VC0 60之輸出作n分頻而予以輸入。 相位比較電路1 〇係從輸入端子A之輸入脈衝之上升至 輸入端子B之輸入脈衝上升之相位差對應之期間成為高態 _ (H)的充電（charge up)信號，並透過反轉緩衝放大器 (buffer amplifier)31送出至電荷泵電路30。 此外，相位比較電路10係將為從輸入端子B之輸入脈 衝之上幵至輸入端子A之輸入脈衝之上昇之相位差對應之 期間成為高態的放電（charge down)信號，送出至電荷泵電 路30，前述相位差。 同樣地，速度比較電路20亦作成根據速度（頻率）之差 之信號，並透過反轉緩衝放大器41將充電信號供給至p 籲通道電晶體43，且將放電信號供給至n通道電晶體44。電 荷泵電路30係由反轉緩衝放大器31、定電流源32、ρ通 道電晶體33、η通道電晶體34以及定電流源35所構成。 此外，電荷泵電路40係由反向緩衝放大器41、定電 流源42、ρ通道電晶體43、η通道電晶體44以及定電流源 45所構成。 根據來自相位比較電路10之充電信號而將定電流1〇 供給至低通濾波器5 0，並根據放電信號而從低通濾波器5 0 將定電流1〇作為吸收電流（sink current)抽出至電荷泵電 8 315887 200539111 路30。同樣地’根據來自速度比較電路2〇之充電信號而 將丈電流1〗供給至低通濾波器5〇,並根據放電信號而將定 電流込作為吸收電流<;sink current)抽出至電荷泵電路· 40。低通濾波為（LPF)5〇係由電阻R與電容C1、C2所構成， 藉由充電電流的流入及放電電流的流出而使信號線51之 電位變化，使經平滑化之電壓供給作為vc〇6〇之控制電 壓。VC060係、輸出可追隨抖動信號肌之頻率的振盈輸出 信號，該抖動信號WBL為與控制電壓對應。 藉此’經1 /N分頻的信號即回授而供給至相位比較電 路ίο以及速度比較電路20，成為PLL迴路（1〇〇p)控制狀 態。由此，抖動信號WBL與系統時脈信號wpcLKm成為鎖 定（locked)的狀態。 【發明内容】 [發明欲解決之問題] 關於第5圖所示系統時脈產生電路，係須有用以進行 相位比較之相位比較電路10以及用以進行速度（頻率）比7 較之速度比較電路2G等2種比較電I此外，如欲在從！ 倍速至56倍速之廣範圍之範圍使系統時脈信號？代^動 作，則須使定電流10、I】或電阻R之值變化。 為了使此種1〇、I】、R等之類比值變化，須另行 供該所用之類比電路’故會有電路搭載面積增大的問題。 此外低通’慮波态5 0須有2個外加的電容c 1與C2。、 如此，習知用於數據解調電路之系統時脈產生電路 係具有類比電路搭載面積增大，在作成單晶片化的積體電 3】5887 9 200539111 路時，則有晶片面積增大的問題。此外，又由於甚至使用 2個外加電容，故會有調整更為複雜之問題。 -纟發明係有鑑於上述問題而研創者，其目的在提供一 ==之數據解調電路’用以減少外加電容個數:、作 成間早的構成之低通濾波器，同時又可停止使用 路而將電路規模縮小。 7 [解決問題之方案] 丨 本發明係一種系統時脈產生電路，藉由固定旋 CAV)使光碟旋轉，並根據所取出的抖動信號， : 她乍記錄之前述抖動信號的系統時脈Ϊ 號’其特徵為具備··第j Ρ ^ 1基準時脈信號鎖定頻率增·料二述广動信號與第 π千”祁位，頻率與相位比較器 = 自前述第1PLL電路之第1輸出信號與前述 二=,，輸出根據頻率及相位之差異的第2輸出信 (=;?二對於前述第2輸出信 經前述第3輸，3二出信號;脈衝寬度調變電路，輸出 輸出" 則述脈衝波之脈衝寬度調變之第4 的截頻：使=遽波器，對於前述第4輸出信號賦予預定 述第5二 而輸出第5輸出信號；VC〇電路，以前 輸出 、fa出k唬，第1分頻電路，將前述第6 第i八=千N(N為整數）分頻以輸出前述系統時脈信號之 刀V、回授至箣述頻率與相位比較器 315887 200539111 (FPC)。 个貧q乃《条 士 CAV記錄資訊之編石馬器二㈣f生電路之特徵在，根據自 前述抖動信號所獲得之^^次同步信號（SUBsync)與自. 差而使前述第2分”路步信號（ATiPS_之相位， 步信號與前述ATIP同牛刀頻比M變化，並將前述次同 1 J步彳自旒予以鎖定。 第：電:發:::統時脈產生電路之特徵在，於前述 基準時脈信號之::::=輪入前述抖動信號或第3 有之遙擇電路。 此外，本發明之系統時脈產生電路 1PLL電路係構成作為π型之數位濾波器，月 第3 月之系統時脈產生電路之特徵在，將前述 义/ _ 13 刀剎以供給至前述脈衝寬度調變電路，俾使 :=3度調變電路之前述載波(。咖)頻率在1週 期内的變動最小化。 、登遲Γΐ ’本發明之系統時脈產生電路，係在2〇3MHz附近· >8守脈，並藉由將前述基準時脈信號分頻，以 獲：别述第卜第2及第3基準時脈信號。 【實施方式】 [發明之實施形態] 弟1圖係顯示本發明之一實施形態之抖動信號之數據 解調電路圖。 r j發明不同於第5圖所示習知之電路構成，未採用電 何泵電路，而係採用脈衝寬度調變（PWM)電路in,藉由Fpc 315887 11 200539111 109求出相位錯誤，並根據此相位錯誤信號使p丽電路 之脈衝寬度變化，俾發揮與電荷果等效之功能。 ’ A抖動k 5虎WBL 302係在CAV驅動時，以固定的旋轉速 康凝轉，而於1倍速時係將22kHz至53kHz之具有經F邡 凋义之抖動頻率fwBL之抖動信號WBL，供給至多工器1〇5 之其中之一端子。此外，對於多工器105之另-端子則係 輸入有基準4就3〇4，又j倍速時之⑽驅動之抖動頻率 # f鼠所變化之範圍22kHz至53kHz之基準信號3〇4則供給 至多工器105。 本κ轭形態係藉由晶體振盪器1〇1而使33· 8688mHz 頻率振盪，並將之乘以6倍而使具有2〇3·2ι28μΗζ(約 203MHz)之頻率之基準信號振盪，並藉由分頻電路工⑽將 33· 8688MHz为頻，以作為基準信號3〇4之用。另外，基準 信號304與抖動信號（WBL)3〇2係可藉由選擇信號31〇而選 擇眭地切換，在直到具有預定頻率之抖動信號wbl可從光 碟獲传之間，係選擇基準信號3〇4而使系統時脈信號好⑽ 產生，並在得以獲得抖動信號WBL之階段，藉由選擇信號 310切換多工器1〇5，俾使其動作選擇抖動信號wbl。 自多工器105之輸出係輸入至pLL電路1〇7，並將自 PLL電路1〇7所獲得之基準信號3〇6予以鎖定相位與頻 率。多工器105選擇抖動信號，而且pLL電路1〇7為相位 鎖疋打，抖動#唬與PLL電路1 〇7係保持相位鎖定狀態。 另外，基準彳§號306係可將前述之約34MHz之信號予以分 頻而供給。PLL 107之輸出係供給至頻率相位比較器（Fpc) 315887 200539111 109之其中一方的輸入。對於Fpc 1〇9之另一方的輸入， 則係輸入系統時脈彳s號WPCLK之經1 / Μ分頻的信號，而予 以頻率與相位比較並根據其差異的輸出信號則係供給至· PLL濾波器200。 PLL濾波器200係可構成為ρι型的數位濾波器。亦 即，係由具有係數kq以及1之乘法器201、2〇3、加法器 202、205以及延遲電路204所構成。 PLL濾波器200係相對於來自Fpc 1〇9之輸出賦予預 定的截頻者，以乘法器201、203情況而言藉由變更Kq、Ki 即可容易使截頻頻率變化。 來自PLL濾波器200之輸出信號係輸入至pWM電路 ill dPwm電路ill係產生以基準時脈信號3〇8作為載波頻 率之脈衝波，並藉由來自PLL濾波器200之信號而將該脈 衝波之脈衝寬度予以調變。另以基準時脈信號3〇8而言， 本κ施形悲係採用具有將前述約2〇3MHz予以1/8分頻之 25· 4MHz之頻率的基準信號。 PWM電路111之輸出係供給至由R、c所構成之低通濾 波态113。而低通濾波器113係對於P·電路111之輸出 賦予預定的截頻並使其平滑，以供給對於後續的Vc〇 115 之控制電壓。 本實施形態所使用之低通濾波器丨丨3係選擇R及c之 值俾賦予1 〇kHz之截頻。VCO 115係在控制電塵變化1 伏特時，即輸出具有約200MHz程度之頻率變化之振盪頻率 之構成。 315887 13 200539111 來自VCO 115之輸出係藉由分頻器、117而作N(N為整 數）分頻，又再以分頻器119而作_為整數）分頻，俾回 授供給至FPC1〇9。藉此，FPC⑽即將PLLi〇7之輸出作 ，號與來自分頻器之輸出信號予以頻率及相位比較 輸出根據其差異之信號。 -藉由此種閉迴路的PLL動作，系統時脈信號wpcLK即 輸出作為抖動k號WBL以及經頻率與相位鎖定之信號。 、另外，分頻器、117之分頻比㈣配合光碟的旋轉速度 而遠擇卜2、4。此外，分頻器119之分頻比M，通常係設 定為686。 第2圖係顯示自CAV記錄資訊之編碼器輸出之次同步 信號SUBsync、以及自抖動信號WBL所獲得之Ατιρ同步作 號ATIPsync者，其中次同步信號（_哪咖加⑽ signal)係於1倍速旋轉時輸出75Hz的同步信號。 AT IP同步4號係藉由數據解調電路從光碟所讀取之 尨唬，須與同步信號在士 2訊框以内將前端邊緣予以 定。 在本發明之電路中，係藉由相位差比較電路121來檢 測次同步信號311與ATIP同步信號312的相位差，並根據 該檢測值而將分頻|| 119的分頻比M予以變化，以使次同 步信號與AT IP同步信號一致。 具體而言，係藉由將分頻比變化為688或684，即可 貫現該結果。[Patent Document 1] · Japanese Patent Application Laid-Open No. 2001-143404 Fig. 5 is a schematic configuration diagram showing a clock generation circuit of a system synchronized with a jitter signal disclosed in the above-mentioned Patent Document 1. ^ The system clock generating circuit shown in Fig. 5 is constituted as a PLL circuit, which operates to lock the wobble signal WBL detected from the optical disc to the system clock number WPCLK. Phase comparison circuit 10, speed (frequency) comparison circuit 20, charge purap circuit 30, 40, low-pass filter (LpF) 50, voltage-controlled oscillation circuit (VCO) 60, N (N Is an integer) frequency division circuit 70. The system clock (WPCLK) generated by the PLL system clock generation circuit is input to a demodulation circuit and a digital PLL (DTLL) of a jitter signal (not shown), and a synchronization signal and an ATip signal are detected. In order to drive the optical disc as a CAV for data recording, a spindle motor for driving the optical disc is driven so that it turns into an a. Eight ", must be here, set the fixed rotation speed to the specified speed, that is, the" broad parent explanation ", then the jitter frequency at the inner periphery of the disc track, that is, the heart ± 1kHz 〇 β is more peripheral than the inner periphery. On the other hand, the jitter frequency is a frequency souther than 315887 7 200539111 22 05 ± 1kHz. In this way, the frequency variation range of the jitter frequency f is, for example, approximately 22kHz to 53kHz. The jitter signal WBL is input to the phase comparison circuit 1 One of the input terminals A of the speed (frequency) comparison circuit 20. As for the other input terminal β, the frequency divider 70 divides the output of VC0 60 by n and inputs it. Phase comparison circuit 1 〇 The period from the rise of the input pulse at input terminal A to the rise of the input pulse at input terminal B becomes a high state (charge) signal during the corresponding period, and passes through the buffer amplifier 31 Send to the charge pump circuit 30. In addition, the phase comparison circuit 10 corresponds to the phase difference between the rise of the input pulse from input terminal B to the input pulse of input terminal A. The high-level charge down signal is sent to the charge pump circuit 30 with the aforementioned phase difference. Similarly, the speed comparison circuit 20 also generates a signal based on the difference in speed (frequency), and sends it through the inverting buffer amplifier 41. The charge signal is supplied to the p-channel transistor 43 and the discharge signal is supplied to the n-channel transistor 44. The charge pump circuit 30 is composed of an inverting buffer amplifier 31, a constant current source 32, a p-channel transistor 33, and an n-channel transistor. 34 and a constant current source 35. In addition, the charge pump circuit 40 is composed of an inverse buffer amplifier 41, a constant current source 42, a p-channel transistor 43, an n-channel transistor 44, and a constant current source 45. According to the phase The constant current 10 is supplied to the low-pass filter 50 by the charging signal of the comparison circuit 10, and the constant current 10 is drawn from the low-pass filter 50 as the sink current to the charge pump according to the discharge signal. 8 315887 200539111 Road 30. Similarly, 'supply the current 1 to the low-pass filter 50 according to the charging signal from the speed comparison circuit 20, and operate the constant current according to the discharge signal. The sink current is drawn to the charge pump circuit. 40. The low-pass filter (LPF) 50 is composed of a resistor R and capacitors C1 and C2, and is caused by the inflow of charging current and the outflow of discharge current. The potential change of the signal line 51 causes the smoothed voltage to be supplied as the control voltage of vc060. VC060 is a vibration output signal that can follow the frequency of the jitter signal muscle, and the jitter signal WBL corresponds to the control voltage. Thereby, the signal divided by 1 / N is fed back to the phase comparison circuit ο and the speed comparison circuit 20, and the PLL loop (100p) is controlled. As a result, the wobble signal WBL and the system clock signal wpcLKm are locked. [Summary of the Invention] [Problems to be Solved by the Invention] Regarding the system clock generating circuit shown in FIG. 5, a phase comparison circuit 10 for phase comparison and a speed comparison circuit for speed (frequency) ratio 7 to 7 must be used. 2G and other 2 kinds of comparison electricity I In addition, if you want to follow! The wide range of double speed to 56 times makes the system clock signal? To do this, the value of the constant current 10, I] or the resistance R must be changed. In order to change such analog values of 10, I], R, etc., it is necessary to provide an analog circuit for the use 'separately, so there is a problem that the circuit mounting area increases. In addition, the low-pass wave state 50 must have two external capacitors c 1 and C2. In this way, the clock generating circuit of the system for data demodulation circuit is known to have an analog circuit with a larger mounting area. When a single chip integrated circuit is made 3] 5887 9 200539111, there is an increase in chip area. problem. In addition, since even two external capacitors are used, the adjustment is more complicated. -纟 The invention is a researcher in view of the above problems, and its purpose is to provide a data demodulation circuit == to reduce the number of external capacitors, and to make a low-pass filter with an early structure, and at the same time, it can be stopped To reduce the circuit scale. 7 [Solution to Problem] 丨 The present invention is a system clock generating circuit, which rotates the disc by a fixed rotation CAV, and according to the jitter signal taken out, the system clock signal of the aforementioned jitter signal that she recorded at first 'It is characterized by: ···· j ^ ^ 1 reference clock signal lock frequency increase · The second-mentioned wide-motion signal and the π-th "th position, frequency and phase comparator = the first output signal from the aforementioned first PLL circuit The second output signal (= ;?) is output according to the difference in frequency and phase from the aforementioned two =, (two; for the aforementioned second output signal via the aforementioned third input, 32 output signals; pulse width modulation circuit, output output " Then the fourth cut-off frequency of the pulse width modulation of the pulse wave: let = waver, give the fifth output signal to the fourth output signal and output the fifth output signal; VC0 circuit, previously output, fa Out of k, the first frequency division circuit divides the aforementioned sixth and eighth = thousands N (N is an integer) to output the knife V of the aforementioned system clock signal, and feeds it back to the stated frequency and phase comparator 315887 200539111 (FPC). A poor man is the second stone horse of the CAV record information. The f-generation circuit is characterized in that the phase of the second-minute step signal (ATiPS_) is made according to the difference between the sub-synchronization signal (SUBsync) obtained from the jitter signal and the self-step difference, and the step signal is the same as the ATIP. The frequency ratio M changes, and the previous time is automatically locked with the same step of 1 J. Section: Electricity: Send: ::: The system clock is characterized by the clock signal :::: = turn in The aforementioned jitter signal or the third remote selection circuit. In addition, the system clock generating circuit 1PLL circuit of the present invention is constituted as a π-type digital filter. The characteristics of the system clock generating circuit of the third month are as follows. Meaning / _ 13 The knife brake is supplied to the aforementioned pulse width modulation circuit, so that: = 3 degree modulation circuit of the aforementioned carrier (. Coffee) frequency within a cycle to minimize the change. 登登 Γΐ '本The system clock generation circuit of the invention is around 203 MHz > 8 guards and divides the aforementioned reference clock signal to obtain: separately mention the second and third reference clock signals. [Embodiment] [Embodiment of the invention] Figure 1 shows the jitter of one embodiment of the present invention Signal data demodulation circuit diagram. The rj invention is different from the conventional circuit structure shown in Fig. 5. Instead of using an electric pump circuit, a pulse width modulation (PWM) circuit in is used, which is obtained by Fpc 315887 11 200539111 109. The phase is wrong, and the pulse width of the circuit is changed according to the phase error signal, and it has the function equivalent to the charge result. 'A dither k 5 tiger WBL 302 is fixed at a fixed speed when driven by CAV. At 1x speed, a wobble signal WBL having a wobble frequency fwBL that has passed through the frequency range of 22kHz to 53kHz is supplied to one of the terminals of the multiplexer 105. In addition, for the other-terminal of the multiplexer 105, the reference 4 is 30%, and the jitter frequency of the ⑽ drive when the speed is doubled. The reference signal 304, which ranges from 22kHz to 53kHz, is supplied. Up to multiplexer 105. In this κ yoke form, the frequency of 33.6888mHz is oscillated by the crystal oscillator 10, and multiplied by 6 times to oscillate a reference signal having a frequency of 203.28m 28μΗζ (about 203MHz). The frequency divider circuit uses a frequency of 3388688 as the reference signal 304. In addition, the reference signal 304 and the wobble signal (WBL) 302 can be switched by selecting the signal 31o. The reference signal 3 is selected until the wobble signal wbl with a predetermined frequency can be transmitted from the optical disc. 〇4, so that the system clock signal is generated, and at the stage when the jitter signal WBL is obtained, the multiplexer 105 is switched by the selection signal 310, and the action selects the jitter signal wbl. The output from the multiplexer 105 is input to the pLL circuit 107, and the reference signal 306 obtained from the PLL circuit 107 is locked to the phase and frequency. The multiplexer 105 selects a jitter signal, and the pLL circuit 107 is phase locked, and the jitter # 10 and the PLL circuit 107 are maintained in a phase locked state. In addition, reference 彳 § No. 306 can be supplied by dividing the aforementioned signal of about 34 MHz. The output of PLL 107 is input to one of frequency phase comparator (Fpc) 315887 200539111 109. For the other input of Fpc 109, it is the signal divided by 1 / M in the system clock 彳 s number WPCLK, and the output signal which is compared with the frequency and phase is supplied to the PLL. Filter 200. The PLL filter 200 is a digital filter that can be constructed as a p-type filter. That is, it is composed of multipliers 201, 203, adders 202, 205, and delay circuits 204 having coefficients kq and one. The PLL filter 200 is designed to give a predetermined cutoff frequency to the output from Fpc 109. In the case of multipliers 201 and 203, the cutoff frequency can be easily changed by changing Kq and Ki. The output signal from the PLL filter 200 is input to the pWM circuit ill and the dPwm circuit ill generates a pulse wave with the reference clock signal 3 08 as the carrier frequency, and the signal from the PLL filter 200 is used to generate the pulse wave. The pulse width is modulated. In addition, with reference to the reference clock signal 308, this Kappa signal system uses a reference signal having a frequency of 25 · 4 MHz that divides the aforementioned approximately 203 MHz by a frequency of 1/8. The output of the PWM circuit 111 is supplied to a low-pass filter state 113 composed of R and c. The low-pass filter 113 applies a predetermined cut-off frequency to the output of the P · circuit 111 and smoothes it so as to supply a control voltage for the subsequent VcO 115. The low-pass filter used in this embodiment 3 selects the values of R and c to give a cutoff frequency of 10 kHz. VCO 115 is configured to output an oscillation frequency with a frequency change of about 200MHz when the electric dust is changed by 1 volt. 315887 13 200539111 The output from VCO 115 is divided by N (N is an integer) through the frequency divider and 117, and divided by 119 (_ is an integer). The feedback is supplied to FPC1. 9. With this, FPC⑽ will make the output of PLLi07, and compare the frequency and phase with the output signal from the frequency divider to output a signal based on its difference. -With this closed loop PLL operation, the system clock signal wpcLK is output as a jitter k number WBL and a frequency and phase locked signal. In addition, the frequency divider and the frequency division ratio 117 of 117 match the rotation speed of the optical disc and choose distances 2 and 4. In addition, the frequency division ratio M of the frequency divider 119 is usually set to 686. Figure 2 shows the secondary synchronization signal SUBsync output from the encoder of the CAV recording information, and the Δτιρ synchronization number ATIPsync obtained from the self-dithering signal WBL, in which the secondary synchronization signal (_ 哪 カ 加 ⑽ signal) is at 1x speed Output 75Hz synchronization signal when rotating. AT IP Sync No. 4 is read from the optical disc by the data demodulation circuit. It must be determined with the sync signal within the frame of the front end. In the circuit of the present invention, the phase difference comparison circuit 121 detects the phase difference between the sub-synchronization signal 311 and the ATIP synchronization signal 312, and changes the division ratio M of the frequency division || 119 according to the detection value. In order to make the secondary synchronization signal coincide with the AT IP synchronization signal. Specifically, the result can be achieved by changing the frequency division ratio to 688 or 684.
依此方式所作成之系統時脈信號WPCLK雖係作為CAV 315887 14 200539111 記錄之通道時脈之用，不過亦可作為線性速度固定（CLV) 記錄時之通道時脈之用。 此外，藉由改變PLL濾波器200的乘法器201的係數， K〇，即可容易調整CAVPLL之迴路增益。同樣地，乘法器· 203之係數1係決定該pLL濾波器200之截頻頻率（cut〇ff frequency)。因此，藉由適當選擇係數Kq、，即可容易 測量PLL迴圈的穩定化。 藉由來自PLL濾波器200的輸出，用以變更P·電路 111的載波頻率之脈衝寬度之數據，係以分割供給成為載_ 波頻率在一周其内的變動最小化為佳。如此，則藉由分割 供給成為在一周内的變動最小化，即可穩定地獲得振盪， 而賦予VCO 115的控制電壓不致有極大變動。 第3圖係顯示將來自PLL濾波器的輸出電壓予以分割 而賦予PWM電路111時之一例圖。 藉由此種控制，即可將系統時脈信號wpcLK之變動的 標準偏差控制在1%以下。而且，可獲得-6〇dB& ρ·載波籲 衰減率。 …另外，本實施形態中，雖採用具有約203MHz的時脈頻 率的基準時脈，以藉此而產生基準信號，不過為了將由於 PWM電路111的載波的vc〇 i丨5之變動縮小，須將供給至 P龍的載波信號的頻率提高。因此，基準信號308係以在 凡件之驅動頻率的範圍内盡可能設定較高為佳。 第4圖係顯示VCO 60之輸出波形者，由此可明瞭在極 短時間（150//s)程度内轉換至穩定狀態之情況。 315887 15 200539111 [發明之功效] 綜上:雖根據本發明之實施形態而詳細說明， 發明由於採用將相位比較電路與速度比較電路設為固 數位FPC，因此可同時進行頻率控制與相位控制。疋 此外，數位FPC係可由2個JK正反器與問極 成’因此具有可簡化電路構成的優點。 苒 再者’由於係以數位的PI遽波器構成PLL滤波器，因 此可容易變更截頻頻率。 此外，替代電荷泵電路所採用的pwM 計數器，因此具有可簡化電路之優點。構成為 此外，藉由將電路全體作成2重pLL構成，即可相 於抖動信號的損失仍可獲得穩定的時脈信號。 【圖式簡單說明】 電路第i圖係本發明之—實施形態之抖動信號的數位解調 ，2圖_示自編碼諸出之次同步信號與自抖動信 u X得之AT IP同步信號之相位差的關係圖。 第3圖顯示供給至PWM電路之信號的一例圖。 第4圖係顯示vc〇的變化圖。 第5圖係顯示專利文獻！所揭示用於抖動信號之數位 ”周電路之系統時脈產生電路之概略構成圖。 【主要元件符號說明】 相位比較電路20 it度（頻率）比較電路 電荷泵（charge pump)電路 315887 16 200539111 31 〇 〇 反向緩衝放大器 32 定電流源 33 Γ\ ρ- Ρ通道電晶體 34 n通道電晶體 35 疋電彡奋、、/5 、％ Ail 你 41 反轉緩衝放大器 42 定電流源 43 P通道電晶體 44 n通道電晶體 45 定電流源 50 低通濾波器（LPF) 51 信號線 60 電壓控制振盪電路（VCO) 70 N(N為整數）分頻電路 101 晶體振盪器 103 分頻電路 105 多工器 107 PLL電路 109 頻率相位比較器（FPC) 111 脈衝寬度調變（PWM)電路 113 低通濾波器 115 VCO 117、 Π 9分頻器 121 相位差比較電路 200 PLL濾波器 201 > 203乘法器 202、 2 0 5加法器 204 延遲電路 302 抖動信號WBL 304、 306、308基準信號 310 次同步信號 312 ATIP同步信號Although the system clock signal WPCLK made in this way is used as the channel clock for CAV 315887 14 200539111 recording, it can also be used as the channel clock for linear velocity fixed (CLV) recording. In addition, by changing the coefficient of the multiplier 201 of the PLL filter 200, K0, the loop gain of the CAVPLL can be easily adjusted. Similarly, the coefficient 1 of the multiplier · 203 determines the cutoff frequency of the pLL filter 200. Therefore, by properly selecting the coefficient Kq, the stabilization of the PLL loop can be easily measured. The output from the PLL filter 200 is used to change the data of the pulse width of the carrier frequency of the P · circuit 111. It is better to minimize the fluctuation of the carrier frequency within one week by dividing the supply. In this way, by dividing the supply to minimize fluctuations within one week, oscillation can be obtained stably, and the control voltage applied to the VCO 115 does not vary greatly. Fig. 3 is a diagram showing an example in which the output voltage from the PLL filter is divided and given to the PWM circuit 111. With this control, the standard deviation of the fluctuation of the system clock signal wpcLK can be controlled below 1%. Furthermore, it is possible to obtain -6dB & ρ carrier attenuation. … In addition, in this embodiment, although a reference clock having a clock frequency of about 203 MHz is used to generate a reference signal therefrom, in order to reduce the fluctuation of vc0i5 due to the carrier wave of the PWM circuit 111, The frequency of the carrier signal supplied to Pron is increased. Therefore, the reference signal 308 is preferably set as high as possible within the range of the driving frequency of each component. Figure 4 shows the output waveform of the VCO 60, so that it can be understood that the transition to the stable state can be achieved in a very short time (150 // s). 315887 15 200539111 [Effect of the invention] In summary: Although the invention is described in detail according to the embodiment of the present invention, since the phase comparison circuit and the speed comparison circuit are fixed FPC, the frequency control and phase control can be performed simultaneously.疋 In addition, the digital FPC system can be composed of two JK flip-flops and an inverter pole, so it has the advantage of simplifying the circuit configuration.苒 Furthermore, since the PLL filter is composed of a digital PI wave filter, the cut-off frequency can be easily changed. In addition, instead of the pwM counter used in the charge pump circuit, it has the advantage of simplifying the circuit. In addition, by making the entire circuit into a double pLL structure, a stable clock signal can be obtained with respect to the loss of the jitter signal. [Brief description of the diagram] The i-th diagram of the circuit is the digital demodulation of the jitter signal according to the embodiment of the present invention. Fig. 2 shows the secondary synchronization signal from the self-encoding and the AT IP synchronization signal obtained from the self-jittering signal u X. Diagram of phase difference. Fig. 3 shows an example of a signal supplied to a PWM circuit. Figure 4 shows the change of vc0. Figure 5 shows the patent literature! The schematic diagram of the system clock generating circuit of the digital “circle” circuit for the jitter signal disclosed. [Description of the main component symbols] Phase comparison circuit 20 it degree (frequency) comparison circuit charge pump circuit 315887 16 200539111 31 〇〇 Inverting buffer amplifier 32 Constant current source 33 Γ \ ρ- P channel transistor 34 n channel transistor 35 疋 彡, / 5,% Ail you 41 inverting buffer amplifier 42 constant current source 43 P channel Crystal 44 n-channel transistor 45 Constant current source 50 Low-pass filter (LPF) 51 Signal line 60 Voltage controlled oscillation circuit (VCO) 70 N (N is an integer) Frequency division circuit 101 Crystal oscillator 103 Frequency division circuit 105 Multiplexer 107 PLL circuit 109 Frequency phase comparator (FPC) 111 Pulse width modulation (PWM) circuit 113 Low-pass filter 115 VCO 117, Π 9 divider 121 Phase difference comparison circuit 200 PLL filter 201 > 203 multiplier 202, 2 0 5 adder 204 delay circuit 302 jitter signal WBL 304, 306, 308 reference signal 310 times synchronization signal 312 ATIP synchronization signal
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