CN109802738B - Distributed MIMO channel simulation synchronization device, system and method - Google Patents
Distributed MIMO channel simulation synchronization device, system and method Download PDFInfo
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Abstract
The utility model provides a because distributed MIMO channel emulation synchronizer, system and method, including digital phase discriminator, loop filter, D/A converter, voltage controlled oscillator and the frequency divider that connects gradually, forms closed loop, voltage controlled oscillator output frequency signal, local second pulse data is fed back to the frequency divider, and GPS second pulse and local second pulse do the difference and transmit for digital phase discriminator, and interconnection between the distributed system can save many synchronous reference clocks, synchronous trigger input and trigger output to and the control connection wiring each other. The wiring space is saved, the capacity of the whole system is increased, and the stability of the system is improved.
Description
Technical Field
The disclosure relates to a device, a system and a method for simulating synchronization based on a distributed MIMO channel.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
With the application of multi-antenna technology, multiple-input multiple-output (MIMO) technology can greatly improve channel capacity without increasing bandwidth, but the performance of the MIMO system is greatly affected by the wireless propagation environment, and particularly, the correlation characteristics between sub-channels greatly affect the channel capacity that can be obtained by the MIMO system.
The project mainly solves the MIMO channel simulation technology meeting specific correlation characteristics, and for a linear time-varying MIMO system, input and output signal vectors meet the following relation
Y(t)＝∫H(t,τ)X(t-τ)dτ+n(t) (1)
The discretized upper formula can be expressed as
Wherein n (t) represents the channel noise matrix, and H (t) is the time-varying MIMO channel unit impulse response matrix, which can be further simplified to
In the formula, hi,jRepresenting the complex fading coefficient between the ith transmit antenna and the jth receive antenna.
The cross-correlation matrix of the MIMO related channel can be rewritten as
Wherein G represents MIMO channel matrix which is distributed identically and not related to each other; vec (·) is a vectorization operator of the matrix, defined as vec (a) ═ a1,a2,…,an]TIn the formula, a1,a2,…,anIs a matrixAN row vectors.
According to a matrix formula
Equation (4) can be simplified to a spatial correlation channel model
The essence of the model is the problem of generating a plurality of space-time correlation complex fading channels, and the Cholesky decomposition (if the Cholesky decomposition is a non-positive definite matrix, the eigenvalue decomposition is adopted for solving) of the channel correlation matrix can be used for obtaining a lower triangular coefficient matrix
Then, the coefficient matrix is multiplied by the normalization matrix to obtain
H＝L·vec(G) (7)
It is easy to verify that the channel fading covariance matrix obtained from the above correlation channel is E HHH]＝RH。
Taking an 8 × 8MIMO channel as an example, the analog output signal is represented as
Wherein, y1，y2……y8Multiple antenna output, x1，x2……x8Is a multiple antenna input.
The wireless MIMO channel simulation equipment needs a large number of digital transceiving components, and the transceiving components must synchronously generate, receive and process signals when working. The non-synchronization of any one component can cause the amplitude-phase relationship of signals among the components to be inconsistent, resulting in errors in the processing of the received and transmitted beams.
The traditional parallel bus processing data synchronization problem uses an isometric shielding coaxial cable to transmit a synchronous clock and a synchronous trigger signal, but tiny flaws at a shielding layer and a joint in a strong electromagnetic environment reduce the shielding performance, influence the transmission of the clock and the trigger signal and cause the asynchrony of the trigger signal; then, through improvement, isometric differential cables are used as transmission media of the synchronous clock and the trigger signals, the differential cables can effectively resist electromagnetic interference, but the quantity of connecting cables of the equipment is increased, the production and debugging difficulty of the equipment is increased, and the change of the trigger edge is reduced along with the increase of the length of the cables, so that the synchronism of the trigger signals is influenced.
In summary, because hardware resources are limited, the above matrix operation scale cannot be extended continuously, and meanwhile, the design process is very complicated due to the defects of electromagnetic interference, low transmission efficiency, complex connection and the like existing between the traditional parallel bus transmission lines.
Disclosure of Invention
In order to solve the problems, the invention provides a device, a system and a method for simulating and synchronizing channels based on distributed MIMO.
According to some embodiments, the following technical scheme is adopted in the disclosure:
the utility model provides a because distributed MIMO channel emulation synchronizer, is including connecting gradually, forming closed loop's digital phase discriminator, loop filter, D/A converter, voltage controlled oscillator and frequency divider, voltage controlled oscillator output frequency signal, local pulse per second data is fed back to the frequency divider, and GPS pulse per second and local pulse do the difference after transmit for digital phase discriminator.
As a further limitation, the GPS second pulse signal is connected to the upper computer by a serial bus, the data format includes world time, positioning state and/or latitude and longitude information, and the GPS second pulse signal is used as a synchronization trigger signal.
As a further limitation, the digital phase detector and the loop filter are implemented on a hardware level by a field programmable gate array.
As a further limitation, the voltage-controlled oscillator is composed of a digital-to-analog converter controlled by a field programmable gate array and a voltage-controlled constant temperature crystal oscillator.
A simulation synchronization system based on a distributed MIMO channel comprises a plurality of distributed digital processing branches, wherein the digital processing branches are communicated through an interactive transmission bus;
each digital processing branch comprises a data processing unit and a data distributed control center which are connected in sequence, the data processing unit and the data distributed control center are connected with the channel simulation synchronization device to realize data synchronization, the data distributed control center serves as a sending end to send a synchronization frame header when receiving a synchronization signal rising edge, the data processing unit receives data and starts caching through a multi-path cache according to the analyzed synchronization frame header input in multiple paths, and when any one cache reaches a set caching depth, the data processing unit starts reading the multi-path cache.
As a further limitation, the data processing unit comprises a plurality of Vertex-7, Kintex-7 series FPGAs (abbreviated as V7, K7), a digital signal processing unit and a synchronous dynamic random access memory unit, the V7 module is in bidirectional communication with each K7 to form a star-shaped architecture, each K7 module is communicated with a plurality of digital signal processing units and synchronous dynamic random access memory units, and the V7 module is connected with a corresponding data distribution control center through an optical multi-path optical module.
As a further limitation, at least one of the multiple optical modules is connected to the rf transceiver module.
As a further limitation, the data distribution control centers are connected by an interactive transmission bus.
Based on the working method of the system, the data processing units realize data synchronization by using a channel simulation synchronization device, the data distributed control center serves as a sending end and sends a synchronization frame header when receiving a rising edge of a synchronization signal, the data processing units receive data and start caching through a multi-path buffer according to the analyzed multi-path input synchronization frame header, and when any one buffer reaches a set caching depth, the operation of reading the multi-path buffer is started.
As a further limitation, the specific process of synchronization of the transmission data includes: starting data transmission according to the edge of the synchronous trigger signal, taking the rising edge of the trigger signal as an example, when the rising edge of the synchronous signal arrives, the sending end sends N sections of synchronous protocol frame headers containing special characters, and the receiving end decodes the moment of the special characters after receiving the frame headers containing the special characters as the edge of the synchronous trigger signal to carry out data synchronization alignment operation.
Compared with the prior art, the beneficial effect of this disclosure is:
the present disclosure achieves synchronous clock frequency synthesis from a GPS pulse-per-second signal. And clock synchronization and synchronous triggering functions of the distributed MIMO channel simulator are realized.
The interconnection between the distributed systems of the present disclosure may save many synchronous reference clocks, synchronous trigger inputs and trigger outputs, and control connection wiring between each other. The wiring space is saved, the capacity of the whole system is increased, and the stability of the system is improved.
The star network topology structure is formed by using the optical fiber communication technology, large-scale distributed MIMO channel simulation is realized, and the number of data bus connecting wires is greatly reduced, so that the external interference probability of the bus is reduced, and the error rate of signal transmission is reduced. The method can be a powerful support for large-bandwidth data transmission, complex beam forming and multi-antenna technical development in the field of 5G communication test.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application.
FIG. 1 is a schematic diagram of a GPS pulse-per-second based digital phase locked loop of the present disclosure;
FIG. 2 is a block diagram of a data signal processing unit of the present disclosure;
FIG. 3 is a large scale distributed MIMO channel simulation topology of the present disclosure;
the specific implementation mode is as follows:
the present disclosure is further described with reference to the following drawings and examples.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
In the present disclosure, terms such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "side", "bottom", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only relational terms determined for convenience in describing structural relationships of the parts or elements of the present disclosure, and do not refer to any parts or elements of the present disclosure, and are not to be construed as limiting the present disclosure.
In the present disclosure, terms such as "fixedly connected", "connected", and the like are to be understood in a broad sense, and mean either a fixed connection or an integrally connected or detachable connection; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present disclosure can be determined on a case-by-case basis by persons skilled in the relevant art or technicians, and are not to be construed as limitations of the present disclosure.
The utility model provides a gigabit transceiver based on FPGA utilizes optic fibre to provide synchronous trigger's mode when transmitting data, realizes each subassembly synchro control to avoid the external interference that the trigger line received, reduce the connecting cable quantity between the equipment simultaneously by a wide margin. The receiving and transmitting component and the signal processing or data processing extension set at the rear end are connected by optical fibers to serve as transmission channels of uplink or downlink digital signals. According to the long-term stability of the GPS pulse per second, the pulse per second of the GPS module is used as a reference clock, and a stable and synchronous system working clock is generated by adopting a digital phase discrimination technology.
The system realizes the frequency synchronization function in an embedded system according to the frequency synchronization function principle of a phase-locked loop, and the system architecture comprises: a digital phase discriminator, a digital loop filter, a voltage controlled oscillator, a frequency divider device, etc. As shown in fig. 1. The digital phase discriminator and the loop filter are realized by FPGA on the hardware level, the frequency synthesis part consists of a digital-to-analog converter controlled by FPGA and a pressure-controlled constant-temperature crystal oscillator, and the local second pulse negative feedback part consists of a frequency divider. The GPS signal and the upper computer are connected in a serial bus mode, and the data format comprises information such as world time, a positioning state, longitude and latitude and the like. According to the information, the coordination and synchronization work of the distributed system can be controlled by using the information as a synchronization trigger signal. And synchronous triggering of a large system is realized.
Clock synchronization and trigger synchronization have been solved, and data transmission synchronization is also a problem. In the embodiment, a topological structure of a star network is adopted to realize data transmission, and absolute synchronization is required for optical fiber data transmission.
During optical fiber data transmission, uncertain delay exists in transmission of a transmitting end and a receiving end, which is mainly caused by the transmitting and receiving establishment time of an SERDES interface and an internal FIFO buffer. The optical fiber transmits data synchronously, and starts data transmission according to the edge of the synchronous trigger signal, taking the rising edge of the trigger signal as an example. When the rising edge of the synchronous signal comes, the sending end sends the synchronous protocol frame header of N sections of special characters. The receiving end decodes the special character as the synchronous trigger signal edge after receiving the frame header containing the special character. And then performing data synchronization alignment operation according to the interface of multiple paths of optical fiber data, GTX and the like shown in FIG. 2. And the data distribution center is used as a sending end to send the synchronization frame header when receiving the rising edge of the synchronization signal. And the data processing unit receives data and starts caching through a plurality of paths of caches in the FPGA chip according to the analyzed synchronous frame headers, and the cache depth of the caches is set according to the experimental test result. When any one of the multi-path buffers reaches the set buffer depth, the operation of reading the multi-path buffers is started, so that the read data is synchronous data.
According to the above theoretical method and the overall design scheme, a specific implementation method for massive distributed MIMO channel simulation in this embodiment is shown in fig. 3. The MIMO channel simulation algorithm is complex, operations need to be performed in a plurality of data processing board units respectively, and interconnection and intercommunication among a plurality of data processing units are realized by utilizing a high-speed data interaction module through a large-scale data interaction bus, so that baseband signals of other units obtained by each data processing unit are subjected to matrix real-time operation respectively.
According to the embodiment, the synchronous clock frequency synthesis and synchronous triggering functions are realized according to the GPS pulse per second signal, and a plurality of synchronous reference clocks, synchronous triggering input and triggering output and control connection wiring among the synchronous reference clocks, the synchronous triggering input and the triggering output can be saved through interconnection among distributed systems. The wiring space is saved, the capacity of the whole system is increased, and the stability of the system is improved.
By using the topological structure of the optical fiber star network, the transmission bandwidth of the whole system is improved, and meanwhile, the number of data bus connecting wires is greatly reduced, so that the external interference probability of the bus is reduced, and the error rate of signal transmission is reduced.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Although the present disclosure has been described with reference to specific embodiments, it should be understood that the scope of the present disclosure is not limited thereto, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present disclosure.
Claims (9)
1. A simulation synchronization device based on a distributed MIMO channel is characterized in that: the digital phase detector comprises a digital phase detector, a loop filter, a D/A converter, a voltage-controlled oscillator and a frequency divider which are sequentially connected and form a closed loop, wherein the voltage-controlled oscillator outputs a frequency signal, the frequency divider feeds back local second pulse data, and GPS second pulses and the local second pulses are subjected to difference and then transmitted to the digital phase detector;
the GPS pulse-per-second signal is connected with the upper computer in a serial bus mode, the data format comprises world time, positioning state and/or longitude and latitude information, and the GPS pulse-per-second signal is used as a synchronous trigger signal;
the data transmission is realized by adopting a topological structure of a star network, absolute synchronization is required for optical fiber data transmission, data synchronization is realized among the data processing units by utilizing a channel simulation synchronization device, interconnection and intercommunication among a plurality of data processing units are realized by utilizing a high-speed data interaction module through a large-scale data interaction bus, so that baseband signals of other units obtained by each data processing unit are respectively subjected to matrix real-time operation.
2. The distributed MIMO based channel simulation synchronization apparatus of claim 1, wherein: the digital phase detector and the loop filter are realized by a field programmable gate array on the hardware level.
3. The distributed MIMO based channel simulation synchronization apparatus of claim 1, wherein: the voltage-controlled oscillator consists of a digital-to-analog converter controlled by a field programmable gate array and a voltage-controlled constant-temperature crystal oscillator.
4. A simulation synchronization system based on a distributed MIMO channel is characterized in that: the system comprises a plurality of distributed digital processing branches, wherein the digital processing branches are communicated through an interactive transmission bus;
each digital processing branch comprises a data processing unit and a data distributed control center which are sequentially connected, wherein the data processing unit and the data distributed control center are connected with the channel simulation synchronization device according to any one of claims 1-3 to realize data synchronization, the data distributed control center is used as a sending end to send a synchronization frame header when receiving a synchronization signal rising edge, the data processing unit receives data and starts caching through a multi-path buffer according to the analyzed multi-path input synchronization frame header, and when any one buffer reaches a set caching depth, the operation of reading the multi-path buffer is started.
5. The system of claim 4, wherein the system is based on distributed MIMO channel simulation synchronization, and comprises: the data processing unit comprises a plurality of V7, K7, a digital signal processing unit and a synchronous dynamic random access memory unit, the V7 is in two-way communication with each K7 to form a star-shaped framework, each K7 is communicated with a plurality of digital signal processing units and the synchronous dynamic random access memory unit, and the V7 is connected with a corresponding data distributed control center through a plurality of optical modules.
6. The system of claim 5, wherein the system is based on distributed MIMO channel simulation synchronization, and further comprising: at least one path of the multi-path optical module is connected to the radio frequency transceiving module.
7. The system of claim 5, wherein the system is based on distributed MIMO channel simulation synchronization, and further comprising: and the data distributed control centers are connected through an interactive transmission bus.
8. The method for operating a channel simulation synchronization system according to any of claims 4 to 7, wherein: the data processing units utilize a channel simulation synchronization device to realize data synchronization, the data distributed control center is used as a sending end to send a synchronization frame header when receiving a synchronization signal rising edge, the data processing units receive data and start caching through a multi-path buffer according to the analyzed multi-path input synchronization frame header, and when any buffer reaches a set caching depth, the operation of reading the multi-path buffer is started.
9. The method of operation of claim 8, wherein: the specific process of synchronization of the transmission data comprises the following steps: starting data transmission according to the edge of the synchronous trigger signal, taking the rising edge of the trigger signal as an example, when the rising edge of the synchronous signal arrives, the sending end sends N sections of synchronous protocol frame headers containing special characters, and the receiving end decodes the moment of the special characters after receiving the frame headers containing the special characters as the edge of the synchronous trigger signal to carry out data synchronization alignment operation.
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| CN102315927A (en) * | 2011-06-30 | 2012-01-11 | 大唐移动通信设备有限公司 | Clock synchronization device and method |
| CN103825696A (en) * | 2014-03-11 | 2014-05-28 | 华中科技大学 | Device for realizing high-speed real-time communication by optical fibers based on FPGA (Field Programmable Gate Array) |
| CN105337677A (en) * | 2015-11-17 | 2016-02-17 | 东南大学 | High-bandwidth large-scale MIMO channel simulation method and device |
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| US20140003564A1 (en) * | 2012-06-27 | 2014-01-02 | Broadcom Corporation | Multichip synchronization system |
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| CN1949691A (en) * | 2006-09-28 | 2007-04-18 | 哈尔滨工业大学 | Control method of MIMO channel simulator and implementing apparatus thereof |
| CN102315927A (en) * | 2011-06-30 | 2012-01-11 | 大唐移动通信设备有限公司 | Clock synchronization device and method |
| CN103825696A (en) * | 2014-03-11 | 2014-05-28 | 华中科技大学 | Device for realizing high-speed real-time communication by optical fibers based on FPGA (Field Programmable Gate Array) |
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