CN204272086U

CN204272086U - A kind of eye pattern sampling and reconstruction hardware circuit

Info

Publication number: CN204272086U
Application number: CN201420767874.5U
Authority: CN
Inventors: 周鹏
Original assignee: WUHAN PRECISE ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: WUHAN PRECISE ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2014-12-09
Filing date: 2014-12-09
Publication date: 2015-04-15
Anticipated expiration: 2024-12-09

Abstract

A kind of eye pattern sampling and reconstruction hardware circuit, it comprises sampling hold circuit, ADC drive circuit, ADC sample circuit, delay circuit, clock circuit, and sampling hold circuit is connected with needing the signal source module carrying out digitized processing; ADC drive circuit is series between ADC sample circuit and sampling hold circuit; The input of clock circuit is connected with signal source module, and for clock circuit provides homology clock, and the output of delay circuit and ADC sample circuit are electrical connected, to provide global clock and accurate delay clock.The purpose of this utility model be to provide a kind of there is antijamming capability is strong, circuit runs good stability and the high eye pattern sampling of analog-to-digital precision with rebuild hardware circuit, to solve existing sample circuit antijamming capability and circuit stability performance is poor, be difficult to the defect of the conversion accuracy guaranteed in AD conversion process.

Description

A kind of eye pattern sampling and reconstruction hardware circuit

Technical field

The utility model belongs to the field of measuring technique of communication transmission signal, is specifically related to the sampling of a kind of eye pattern and rebuilds hardware circuit.

Background technology

In modern communications transmission system, signal because a variety of causes can cause damage, is due to long transmission distance in a lot of situation or joint is aging causes signal attenuation in transmitting procedure, thus error code occurs.Eye pattern is the one measurement means very directly perceived, efficient of assessment serial digital signal quality.And along with the raising of signal rate, the sample rate of traditional oscillograph also cannot meet the demand of waveform reconstruction, and eye pattern is as the one measurement means very directly perceived, efficient of assessment serial digital signal quality, special eye Diagram Analysis instrument is made to become the only choosing of signal quality detection.

In eye Diagram Analysis instrument, Waveshape Collecting System is the most important link realizing eye pattern test, in high speed signal field, the accurate tracking of complete pair signals also ensures that enough sample rates need the sampling system of good design to realize, therefore, sampling clock delay circuit is the Key Circuit realizing system equivalent sampling.But, existing sample circuit, its circuit anti-interference ability and circuit stability performance poor, and sampling and data processing are difficult to realize synchronous, thus are difficult to guarantee the conversion accuracy in AD conversion process.

Utility model content

For solving the problems of the technologies described above, the purpose of this utility model be to provide a kind of there is antijamming capability is strong, circuit runs good stability and the high eye pattern sampling of analog-to-digital precision with rebuild hardware circuit, to solve existing sample circuit antijamming capability and circuit stability performance is poor, be difficult to the defect of the conversion accuracy guaranteed in AD conversion process.

For achieving the above object, a kind of eye pattern sampling and the reconstruction hardware circuit of the utility model, it is characterized in that: it comprises sampling hold circuit, ADC drive circuit, ADC sample circuit, delay circuit, clock circuit, described sampling hold circuit is connected with needing the signal source module carrying out digitized processing, for gathering simulation signal generator input voltage instantaneous value at a time, and during ADC sample circuit carries out analog-to-digital conversion, keep output voltage constant, for analog-to-digital conversion; Described ADC drive circuit is series between described ADC sample circuit and sampling hold circuit, single-ended signal for being gathered from signal source module by described sampling hold circuit is converted to differential signal, and signal is amplified, carry out analog-to-digital conversion for adc circuit; The input of described clock circuit is connected with described signal source module, and for described clock circuit provides homology clock, and the output of described delay circuit and described ADC sample circuit are electrical connected, to provide global clock and accurate delay clock.

On the basis of such scheme preferably, described eye pattern sampling further comprises a circuit for switching between two clocks with reconstruction hardware circuit, and this circuit for switching between two clocks is connected between described ADC sample circuit and delay circuit, for single-ended clock signal is converted to differential clock signal, to provide change over clock signal to adc circuit.

On the basis of such scheme preferably, described delay circuit comprises the LVTTL Clock generation module, the LVTTL that connect successively and turns LVPECL module and stepping time delay module able to programme.

On the basis of such scheme preferably, described stepping time delay module able to programme comprises interconnective stepping time delay module and delays time to control module, and described stepping time delay module and delays time to control module all turn LVPECL model calling with LVTTL.

On the basis of such scheme preferably, described eye pattern sampling also comprises the controller of a band display screen with rebuilding hardware circuit, described ADC sample circuit output is connected with described controller, and the output of described controller and described delay circuit are electrical connected.

The utility model compared with prior art, its beneficial effect is: a kind of eye pattern sampling of the present utility model and reconstruction hardware circuit, by ADC drive circuit, single-ended signal is converted to differential signal, by circuit for switching between two clocks, single-ended clock signal is converted to differential clock signal simultaneously, can greatly improve circuit anti-interference ability, improve the precision of AD conversion; Meanwhile, adopt unified clock source, and be equipped with stepping time-delay time base module, can ensure that each module synchronization carries out in order, improve circuit operational efficiency and stability.

Accompanying drawing explanation

Fig. 1 is a kind of eye pattern sampling of the present utility model and the structured flowchart rebuilding hardware circuit;

Fig. 2 is the structured flowchart of delay circuit of the present utility model.

Embodiment

By describe in detail the utility model technology contents, structural feature, reached object and effect, hereby exemplify embodiment below and coordinate accompanying drawing to be explained in detail.

Refer to shown in Fig. 1, and shown in composition graphs 2, the utility model provides a kind of eye pattern to sample and rebuilds hardware circuit, it is characterized in that: it comprises sampling hold circuit, ADC drive circuit, ADC sample circuit, delay circuit, clock circuit, described sampling hold circuit is connected with needing the signal source module carrying out digitized processing, for gathering simulation signal generator input voltage instantaneous value at a time, and during ADC sample circuit carries out analog-to-digital conversion, keep output voltage constant, for analog-to-digital conversion; Described ADC drive circuit is series between described ADC sample circuit and sampling hold circuit, single-ended signal for being gathered from signal source module by described sampling hold circuit is converted to differential signal, and signal is amplified, carry out analog-to-digital conversion for adc circuit; The input of described clock circuit is connected with described signal source module, and for described clock circuit provides homology clock, and the output of described delay circuit and described ADC sample circuit are electrical connected, to provide global clock and accurate delay clock.Preferably, eye pattern sampling of the present utility model also comprises a circuit for switching between two clocks with reconstruction hardware circuit, and this circuit for switching between two clocks is connected between ADC sample circuit and delay circuit, for single-ended clock signal is converted to differential clock signal, to provide change over clock signal to adc circuit.

Single-ended signal is converted to differential signal by ADC drive circuit by the present invention, by circuit for switching between two clocks, single-ended clock signal is converted to differential clock signal simultaneously, its objective is for improving circuit anti-interference ability, reduces noise, improves the precision of AD conversion.ADC sample circuit, ADC drive circuit and circuit for switching between two clocks are existing known technology, repeat no more here to its principle effect etc.Wherein, ADC sample circuit preferentially adopts high-resolution difference A/D chip, and model specifically can be selected to be one in AD9244, AD9445, AD7671 or AD7677.

Shown in Fig. 2, delay circuit of the present utility model comprises the LVTTL Clock generation module, the LVTTL that connect successively and turns LVPECL module and stepping time delay module able to programme, wherein, stepping time delay module able to programme comprises interconnective stepping time delay module and delays time to control module, and stepping time delay module and delays time to control module all turn LVPECL model calling with LVTTL.Wherein, LVTTL Clock generation module, for providing LVTTL level clock source, its inside have employed the VCTCXO crystal oscillator (voltage controlled temperature compensated crystal oscillator) of high stability, and during guarantee clock, base drift is little, ensure that the high accuracy of AD sampling and conversion; LVTTL turns LVPECL module for by LVTTL (Low Voltage TTL, low-voltag transistor-transistor logic) level conversion is LVPECL(Low Voltage Positive ECL, the emitter-coupled logic of low positive pressure) level, improve the transition response speed of level simultaneously and reduce the transmission delay of signal, it is even less that transmission delay can reach several ns; Stepping time delay module able to programme is used for providing global clock and accurate stepping delay clock.

On the basis of such scheme preferably, eye pattern sampling with rebuild hardware circuit and also comprise the controller of a band display screen, described ADC sample circuit output is connected with described controller, and the output of described controller and described delay circuit are electrical connected.

The present invention is equipped with delay circuit between AD sample circuit and signal source module, for providing global clock and provide accurate stepping delay clock in the analog-to-digital conversion course of work, to ensure that each functional circuit synchronously works in an orderly manner, the operational efficiency of effective raising circuit and stability, wherein, the work general principle of delay circuit is: the global clock (being provided by clock circuit) inputted outside by LVTTL Clock generation module is converted to LVTTL clock, LVTTL turns LVPECL module and raises speed to this clock, clock after speed-raising is sent to stepping time delay module on the one hand and inputs, be sent on the other hand delays time to control module to do time delay and synchronously trigger.The control of the controlled machine of delays time to control module, controller starts after the corresponding command is write delays time to control module and carries out time delay output to the input clock of stepping time delay module, the output signal of stepping time delay module is sent to controller, circuit for switching between two clocks and signal source module, ensure that each functional circuit synchronously works in an orderly manner, effectively can improve operational efficiency and the stability of circuit.

The utility model is by adopting high-resolution difference A/D chip, utilize ADC drive circuit that single-ended signal is converted to differential signal simultaneously, utilize circuit for switching between two clocks that single-ended clock signal is converted to differential signal, greatly can improve the antijamming capability of circuit, reduce noise, analog-to-digital precision is provided; In addition, additionally use unified clock source, and be equipped with delay circuit, ensure that each functional circuit synchronously works in an orderly manner, effectively improve operational efficiency and the stability of circuit.

In sum, be only the preferred embodiment of the utility model, do not limit protection range of the present utility model with this, all equivalence changes done according to the utility model the scope of the claims and description with modify, be all within scope that the utility model patent contains.

Claims

1. an eye pattern sampling and reconstruction hardware circuit, it is characterized in that: it comprises sampling hold circuit, ADC drive circuit, ADC sample circuit, delay circuit, clock circuit, described sampling hold circuit is connected with needing the signal source module carrying out digitized processing, for gathering simulation signal generator input voltage instantaneous value at a time, and during ADC sample circuit carries out analog-to-digital conversion, keep output voltage constant, for analog-to-digital conversion; Described ADC drive circuit is series between described ADC sample circuit and sampling hold circuit, single-ended signal for being gathered from signal source module by described sampling hold circuit is converted to differential signal, and signal is amplified, carry out analog-to-digital conversion for adc circuit; The input of described clock circuit is connected with described signal source module, and for described clock circuit provides homology clock, and the output of described delay circuit and described ADC sample circuit are electrical connected, to provide global clock and accurate delay clock.

2. a kind of eye pattern sampling as claimed in claim 1 and reconstruction hardware circuit, it is characterized in that: described eye pattern sampling further comprises a circuit for switching between two clocks with reconstruction hardware circuit, and this circuit for switching between two clocks is connected between described ADC sample circuit and delay circuit, for single-ended clock signal is converted to differential clock signal, to provide change over clock signal to adc circuit.

3. a kind of eye pattern sampling as claimed in claim 2 with rebuild hardware circuit, it is characterized in that: described delay circuit comprises the LVTTL Clock generation module, the LVTTL that connect successively and turns LVPECL module and stepping time delay module able to programme.

4. a kind of eye pattern sampling as claimed in claim 3 and reconstruction hardware circuit, it is characterized in that: described stepping time delay module able to programme comprises interconnective stepping time delay module and delays time to control module, and described stepping time delay module and delays time to control module all turn LVPECL model calling with LVTTL.

5. a kind of eye pattern sampling as claimed in claim 1 and reconstruction hardware circuit, it is characterized in that: described eye pattern sampling also comprises the controller of a band display screen with rebuilding hardware circuit, described ADC sample circuit output is connected with described controller, and the output of described controller and described delay circuit are electrical connected.