CN1630222A - Clock synchronization method and equipment in multi-signal multiplexing processing procedure - Google Patents
Clock synchronization method and equipment in multi-signal multiplexing processing procedure Download PDFInfo
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Abstract
This invention provides clock synchronous method and device in multiplex signal process, which checks the external and internal clock in multiplex signal process, determining the needed reference clock source according check result. Said invention guarantees the quality of reference clock source selected by multiplex signal process part and can select clock source according the priority of internal and external clock source of multiplex signal part avoiding clock looping to raise multiplex signal and whole network communication function.
Description
Technical field
The present invention relates to the network communications technology field, be specifically related to clock synchronizing method and device in a kind of many signal multiplexings processing procedure.
Background technology
In wave transmission system, the bandwidth particle of transmission signals is bigger, and in fact loaded service is the low speed service signal basically, comprises the multiple tributary signal such as SONET (synchronous optical network)/SDH (synchronous digital hierarchy) signal, GE (Gigabit Ethernet) signal, ATM (asynchronous digital series) signal of low speed.In order to improve the wavelength utilance, usually transmit at a wavelength a plurality of service signals are multiplexing in actual applications, therefore the service convergence unit has appearred.The major function of service convergence unit promptly is that the low speed service signal with a plurality of branch roads converges in the wavelength, carries out the transmission of signal via wave transmission system.
The process that the service convergence unit carries out many signal multiplexings is: converging direction, each service signal that receives is handled accordingly, recovered clock from each service signal, data-signal is become the signal that FG (framer) is fit to processing, and itself and each recovered clock transferred to framer together, framer carries out synchronous multiplexing to the multichannel service signal and becomes one road signal under the effect of a certain clock signal, carry out and go here and there processing such as conversion producing the service signal that is adapted at transmission among the DWDM (dense wavelength division system).It is opposite fully with the processing procedure that converges direction to separate the processing procedure that converges direction.
Because the service convergence unit need carry out multiplexing a plurality of low speed service signals, usually from different business networks, each business network to the clock source require inequality, the clock source of adopting is also not the same, especially when a plurality of low speed service signals during from the network of network of different nature or different operators, the clock source difference of each low speed service signal is especially obvious.Follow under the situation of different clock standards at this different low speed service signal, can not keep synchronously between each low speed service signal, how designing the synchronised clock that converges the unit handles, the low speed service signal that allow certain frequency difference, differs pools one road high speed signal, becomes the key that its function is realized in the service convergence unit.
The multi-service signal clock method for synchronous that solves the service convergence unit in the prior art is: place a local crystal oscillator in the service convergence unit, local crystal oscillator produces the clock signal of certain frequency, the clock processing module according to preset priority to local crystal oscillator and from low speed/high speed business signal recovered clock signal select, after the clock signal selected handled through certain frequency division, frequency multiplication etc., produce the required clock of service convergence each module of unit.Local crystal oscillator and from low/high speed business signal recovered clock signal be internal clocking.
Below we for an example that 2 STM-1 (synchronous transfer mode) signal and 1 GbE (gigabit Ethernet) signal gathering is become a STM-16 signal, as shown in Figure 1, further specify the clock synchronizing method of many signal multiplexings of prior art employing.
In Fig. 1, O/E is a photoelectric conversion module, and E/O is an electrooptic conversion module, and SerDes is serial/parallel, parallel/serial modular converter, and CDR is the clock and data recovery unit, and CMU is the clock Multiplexing Unit, and PP is that pointer is handled, FG is a framer.
The clock signal of recovered clock signal and local crystal oscillator generation in multipath high-speed and/or the low speed service signal is transferred to together the clock selector of clock processing module, clock selector is selected one tunnel clock signal according to preset priority and is transmitted it to frequency division/process of frequency multiplication module, and frequency division/process of frequency multiplication module produces the required reference clock signal of service convergence each module of unit according to the clock signal of selecting.
Adopt the clock synchronizing method of this multi-service signal multiplexing of prior art, need set in advance fixing priority, from a plurality of input clocks, select one road clock as reference clock source according to priority to the input reference clock source.Its specific implementation method is: clock selector is set, and general clock selector is that a multichannel is selected one selector, selects one tunnel clock signal as reference clock source from a plurality of clocks according to the preset priority rule.For example according to outside input clock, circuit input clock, branch road input clock port one, 2,3, local clock priority selective sequential one road clock from high to low as reference clock source.Because not having clock quality to detect in many signal multiplexings processing procedure handles, so after having selected one road reference clock, only break down in the module work of using this reference clock source, lost efficacy to reference clock source according to fault inquiry, and just the reference clock source that this module is used can be switched to clock priority and set lower clock.For example, the business that causes the receiving terminal of service convergence unit to receive owing to the inefficacy of reference clock source breaks down, lost efficacy to reference clock source according to fault inquiry, ability switches to the lower clock of priority level initializing with the reference clock source of the receiving terminal of service convergence unit.
The above-mentioned this method of choosing the clock source is not handled owing to there being clock quality to detect, can't guarantee the quality of the reference clock source selected, when having the clock quality deterioration of limit priority, still can select the clock signal of this quality deterioration as reference clock source according to preset priority.The multi-service signal multiplexing performance of reference clock source clock quality deterioration meeting deterioration service convergence unit, even the net synchronization capability of the whole communication network of meeting deterioration.
For the two-way communication situation between two service convergence unit, if separately high-speed line recovered clock is all chosen as reference clock source in two service convergence unit, the recovered clock of the high speed business signal that such two service convergence unit send just forms the situation of clock ring just each other as the other side's reference clock source.
Utilize prior art to select situation that reference clock source produces the clock ring as shown in Figure 2 for the service convergence unit, in Fig. 2, the high speed signal recovered clock that the framer of the framer selection service convergence unit B of service convergence unit A sends is as reference clock source, the high speed signal recovered clock that the framer of the framer selection service convergence unit A of service convergence unit B sends has so just formed clock ring phenomenon as reference clock source.When producing clock one-tenth ring phenomenon, can cause that the clock circuit anti-interference is poor, cause clock performance to descend.Utilize prior art when the Clock Managing Unit configuration service converges the reference clock source of unit, the reference clock source that require careful consideration, affirmation and service convergence unit has the module of other service convergence unit of data interaction to choose, just can avoid the problem of clock Cheng Huan, the layoutprocedure complexity.
In sum, adopt the clock synchronizing method of the multi-service signal multiplexing of prior art, in the service convergence unit each module all with same clock as reference clock source, for the module that requires the different accuracy reference clock in the service convergence unit, can not satisfy the demand of its clock accuracy.If present clock source clock signal quality deterioration, because not having clock quality to detect handles, in the service convergence unit each module still with this clock as the reference clock, multi-service signal multiplexing performance that will deterioration service convergence unit, even net synchronization capability that can the whole communication network of deterioration.
Summary of the invention
The objective of the invention is to, clock synchronizing method in a kind of many signal multiplexings processing procedure is provided, carry out the clock quality detection by each external clock and internal clocking to many signal multiplexings processing section, and by from external clock and internal clocking, determining reference clock source respectively for each required reference clock of many signal multiplexings processing section, to realize improving the clock configuration flexibility, improve many signal multiplexings performance, improve the purpose of the net synchronization capability of whole communication network.
For achieving the above object, clock synchronizing method comprises in a kind of many signal multiplexings processing procedure provided by the invention:
A, obtain all external clocks and the internal clocking of many signal multiplexings processing section;
B, detect described each external clock and internal clocking, and determine the priority of described each external clock and internal clocking according to testing result;
C, determine the reference clock source of described many signal multiplexings processing section according to the priority of described each external clock and internal clocking.
Described many signals comprise synchronous digital hierarchy signal, synchronous optical network signal, Gigabit Ethernet signal, asynchronous transfer mode signal;
Described many signal multiplexings processing section comprises the service convergence unit.
Described step b comprises:
Detect each external clock of described many signal multiplexings processing section and the clock quality of internal clocking in real time, and determine the priority of described each external clock and internal clocking according to the clock quality testing result.
Described step c comprises:
C1, determine each reference clock that described many signal multiplexings processing section needs;
C2, be respectively described each reference clock according to the priority of described each external clock and internal clocking and determine reference clock source.
Described step c2 comprises:
C21, according to the clock quality of each reference clock of described many signal multiplexings processing section needs with described each reference clock grouping, each reference clock group comprises one or more reference clocks;
C22, determine respectively to meet the clock that each reference clock group clock quality requires in described each external clock and the internal clocking according to the priority of described each external clock and internal clocking;
C23, respectively will the corresponding described reference clock source that meets the clock of each reference clock group clock quality requirement as each reference clock of described many signal multiplexings processing section.
Described step c22 comprises:
Described each external clock and internal clocking are carried out shaping, filtering, and in shaping, filtered each clock, determine to meet the clock that described each reference clock group clock quality requires according to the priority of described each external clock and internal clocking.
Described method also comprises:
With described each reference clock source carry out frequency division respectively as required, doubled clock offers described many signal multiplexings processing section.
Described method also comprises:
All external clocks and internal clocking according to clock characteristic information system one-to-many signal multiplexing processing section carry out sorting code number;
For the multiplexing of described many signal multiplexings processing section and become the reference clock source that frame module chooses coding should with this many signal multiplexings processing section other many signal multiplexings processing sections described multiplexing of data interaction arranged and becomes the coding of the reference clock source that frame module chooses different.
Described clock characteristic information comprises: clock priority, clock source, the positional information of many signal multiplexings processing section, wavelength information.
The present invention also provides clock synchronization apparatus in a kind of many signal multiplexings processing procedure, comprising:
Obtain clock module: obtain each external clock and the internal clocking of many signal multiplexings processing section, and described each external clock that obtains and internal clocking are transferred to definite clock priority module;
Determine the clock priority module: receive described described external clock and the internal clocking that the clock module transmission comes that obtain, detect described each external clock and internal clocking, determine the priority of described each clock according to testing result, and described each clock and its corresponding priorities transferred to determine the reference clock source module;
Determine the reference clock source module: determine each reference clock of described many signal multiplexings processing section needs, determine the reference clock source of described many signal multiplexings processing section according to each clock and its corresponding priorities of described definite clock priority module transmission.
Described definite reference clock source module comprises:
The clock processing sub: the clock of described definite clock priority module transmission is carried out shaping, filtering, and with shaping, filtered clock transfer to described definite clock submodule;
Determine the clock submodule: determine each reference clock that described many signal multiplexings processing section needs, from the clock that described clock processing sub transmission comes, determine to meet the clock of the clock quality that described each reference clock requires respectively and transmit it to and determine the reference clock source submodule;
Determine the reference clock source submodule: the clock and the corresponding clock priority thereof that meet the clock quality that described each reference clock requires that come according to described definite clock submodule transmission, respectively with the reference clock source of corresponding clock as each reference clock of described many signal multiplexings processing section.
Described device also comprises:
Coding module: described each clock and its corresponding priorities to described definite clock priority module transmission are encoded according to the clock characteristic information, and with described coding transmission to described definite reference clock source module.
From technique scheme, can obviously learn, the present invention carries out many signal multiplexings when handling in many signal multiplexings processing section, each external clock by detecting many signal multiplexings processing section and the clock quality of internal clocking, adjust described each external clock and internal clocking priority in real time, when the clock quality of the reference clock source of choosing descends, because clock quality detection scheme of the present invention, the clock signal that can not choose the clock quality deterioration has been guaranteed the clock quality of the reference clock that many signal multiplexings processing section is required as reference clock source.Simultaneously because the present invention unifies sorting code number according to the characteristic information of clock to each clock of many signal multiplexings processing section, when being many signal multiplexings processing section configuration reference clock source, can obviously learn with it other many signal multiplexings processing sections multiplexing of data interaction and the reference clock source that becomes frame module to choose are arranged, simplified to avoiding clock to become to encircle the process that disposes reference clock source, easily avoided the phenomenon of clock Cheng Huan.Technical scheme provided by the invention also can realize providing reference clock source separately to each reference clock of many signal multiplexings processing section, also can realize providing reference clock source separately, can realize equally providing a reference clock source all reference clocks of many signal multiplexings processing section to each reference clock group of many signal multiplexings processing section.Thereby can choose suitable reference clock source respectively according to the required precision of each reference clock/each reference clock group, requirement.Realize raising clock configuration flexibility, improved many signal multiplexings performance, improved the purpose of the net synchronization capability of whole communication network.
Description of drawings
Fig. 1 is the clock synchronization schematic diagram of the many signal multiplexings in service convergence unit of prior art;
Fig. 2 is that clock becomes the ring schematic diagram;
Fig. 3 is the clock synchronization schematic diagram of the many signal multiplexings in service convergence of the present invention unit;
Fig. 4 is the schematic diagram of the Clock Synchronization Technology scheme one of many signal multiplexings of the present invention;
Fig. 5 is the schematic diagram of the Clock Synchronization Technology scheme two of many signal multiplexings of the present invention;
Fig. 6 is the schematic diagram of the Clock Synchronization Technology scheme three of many signal multiplexings of the present invention;
Fig. 7 is the schematic diagram of the clock synchronization apparatus one of many signal multiplexings of the present invention;
Fig. 8 is the schematic diagram of the clock synchronization apparatus two of many signal multiplexings of the present invention.
Embodiment
Core of the present invention is to carry out many signal multiplexings in many signal multiplexings processing section when handling, all external clocks and internal clocking to many signal multiplexings processing section carry out clock detection, provide reference clock source according to the result of clock detection for many signal multiplexings processing section.
Based on the core concept of the invention described above, the present invention avoids the clock quality deterioration of reference clock source by the clock quality that detects each clock.Because clock synchronization is to the importance of many signal multiplexings processing section, so the present invention can adopt the clock synchronization quality to all external clocks and internal clocking to detect in real time, with the clock synchronization quality of the reference clock source guaranteeing to choose.
Clock synchronization quality testing of the present invention can realize according to following two kinds of methods:
First method: in the internal clocking from low/high speed business signal recovered clock signal, when many signal multiplexings processing section recovers to obtain clock signal from input signal, extract the clock synchronization quality information of describing this clock signal from input signal, the clock synchronization quality information that extracts from input signal has directly been described the clock synchronization credit rating of this clock.
Second method: reach the clock signal that from low/high speed business signal, recovers for the local crystal oscillator in external clock, the internal clocking, can determine the clock synchronization quality by detecting the clock performance parameter.The clock performance parameter can be chosen frequency deviation.Its implementation procedure is: for the many signal multiplexings processing section that obtains all inside, external timing signal, respectively to each clock signal counting, obtain the frequency difference of each clock, the i.e. frequency deviation of each clock according to count results with a predetermined nominal clock.Can determine the clock synchronization credit rating of each clock according to the frequency deviation of each clock.
For in the internal clocking from low/high speed business signal recovered clock signal, for guaranteeing clock synchronization quality testing result's reliability, we can combine use with above-mentioned two kinds of methods, promptly at first from input signal, extract the clock synchronization quality information of describing this clock signal, and then the clock signal of obtaining is carried out frequency deviation detect, determine the clock synchronization credit rating of each clock according to clock synchronization quality information and frequency deviation testing result.
The present invention can determine the priority of each clock signal according to the clock synchronization credit rating of each clock.For example, the clock synchronization quality of all external clocks and internal clocking is detected, determine that each clock synchronization quality has a, b, c, four grades of d, the clock that wherein satisfies the requirement of clock synchronization quality a level has a1, determines that the priority of an above-mentioned a1 clock is a level, and priority is the highest; Remove and satisfy the clock that clock synchronization quality b level requires behind the above-mentioned a1 clock and have b1, determine that the priority of b1 clock is the b level, priority is taken second place; Remove and satisfy the clock that clock synchronization quality c level requires behind a1, the b1 clock and have c1, determine that the priority of c1 clock is the c level, priority is more taken second place; Remove and satisfy the clock that clock synchronization quality d level requires behind a1, b1, the c1 clock and have d1, determine that the priority of d1 clock is the d level, priority is minimum.
Owing to the synchronizing quality requirement of the required reference clock of each module in many signal multiplexings processing section is different, in order to satisfy the different clocks quality requirement of different reference clocks, the present invention can provide reference clock source respectively to different reference clocks.For example continuous precedent, if module 1 needs reference clock to satisfy the requirement of a level synchronizing quality, the present invention can choose definite reference clock source from a1 the clock that clock priority is the highest; If module 2 needs reference clock to satisfy the requirement of b level synchronizing quality, the present invention can choose definite reference clock source from the clock that a1 the clock that clock priority is the highest and b1 clock priority take second place; In like manner, if module 3 needs reference clock to satisfy the requirement of c level synchronizing quality, choose definite reference clock source the clock that the clock that the present invention can take second place from a1 the clock that clock priority is the highest and b1 clock priority and c1 clock priority more take second place; And, can from the reference clock of a1 and b1 and c1 and d1 different priorities, choose reference clock source if module 4 needs reference clock to satisfy the requirement of d level synchronizing quality.
The present invention is by detecting the synchronizing quality information of each external clock of many signal multiplexings processing section, internal clock signal in real time, dynamically adjust the priority of each clock, can from a plurality of clocks that satisfy the synchronizing quality requirement, select reference clock source neatly, guarantee the quality of reference clock source.
Because the required reference clock in many signal multiplexings processing section is a plurality of, the required clock accuracy of each reference clock may be inequality, if with the reference clock source of same clock as each reference clock, then possibly can't satisfy the required precision of all reference clocks.The present invention can be respectively it reference clock source is provided according to the requirement of each reference clock, satisfied the required precision of each reference clock respectively.
The present invention can be implemented as each reference clock different reference clock sources is provided, also can require according to the synchronizing quality of each reference clock reference clock is divided into groups, be embodied as each reference clock group different reference clock sources is provided, each reference clock group can comprise a reference clock, also can comprise a plurality of reference clocks.When all reference clocks being divided into a group, the present invention has then realized providing same reference clock source to all reference clocks in the reference clock group.
For example continuous precedent, the step credit rating of will seeking common ground are that the reference clock of a level is divided into one group, and this reference clock group can be chosen definite reference clock source from priority is 1 grade clock; The step credit rating of will seeking common ground is that the reference clock of b level is divided into one group, and this reference clock group can be chosen definite reference clock source from priority is the clock of 1 grade and/or 2 grades.
After having determined reference clock source, each reference clock source is offered corresponding module in many signal multiplexings processing section after through processing such as frequency division, frequency multiplication, shapings according to the needs of its corresponding reference clock respectively.
The external clock that the present invention mentions can be provided with one or more high-precision external clocks according to the needs of many signal multiplexings processing section, to satisfy the requirement of many signal multiplexings processing section different clocks precision.
In the present embodiment, determined that the clock of different priorities can show as the form of clock priority configuring matrix, the clock priority configuring matrix be input as external clock and internal clocking, be output as the reference clock source that many signal multiplexings processing section needs, adopt the clock priority configuring matrix can make the selectable reference clock source of each module of many signal multiplexings processing section clear, thereby improved the flexibility of configuration reference clock source.
When configurable clock generator priority, can carry out unified sorting code number according to the clock characteristic information to it to each external clock and internal clocking, like this Clock management side can be easy to know the clock priority rank of the reference clock source of each module, from which input port, multiplexing and when becoming the reference clock source of frame module in configuration, can choose the clock clock synchronization quality that meets reference clock, that with it other many signal multiplexings processing sections multiplexing of data interaction arranged and become the reference clock source different coding that frame module chooses as reference clock source.
Sorting code number can be encoded according to the clock characteristic information.The clock characteristic information comprises clock priority, clock source, the positional information of many signal multiplexings processing section, wavelength information.Clock priority is determined according to the clock synchronization credit rating; The clock source is used for determining that clock is the clock of outside input clock signal or branch input signal recovered clock or kinds such as circuit input clock or local crystal oscillator reference clock, when certain kind has a plurality of clock signal, can various types of clock signal be numbered; The positional information of many signal multiplexings processing section is used for determining the location label of many signal multiplexings processing section in network; Wavelength information is used for representing line side, many signal multiplexings processing section data wavelength label.For example, certain clock signal be encoded to E12a3, its implication is the 3rd outside input clock signal in the outside input clock signal E kind of many signal multiplexings processing section of 1 for the location label in network, and the wavelength label is 2, clock priority is a level.Can find easily that by above-mentioned clock coding clock becomes the ring phenomenon, can in time tear ring open and handle clock Cheng Huan.
For example, setting the many signal multiplexings processing section location label of A in network is network element 1, the many signal multiplexings processing section location label of B in network is network element 2, supposing between two network elements has used wavelength 1 to communicate, and the FG module of service convergence unit A has selected for use the CDR clock recovered L1 of line input signal as reference clock source, this reference clock be encoded to L11a1, the FG module of many signal multiplexings processing section B has selected for use line input signal CDR clock recovered L1 as reference clock source, this reference clock is encoded to L21a1, the Clock management side can be according to many signal multiplexings processing section A, the coding of the reference clock source of the FG module of B is judged many signal multiplexings processing section A, B has formed the clock ring by wavelength 1, should tear ring open to this clock ring and handle.Like this, in simple and convenient realization in the process of configuration reference clock source, avoided the phenomenon of clock Cheng Huan easily; In like manner, when clock one-tenth ring occurring, the Clock management side is easy to find, is easy to correct.
Below in conjunction with accompanying drawing the present invention is described in further detail.
When many signal multiplexings processing section is the service convergence unit, we are same to lift one 2 STM-1 signals and 1 GbE signal gathering is become the example of a STM-16 signal, further specifies clock synchronizing method in many signal multiplexings processing procedure of the present invention's employing.As shown in Figure 3.
In Fig. 3, the clock signal isochronon signal that recovered clock signal and local crystal oscillator produce in external clock, the multichannel service signal transfers to clock synchronization apparatus of the present invention together, clock synchronization apparatus be you can well imagine clock for reference source for each reference clock/reference clock component, each reference clock source is passed through processing such as frequency division, frequency multiplication, shaping respectively according to the needs of reference clock, and the signal after will handling is as the required reference clock signal of each module of service convergence unit.By learning in the technique scheme that the required reference clock corresponding reference clock source of each module of service convergence unit can be inequality as required.
The Clock Synchronization Technology scheme one of the many signal multiplexings of realization of the present invention as shown in Figure 4.
In Fig. 4, obtain external clock, the clock signal isochronon signal that recovered clock signal and local crystal oscillator produce in the multichannel service signal, detect the clock synchronization quality of each clock signal in real time, determine the priority of each clock, priority according to each clock is arranged as the clock priority configuring matrix with each clock signal, from the clock priority configuring matrix, require to be respectively each reference clock/reference clock group reference clock source is provided according to the synchronizing quality of reference clock, each reference clock source is passed through frequency division respectively according to the needs of reference clock, frequency multiplication, processing such as shaping, and the signal after will handling is as the required reference clock of each module of service convergence unit.Can be inequality as required by the reference clock corresponding reference clock source that each module that can learn the service convergence unit in the technique scheme is required.
The Clock Synchronization Technology scheme two of the many signal multiplexings of realization of the present invention as shown in Figure 5.
In Fig. 5, at first obtain the clock signal that recovered clock signal in external clock, the multichannel service signal and local crystal oscillator produce, detect the clock synchronization quality of each clock signal in real time, determine the priority of each clock, priority according to each clock is arranged as clock priority configuring matrix 1 with each clock signal, then the clock signal in the clock priority configuring matrix 1 is carried out frequency division, frequency multiplication, driving processing.Clock signal and its corresponding priorities configurable clock generator priority configuring matrix 2 after the clock synchronization credit rating that requires according to each reference clock/each reference clock group will be handled, produce the reference clock source of each reference clock/each reference clock group by the clock priority configuring matrix 2 of each reference clock/each reference clock group, each reference clock source carries out processing such as frequency division, frequency multiplication, driving according to the needs of reference clock, and each clock signal after will handling is as the reference clock.
The Clock Synchronization Technology scheme three of the many signal multiplexings of realization of the present invention as shown in Figure 6.
In Fig. 6, at first obtain the clock signal that recovered clock signal in external clock, the multichannel service signal and local crystal oscillator produce, detect the clock synchronization quality of each clock signal in real time, determine the priority of each clock, priority according to each clock is arranged as clock priority configuring matrix 1 with each clock signal, then the clock signal in the clock priority configuring matrix 1 is carried out frequency division, frequency multiplication, driving processing.Clock signal after handling is carried out shaping according to the needs of each reference clock/each reference clock group, filtering, phase-locked processing, clock signal after the clock synchronization credit rating that requires according to each reference clock/each reference clock group will be handled is arranged as clock priority configuring matrix 2 according to its corresponding priorities, produce the reference clock source of each reference clock/each reference clock group by the clock priority configuring matrix 2 of each reference clock/each reference clock group, each reference clock source carries out frequency division according to the needs of reference clock, frequency multiplication, processing such as driving, and each clock signal after will handling is as the reference clock.
Can learn obviously that by above-mentioned three kinds of technical schemes technical scheme provided by the invention can realize providing reference clock source respectively to each reference clock of many signal multiplexings processing section.
The clock synchronization apparatus of signal multiplexing more than two kinds provided by the invention is shown in accompanying drawing 7,8.
In Fig. 7, the clock synchronization apparatus of many signal multiplexings comprises and obtains clock module 700, determines clock priority module 710, determines reference clock source module 720.The function of determining clock source module 720 by clock processing sub 721, determine clock submodule 722, determine that reference clock source submodule 723 realizes.
Obtain 1 road or multichannel external clock that clock module 700 obtains many signal multiplexings processing section, 1 road or the multichannel internal clocking, and each external clock that will obtain and internal clocking transfer to and determine clock priority module 710.
Determine that clock priority module 710 detects each synchronization of clock signals quality information in real time, and determine the priority of each clock each clock and its corresponding priorities to be transferred to clock processing sub 721 according to the synchronizing quality information of each clock signal correspondence.
Can illustrate at the function of obtaining clock module 700 and definite clock priority module 710:
Suppose the external clock 1, external clock 2, internal clocking 1, internal clocking 2, the internal clocking 3 that obtain clock module 700 and obtain many signal multiplexings processing section, and each clock is offered definite clock priority module 710.After determining that 710 pairs of above-mentioned 5 clocks of clock priority module carry out the clock synchronization quality testing in real time, determine that the priority of external clock 1 and internal clocking 1, internal clocking 2 is the highest, the priority of external clock 2, internal clocking 3 is minimum.Above-mentioned 5 clock signals and its corresponding priorities are transferred to clock processing sub 721.
Clock processing sub 721 will determine that the clock that clock priority module transmission comes carries out shaping, filtering according to the requirement of reference clock, and with shaping, filtered clock transfer to described definite clock submodule 722.
Determine that clock submodule 722 determines each reference clock that described many signal multiplexings processing sections need, from the clock that 721 transmission of clock processing sub come, determine to meet the clock that described each reference clock requires respectively and transmit it to and determine reference clock source submodule 723.Go on to say as follows at the function of determining clock submodule 722 according to top example: determine that the reference clock that clock submodule 722 definite many signal multiplexings processing sections need is reference clock 1, reference clock 2, reference clock 3, the clock synchronization of supposing reference clock 1 and reference clock 2 needs is identical in quality, so, determine that clock submodule 722 is defined as reference clock group 1 with reference clock 1 and reference clock 2, reference clock 3 is a reference clock group 2.Determine that clock submodule 722 is defined as satisfying the clock of the requirement of reference clock group 1 according to the needs of reference clock group 1 and reference clock group 2 with external clock 1, internal clocking 1, internal clocking 2, external clock 2, internal clocking 3 are defined as satisfying the clock of the requirement of reference clock group 2.With external clock 1,2, information and 5 clock signals that internal clocking 1,2,3 satisfies reference clock group 1 and reference clock group 2 respectively transfer to definite reference clock source submodule 723.
Determine that reference clock source submodule 723 is according to the clock and the corresponding clock priority thereof that meet described each reference clock/reference clock group requirement of determining that 722 transmission of clock submodule come, respectively with the reference clock source of corresponding clock as each reference clock of many signal multiplexings processing section.It is as follows to go on to say the function of determining reference clock source submodule 723 according to top example: according to determine clock that 722 transmission of clock submodule come and corresponding clock priority thereof respectively with external clock 1 as reference clock source with reference to clock group 1, with external clock 2 as reference clock source with reference to clock group 2.After the reference clock source of determining being carried out processing such as frequency division, frequency multiplication, shaping, transfer to many signal multiplexings processing section, as its reference clock.
In Fig. 8, the clock synchronization apparatus of many signal multiplexings comprises and obtains clock module 800, determines clock priority module 810, determines reference clock source module 820, coding module 830.The function of determining reference clock source module 820 by clock processing sub 821, determine clock submodule 822, determine that reference clock source submodule 823 realizes.
This device is to have increased coding module 830 on device shown in Figure 7.The function of this module is to receive each road clock signal of determining that 810 transmission of clock priority module come, and the clock signal that receives encoded according to the characteristic information of each clock, the coding of each clock signal, each clock signal is transferred to clock processing sub 821 with the form of clock priority matrix.
Though described the present invention by embodiment, those of ordinary skills know, the present invention has many distortion and variation and do not break away from spirit of the present invention, wishes that appended claim comprises these distortion and variation.
Claims (12)
1, clock synchronizing method in a kind of many signal multiplexings processing procedure is characterized in that comprising:
A, obtain all external clocks and the internal clocking of many signal multiplexings processing section;
B, detect described each external clock and internal clocking, and determine the priority of described each external clock and internal clocking according to testing result;
C, determine the reference clock source of described many signal multiplexings processing section according to the priority of described each external clock and internal clocking.
2, clock synchronizing method in a kind of many signal multiplexings processing procedure as claimed in claim 1 is characterized in that described many signals comprise synchronous digital hierarchy signal, synchronous optical network signal, Gigabit Ethernet signal, asynchronous transfer mode signal;
Described many signal multiplexings processing section comprises the service convergence unit.
3, clock synchronizing method in a kind of many signal multiplexings processing procedure as claimed in claim 1 or 2 is characterized in that described step b comprises:
Detect each external clock of described many signal multiplexings processing section and the clock quality of internal clocking in real time, and determine the priority of described each external clock and internal clocking according to the clock quality testing result.
4, clock synchronizing method in a kind of many signal multiplexings processing procedure as claimed in claim 3 is characterized in that described step c comprises:
C1, determine each reference clock that described many signal multiplexings processing section needs;
C2, be respectively described each reference clock according to the priority of described each external clock and internal clocking and determine reference clock source.
5, clock synchronizing method in a kind of many signal multiplexings processing procedure as claimed in claim 4 is characterized in that described step c2 comprises:
C21, according to the clock quality of each reference clock of described many signal multiplexings processing section needs with described each reference clock grouping, each reference clock group comprises one or more reference clocks;
C22, determine respectively to meet the clock that each reference clock group clock quality requires in described each external clock and the internal clocking according to the priority of described each external clock and internal clocking;
C23, respectively will the corresponding described reference clock source that meets the clock of each reference clock group clock quality requirement as each reference clock of described many signal multiplexings processing section.
6, clock synchronizing method in a kind of many signal multiplexings processing procedure as claimed in claim 5 is characterized in that described step c22 comprises:
Described each external clock and internal clocking are carried out shaping, filtering, and in shaping, filtered each clock, determine to meet the clock that described each reference clock group clock quality requires according to the priority of described each external clock and internal clocking.
7, clock synchronizing method in a kind of many signal multiplexings processing procedure as claimed in claim 1 or 2 is characterized in that described method also comprises:
With described each reference clock source carry out frequency division respectively as required, doubled clock offers described many signal multiplexings processing section.
8, clock synchronizing method in a kind of many signal multiplexings processing procedure as claimed in claim 1 or 2 is characterized in that described method also comprises:
All external clocks and internal clocking according to clock characteristic information system one-to-many signal multiplexing processing section carry out sorting code number;
For the multiplexing of described many signal multiplexings processing section and become the reference clock source that frame module chooses coding should with this many signal multiplexings processing section other many signal multiplexings processing sections multiplexing of data interaction arranged and becomes the coding of the reference clock source that frame module chooses different.
9, clock synchronizing method in a kind of many signal multiplexings processing procedure as claimed in claim 8 is characterized in that described clock characteristic information comprises: clock priority, clock source, the positional information of many signal multiplexings processing section, wavelength information.
10, clock synchronization apparatus in a kind of many signal multiplexings processing procedure is characterized in that described device comprises:
Obtain clock module: obtain each external clock and the internal clocking of many signal multiplexings processing section, and described each external clock that obtains and internal clocking are transferred to definite clock priority module;
Determine the clock priority module: receive described described external clock and the internal clocking that the clock module transmission comes that obtain, detect described each external clock and internal clocking, determine the priority of described each clock according to testing result, and described each clock and its corresponding priorities transferred to determine the reference clock source module;
Determine the reference clock source module: determine each reference clock of described many signal multiplexings processing section needs, determine the reference clock source of described many signal multiplexings processing section according to each clock and its corresponding priorities of described definite clock priority module transmission.
11, clock synchronization apparatus in a kind of many signal multiplexings processing procedure as claimed in claim 10 is characterized in that described definite reference clock source module comprises:
The clock processing sub: the clock of described definite clock priority module transmission is carried out shaping, filtering, and with shaping, filtered clock transfer to described definite clock submodule;
Determine the clock submodule: determine each reference clock that described many signal multiplexings processing section needs, from the clock that described clock processing sub transmission comes, determine to meet the clock of the clock quality that described each reference clock requires respectively and transmit it to and determine the reference clock source submodule;
Determine the reference clock source submodule: the clock and the corresponding clock priority thereof that meet the clock quality that described each reference clock requires that come according to described definite clock submodule transmission, respectively with the reference clock source of corresponding clock as each reference clock of described many signal multiplexings processing section.
12, clock synchronization apparatus in a kind of many signal multiplexings processing procedure as claimed in claim 10 is characterized in that described device also comprises:
Coding module: described each clock and its corresponding priorities to described definite clock priority module transmission are encoded according to the clock characteristic information, and with described coding transmission to described definite reference clock source module.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2003101241149A CN1302629C (en) | 2003-12-18 | 2003-12-18 | Clock synchronization method and equipment in multi-signal multiplexing processing procedure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101241149A CN1302629C (en) | 2003-12-18 | 2003-12-18 | Clock synchronization method and equipment in multi-signal multiplexing processing procedure |
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| CN1630222A true CN1630222A (en) | 2005-06-22 |
| CN1302629C CN1302629C (en) | 2007-02-28 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102006135A (en) * | 2010-12-03 | 2011-04-06 | 北京华环电子股份有限公司 | Method and device for selecting synchronous clock source |
| WO2013086833A1 (en) * | 2011-12-14 | 2013-06-20 | 中兴通讯股份有限公司 | Clock time synchronization source configuration method and device |
| CN103684902A (en) * | 2012-09-21 | 2014-03-26 | 阿尔特拉公司 | Apparatus and methods for determining latency of a network port |
| CN108616272A (en) * | 2018-05-15 | 2018-10-02 | 原时（荆门）电子科技有限公司 | A kind of high-precision low jitter time frequency signal switching device |
| CN109088635A (en) * | 2018-07-24 | 2018-12-25 | 北京航天控制仪器研究所 | A kind of multichannel clock synchronous |
| CN110572532A (en) * | 2019-07-17 | 2019-12-13 | 北京小鸟科技股份有限公司 | synchronization device for splicer and splicing processing system |
| CN111786741A (en) * | 2020-07-20 | 2020-10-16 | 哈尔滨海能达科技有限公司 | Clock synchronization method and related device for CPRI transmission data |
| CN109696822B (en) * | 2019-01-17 | 2021-01-01 | 西安电子科技大学 | Time signal switching system and switching method |
| CN114637370A (en) * | 2022-03-25 | 2022-06-17 | 北京中科飞鸿科技股份有限公司 | Circuit, device and method for switching internal and external different frequency reference clock signals |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3052922B2 (en) * | 1998-02-18 | 2000-06-19 | 日本電気株式会社 | COMMUNICATION TERMINAL DEVICE, ITS OPERATION CLOCK SELECTION METHOD, AND RECORDING MEDIUM RECORDING ITS CONTROL PROGRAM |
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- 2003-12-18 CN CNB2003101241149A patent/CN1302629C/en not_active Expired - Lifetime
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| CN102006135A (en) * | 2010-12-03 | 2011-04-06 | 北京华环电子股份有限公司 | Method and device for selecting synchronous clock source |
| WO2013086833A1 (en) * | 2011-12-14 | 2013-06-20 | 中兴通讯股份有限公司 | Clock time synchronization source configuration method and device |
| CN103684902A (en) * | 2012-09-21 | 2014-03-26 | 阿尔特拉公司 | Apparatus and methods for determining latency of a network port |
| CN103684902B (en) * | 2012-09-21 | 2018-05-01 | 阿尔特拉公司 | Apparatus and method for the delay for determining the network port |
| CN108616272A (en) * | 2018-05-15 | 2018-10-02 | 原时（荆门）电子科技有限公司 | A kind of high-precision low jitter time frequency signal switching device |
| CN109088635A (en) * | 2018-07-24 | 2018-12-25 | 北京航天控制仪器研究所 | A kind of multichannel clock synchronous |
| CN109696822B (en) * | 2019-01-17 | 2021-01-01 | 西安电子科技大学 | Time signal switching system and switching method |
| CN110572532A (en) * | 2019-07-17 | 2019-12-13 | 北京小鸟科技股份有限公司 | synchronization device for splicer and splicing processing system |
| CN110572532B (en) * | 2019-07-17 | 2021-12-14 | 北京小鸟科技股份有限公司 | Synchronization device for splicer and splicing processing system |
| CN111786741A (en) * | 2020-07-20 | 2020-10-16 | 哈尔滨海能达科技有限公司 | Clock synchronization method and related device for CPRI transmission data |
| CN114637370A (en) * | 2022-03-25 | 2022-06-17 | 北京中科飞鸿科技股份有限公司 | Circuit, device and method for switching internal and external different frequency reference clock signals |
| CN114637370B (en) * | 2022-03-25 | 2024-02-20 | 北京中科飞鸿科技股份有限公司 | Internal and external different frequency reference clock signal switching circuit, device and method |
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| CN1302629C (en) | 2007-02-28 |
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