CN201018421Y

CN201018421Y - Rectifier synchronous signal processing equipment

Info

Publication number: CN201018421Y
Application number: CNU2006201544278U
Authority: CN
Inventors: 黄赋光
Original assignee: Guangzhou Kinte Industrial Co Ltd
Current assignee: Guangzhou Kinte Industrial Co Ltd
Priority date: 2006-12-07
Filing date: 2006-12-07
Publication date: 2008-02-06
Anticipated expiration: 2016-12-07

Abstract

The utility model discloses a rectifier synchronous signal processing device which comprises a synchronous latch module, an AD sampling module and an FPGA chip for separating out fundamental component; wherein the input original synchronous signal is firstly latched through the latch module, the output signal of the latch module converts the analog quantity of the synchronous signal into the digital quantity through the AD sampling module, the synchronous signal converted into the digital quantity through the orderly three ways is inputted into the FPGA chip, the FPGA chip finally separates out the fundamental component from the synchronous signal, and the fundamental component is used as the synchronous signal of the rectifier. The utility model adopts the all-digital design, isn't influenced by the parameter change of the elements, the synchronous signal frequency, the environmental temperature and other uncertain factors, and has the strong adaptability.

Description

Rectifier synchronous signal processing device

Technical Field

The utility model relates to a rectifier synchronous signal processing apparatus.

Background

Synchronous thyristor rectifiers are currently widely used in a number of industries such as electrolysis, electroplating, electrical power, and the like. Its basic function is to convert ac power to dc output. The design and the control method of the synchronous thyristor rectifier circuit are basically established after years of development and improvement, but some places which are not ideal exist in the design and the control method. At present, all synchronous thyristor rectifiers in the market adopt an RC filter circuit and an operational amplifier to process synchronous signals. The RC filter circuit adopts one-stage filtering and multi-stage filtering, which are the same in nature, and a low-pass filter is expected to be designed to filter out high-frequency interference signals on the synchronous signals and obtain fundamental wave components in the synchronous signals. There are several problems among them:

1. the phase shift generated by the filter of the sinusoidal signals with different frequencies is not the same, and such a characteristic brings great troubles to the controller design of the rectifier.

2. Due to the drift of the device parameters of the RC filter circuit, the phase shift characteristics between the multiple RC circuits are also inconsistent, which affects the performance of the whole rectifier.

3. An RC filter circuit, particularly a filter circuit with a first-order structure, often cannot completely filter interference on a synchronization signal. Secondary processing must be performed in the commutation controller. Therefore, not only is the workload of software design increased, but also some uncertain factors are brought to the stability of the whole controller.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a can avoid receiving the rectifier synchronous signal processing apparatus that uncertain factors such as device parameter variation and synchronous signal frequency influence.

The purpose of the utility model can be realized by the following technical measures: a synchronous signal processing device of a rectifier comprises a synchronous latch module, an AD sampling module and an FPGA chip for separating fundamental wave components, wherein input original synchronous signals are latched by the latch module firstly, output signals of the latch module are converted into digital quantities by analog quantities of the synchronous signals after passing through the AD sampling module, the digital quantities are converted into synchronous signals of the digital quantities by three paths in sequence, and the synchronous signals are input into the FPGA chip, the FPGA chip separates the fundamental wave components from the synchronous signals finally, and the fundamental wave components are used as the synchronous signals of the rectifier.

FPGA chip be equipped with and be used for sending the AD sampling control timer of timing control order to latching the module, the FPGA chip latches three routes synchronizing signal through its control leg control synchronization latching module when the timer overflows.

FPGA chip in be equipped with and be used for carrying on Fourier transform and acquire the digital signal processor of fundamental wave weight.

The utility model discloses a FPGA chip utilizes its corresponding control pin control AD sampling module's multi-way switch, makes it select three routes synchronizing signal's each way signal in proper order, then the FPGA chip pushes in a first-in first-out buffer to the value after three routes synchronizing signal obtains the sampling, utilizes the data in the buffer to calculate, can obtain the fundamental wave component among the synchronizing signal.

The utility model can be used as a part of the whole thyristor rectification controller, and the whole controller is arranged in an FPGA chip, thus effectively reducing the area of the circuit board and the number of elements and obviously reducing the cost; simultaneously, the utility model discloses an adopt full digital design, can not receive the influence of uncertain factors such as device parameter variation, synchronizing signal frequency, ambient temperature, have very strong adaptability.

Drawings

FIG. 1 is a schematic block diagram of the present invention;

FIG. 2 is a schematic circuit diagram of the synchronous latch module of the present invention;

fig. 3 is a schematic circuit diagram of the AD sampling module of the present invention;

FIG. 4 is a schematic diagram of the FPGA chip of the present invention;

FIG. 5 is a schematic diagram of an input signal containing harmonic interference;

fig. 6 is a schematic diagram of a fundamental wave signal obtained through fourier transform processing.

Detailed Description

As shown in fig. 1, the utility model discloses the hardware part is including the synchronous latch module, AD sampling module and the FPGA chip that is used for isolating the fundamental wave component, the original synchronizing signal of input is at first latched through the latch module, the output signal of latch module converts the analog quantity of synchronizing signal to the digital quantity behind the AD sampling module, the synchronizing signal who converts the digital quantity into through dividing three routes in proper order inputs the FPGA chip, the fundamental wave component is isolated from this synchronizing signal at last to the FPGA chip, and regard this fundamental wave component as the synchronizing signal of rectifier.

FPGA chip be equipped with and be used for carrying on Fourier transform and acquire the digital signal processor of fundamental wave component, according to Fourier algorithm's requirement, the sampling point must will be surveyed signal N partition in a cycle. As shown in fig. 2 and fig. 3, an AD sampling control timer is disposed in the FPGA chip, and when the timer overflows, the FPGA controls the U3001, the U3004, and the U3007 in the latch module to latch the three paths of synchronization signals through the nHold0 pin. As shown in FIG. 3, the FPGA chip then controls an one-out-of-eight multiplexer U3102 in the AD sampling module via the MUX0_ CON [0 ] pin, selecting one of the three synchronization signals to be sent to the Vin pin of the 16-bit AD sampling chip U3104. Next, as shown in fig. 3 and 4, the FPGA chip converts this analog quantity into a digital quantity through the ADC0_ nBusy, ADC0_ nCS, and ADC0_ RnC pins of the control U3104. When the AD sampling module finishes conversion, the FPGA reads the conversion result through ADC _ D [0 ]. The FPGA controls the multi-way switch to select another path of synchronous signals for sampling through a MUX0_ CON [0 ] pin until all three-phase synchronous signals are sampled.

The Fourier transform algorithm of the utility model is as follows:

according to the discrete fourier transform, a periodic sequence x (N) with an arbitrary period N, whose exponential form of the fourier sequence is as follows:

where { Ck } is a parameter of the sequence, k =0,1,2, \ 8230;, N-1.

From the expressions (1) and (2), in the sequence x (n), the fundamental component f1 (n) is:

the following is the algorithm simulation result obtained by Matlab, wherein as shown in fig. 5, the analog input original synchronization signal contains 6 th harmonic harmonics and dc component interference, and the equation is:

b＝Sin(2πt)+0.5Sin(6×2πt)+0.5

where the Sin (2 π t) moiety is the fundamental component.

As shown in fig. 6, the fundamental component obtained by fourier transform extraction shows that the two algorithms are completely matched.

The FPGA chip pushes a value sampled by the AD sampling module into a first-in first-out buffer area, data in the buffer area is used for calculation according to the formula (3), so that a fundamental component in the synchronous signal can be obtained, and the fundamental component is used as the synchronous signal of the rectifier.

Claims

1. A rectifier synchronous signal processing device is characterized in that: the FPGA chip comprises a synchronous latch module, an AD sampling module and an FPGA chip for separating fundamental wave components, wherein input original synchronous signals are latched by the latch module firstly, output signals of the latch module are converted into digital quantity from analog quantity of the synchronous signals after passing through the AD sampling module, the digital quantity converted from the analog quantity of the synchronous signals are input into the FPGA chip, and the FPGA chip separates the fundamental wave components from the synchronous signals finally.

2. The synchronization signal processing apparatus according to claim 1, wherein: the FPGA chip is provided with an AD sampling control timer used for sending timing control commands to the latch module.

3. The synchronization signal processing apparatus according to claim 1, wherein: the FPGA chip is provided with a digital signal processor for carrying out Fourier transform to obtain a fundamental component.

4. The synchronization signal processing apparatus according to claim 1, wherein: the AD sampling module is provided with a multi-way switch for sequentially selecting each way of signals in the three ways of synchronous signals to sample.