CN116192126A - Delay phase-locked loop and memory - Google Patents
Delay phase-locked loop and memory Download PDFInfo
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Abstract
The invention provides a delay phase-locked loop, comprising: the preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal and output a plurality of frequency division clock signals; the plurality of adjustable delay lines are configured to respectively adjust and transmit each frequency division clock signal and output a plurality of delay clock signals; and the post-processing module is configured to post-process the plurality of delayed clock signals and output a target clock signal, the frequency of the target clock signal is equal to that of the initial clock signal, and the phase of the target clock signal is the same as that of the initial clock signal. The delay phase-locked loop provided by the application realizes the frequency reduction of an external clock in the loop, and increases the clock pulse width in the loop, thereby improving the noise immunity of the system and the working frequency. The invention also provides a memory.
Description
Technical Field
The invention belongs to the technical field of semiconductor memories, and particularly relates to a delay locked loop and a memory.
Background
Delay locked loops (delay locked loop, DLLs) are a circuit structure commonly used in computer operating environments to generate the required clocks to control the accurate transfer of instructions and data from, for example, dynamic Random Access Memory (DRAM) to an external chipset or control Chip (CPU).
When a clock signal is transmitted to and/or from an internal controller in a DRAM, the clock signal is delayed due to line loads, logic circuits, and other blocks therein. Therefore, there is a phase difference between the external clock signal and the internal clock signal generated inside the DRAM. In order to synchronize the internal clock signal with the external clock signal, the DLL is used to compensate for the phase difference, thereby synchronizing the data output signal from the DRAM with the external clock signal. The DLL circuit is mainly used for adjusting the output clock signal of the DRAM to align the output clock signal with the external input clock signal.
In the related art, the operating frequency in the DLL loop coincides with the external clock. However, as the frequency of the external clock signal increases, the narrower pulse width thereof is more susceptible to PVT (process/voltage/temperature), noise, and other non-ideal factors, thereby causing clock signal loss.
Therefore, it is very necessary to study a delay locked loop adapted to the high-frequency working environment, so as to further promote the deep development and wide application of the semiconductor memory technology.
Disclosure of Invention
The invention aims to solve all or part of the problems in the prior art, and provides a delay phase-locked loop which can adapt to a high-frequency working environment.
The invention provides a delay phase-locked loop, comprising: the preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal and output a plurality of frequency division clock signals; the plurality of adjustable delay lines are configured to respectively adjust and transmit each frequency division clock signal and output a plurality of delay clock signals; and the post-processing module is configured to post-process the plurality of delayed clock signals and output a target clock signal, the frequency of the target clock signal is equal to that of the initial clock signal, and the phase of the target clock signal is the same as that of the initial clock signal. The method comprises the steps of firstly performing frequency-reducing processing on an initial clock signal, respectively adjusting and transmitting a plurality of clock signals after the frequency-reducing processing, and then performing post-processing on a delayed clock signal to obtain a complete signal. Therefore, the problems of clock missing or too narrow pulse width in the initial clock signal can be effectively avoided.
The delay locked loop further comprises: a control module configured to generate a delay line control signal; the adjustable delay line is specifically configured to receive the delay line control signal, adjust and transmit each frequency division clock signal based on the delay line control signal, and output a delay clock signal. Therefore, based on the delay line control signal, the adjustable delay line can adjust each frequency division clock signal in multiple aspects, and the duty ratio and the phase of the target clock signal are ensured to meet the requirements.
The control module includes: a feedback module configured to receive the divided clock signal, and output a feedback clock signal based on a predetermined amount modeled by the delay component; the detection module is configured to receive the initial clock signal and the feedback clock signal, and perform phase detection on the feedback clock signal and the initial clock signal to obtain a phase detection signal; and the parameter adjusting module is configured to receive the phase detection signal and output the delay line control signal based on the phase detection signal.
The control module is used for generating a delay control signal based on a frequency division clock signal, and the plurality of adjustable delay lines are adjusted based on the delay control signal to generate a plurality of delay clock signals. The occupied area of the control module is effectively reduced, and the integration level is increased.
The delay locked loop further comprises: and the intermediate processing module is configured to perform intermediate processing on the plurality of frequency division clock signals and output an intermediate clock signal, wherein the intermediate clock signal is input to the feedback module, and the frequency of the intermediate clock signal is equal to that of the initial clock signal. Therefore, the intermediate processing module enables the frequencies of the feedback clock signal and the initial clock signal to be equal, and is convenient for the detection of the phase discrimination module. The working environment of the phase detection module is the same as that of the phase detection module without adopting the preprocessing module for frequency reduction in the related technology, so that the variable is reduced, and the yield is improved.
The feedback module is configured to respectively receive a plurality of frequency division clock signals and correspondingly output a plurality of feedback clock signals; the detection module is configured to respectively perform phase detection on the feedback clock signals and correspondingly output a plurality of phase detection signals; the parameter adjusting module is configured to respectively receive a plurality of phase detection signals and output a plurality of corresponding delay line control signals based on each phase detection signal; the adjustable delay lines are specifically configured to correspondingly receive a plurality of delay line control signals, adjust and transmit each frequency division clock signal based on each delay line control signal, and correspondingly output a plurality of delay clock signals. In this way, mismatch between the multiple adjustable delay lines can be eliminated. And a plurality of frequency division clock signals can be synchronously adjusted and phase-locked through the control module, so that the efficiency is high.
The delay locked loop further comprises: the multiplexer is configured to transmit a plurality of frequency division clock signals to the control module, and the plurality of frequency division clock signals sequentially pass through the control module to respectively generate a plurality of corresponding delay line control signals. By arranging the multiplexer, the occupied area of the feedback module can be effectively reduced.
The preprocessing module comprises: the receiving module is configured to receive the initial clock signal and output a clock signal to be processed; wherein the clock period of the clock signal to be processed is the same as the clock period of the initial clock signal; the first conversion module is configured to receive the clock signal to be processed, perform frequency division processing on the clock signal to be processed and output a plurality of frequency division clock signals.
The post-processing module includes: the second conversion module is configured to receive a plurality of the delayed clock signals, perform frequency multiplication processing on the delayed clock signals and output a plurality of frequency multiplication clock signals; and the off-chip driving module is configured to receive the frequency multiplication target clock signal and output the target clock signal. Here, the frequency multiplication processing means to combine a plurality of delayed clock signals to output a frequency-multiplied clock signal. Thus, the frequency multiplication processing is prevented from being carried out on one delay clock signal, and the signal distortion is avoided. The off-chip driving module can be used for adjusting the voltage of the I/O interface end to compensate the pull-up resistance value and the pull-down resistance value, so that the synchronization between the target clock signal and DQ data is adjusted to ensure the integrity and the reliability of the signal.
The preprocessing module is configured to output a differential pair of divided clock signals. The signal anti-interference and noise reduction effects of the frequency division clock signal differential pair are better.
The invention also provides a memory, which comprises the delay phase-locked loop.
Compared with the prior art, the invention has the main beneficial effects that:
the delay phase-locked loop provided by the application realizes the frequency reduction of an external clock in the loop, and increases the clock pulse width in the loop, thereby improving the noise immunity of the system and the working frequency.
Drawings
Fig. 1 is a block diagram of a delay locked loop in the related art;
FIG. 2 is a signal timing diagram of clock signals of each link in a clock signal transmission process in the related art;
fig. 3 is a schematic structural diagram of a delay locked loop according to the present invention;
FIG. 4 is a signal timing diagram of differential pairs of an initial clock signal and a divided clock signal;
fig. 5 is a schematic structural diagram of another delay locked loop according to the present invention;
fig. 6 is a schematic diagram of a delay locked loop according to another embodiment of the present invention;
fig. 7 is a schematic diagram of a memory according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully, and it is apparent that the embodiments described are only some, but not all, of the embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a block diagram (DLL BlockDigram) of a delay locked loop in the related art, as shown in fig. 1, the delay locked loop includes a receiver RCV, an adjustable delay line, a feedback module Replica (Feedback), an Off-Chip Driver (OCD), a phase detector, and a Control unit Control Units. The combination (Mixer) of the duty cycle adjustment module DCC (Duty cycle correction), coarse Delay module Coarse Delay, and Fine Delay module Fine Delay forms an adjustable Delay line. Taking the delay locked loop in DDR4 as an example here.
In a read operation, DDR4 needs to provide a target clock signal DQS, and when DQS and an initial clock signal VCLK have a large phase difference, the CPU may capture erroneous data. The DLL needs to keep the phases of the target clock signal DQS and the initial clock signal VCLK aligned. The feedback module Replica (Feedback) functions to replicate the real delay in the signal transmission path, e.g., the delay of the off-chip driver module OCD located after the DLL, adding the effect of the OCD on the clock signal to the DLL so that the target clock signal DQS may be phase aligned with the external clock signal VCLK.
The phase detector identifies the phase difference between the initial clock signal and the feedback clock signal; the Control unit Control Units make a Control strategy to Control the DCC and the feedback module according to the output result of the phase detector PhaseDetector, the DCC adjusts the duty ratio of the initial clock signal VCLK, the adjustable delay line delays the initial clock signal VCLK to change the phase, the signals form delay signals after being delayed, and the delay signals are delayed by the feedback module to obtain feedback clock signals. The control unit controls the DCC and the adjustable delay line to increase or decrease the length of the delay line to realize the same phase of the initial clock signal and the feedback clock signal, which is also called phase locking, so as to ensure that the CPU accurately grabs the data output by the DRAM.
Fig. 2 is a timing diagram of clock signals of each link in a related art clock signal transmission process. Referring to fig. 1, when an external chipset or control Chip (CPU) clock signal is Input (Input CLK), the external clock signal VCLK passes through the receiver RCV to generate an intermediate delay signal clk_i, and the receiver delay time is tRCV. The intermediate delay signal clk_i generates the delay signal dqs_i after passing through an adjustable delay line having a delay time tDLL. The delayed signal dqs_i generates the target clock signal VDQS after passing through the off-chip driving module OCD, and the off-chip driving module OCD has a delay time tcocd. The target clock signal VDQS is finally input to an output clock signal DQS of an external chipset or a control Chip (CPU) after phase locking.
However, as the frequency of the external clock signal increases, the narrower pulse width thereof is more susceptible to non-ideal factors such as PVT, noise, etc., thereby causing clock signal loss.
Based on this, referring to fig. 3, the present invention provides a delay locked loop 30, comprising: a preprocessing module 31 configured to receive an initial clock signal, preprocess the clock signal, and output a plurality of divided clock signals, the frequency of the divided clock signal being smaller than the frequency of the initial clock signal; a plurality of adjustable delay lines 32 configured to adjust and transmit each divided clock signal, respectively, and output a plurality of delayed clock signals; the post-processing module 33 is configured to post-process the plurality of delayed clock signals and output a target clock signal, wherein the frequency of the target clock signal is equal to the frequency of the initial clock signal, and the phase of the target clock signal is the same as the phase of the initial clock signal. The method comprises the steps of firstly performing frequency-reducing processing on an initial clock signal, respectively adjusting and transmitting a plurality of clock signals after the frequency-reducing processing, and then performing post-processing on a delayed clock signal to obtain a complete signal. Therefore, the problems of clock missing or too narrow pulse width in the initial clock signal can be effectively avoided. Here, the frequencies of the plurality of divided clock signals may be the same, and the phases may be the same. The number of adjustable delay lines 32 is equal to the number of divided clock signals.
The preprocessing module 31 includes: a receiving module 311 configured to receive an initial clock signal and output a clock signal to be processed; the clock period of the clock signal to be processed is the same as the clock period of the initial clock signal; the first conversion module 312 is configured to receive a clock signal to be processed, perform frequency division processing on the clock signal to be processed, and output a plurality of frequency division clock signals.
The initial clock signal is an external clock signal, and may be, for example, a clock signal input by an external chipset or a control Chip (CPU). In some embodiments, the frequency of the initial clock signal is greater than or equal to 1.6Ghz. The data transmission speed under the high-frequency signal is high, the bandwidth is large, and the communication of data is facilitated.
In actual operation, the initial clock signal can be a differential clock signal, the differential clock signal has strong anti-interference capability, electromagnetic interference can be effectively inhibited, and the time sequence positioning is accurate.
The first conversion module 312 includes a frequency divider, which may be, for example, a frequency divider. As shown in fig. 4, the preprocessing module 31 is specifically configured to output a divided clock signal differential pair. The first divided clock signal clk_even and the second divided clock signal clk_odd are respectively generated by dividing the initial clock signal clk by two to generate positive and negative differential clock signals, i.e., two divided clock signals. The first divided clock signal and the second divided clock signal have the same amplitude and opposite phases. In actual operation, the differential pair signal generated by the two frequency division has better anti-interference and noise reduction effects.
For ease of understanding, the conversion of the initial clock signal into the first divided clock signal clk_even and the second divided clock signal clk_odd is described below in a divide-by-two manner.
As shown in fig. 3, the delay locked loop further includes: a control module 34 configured to generate a delay line control signal; the adjustable delay line 32 is specifically configured to receive the delay line control signal, adjust and transmit each divided clock signal based on the delay line control signal, and output a delayed clock signal. Therefore, based on the delay line control signal, the adjustable delay line can adjust each frequency division clock signal in multiple aspects, and the phase of the target clock signal is ensured to meet the requirements.
Accordingly, as shown in FIG. 3, the control module 34 includes: a feedback module 341 configured to receive the divided clock signal, and output a feedback clock signal based on a predetermined amount modeled by the delay component; the detection module 342 is configured to receive the initial clock signal and the feedback clock signal, and perform phase detection on the initial clock signal and the feedback clock signal to obtain a phase detection signal; the parameter tuning module 343 is configured to receive the phase detection signal and output a delay line control signal based on the phase detection signal. Here, the actual delay that occurs after the initial clock signal passes through the entire transmission path is based on a predetermined amount modeled by the delay component.
It should be noted that, waveforms of the initial clock signal and the target clock signal need to be consistent, and thus a feedback adjustment mechanism needs to be constructed. Specifically, the frequency-divided clock signal obtained after the initial clock signal is preprocessed is passed through the feedback module 341 to generate an analog clock signal, and since the analog clock signal can simulate a waveform of the initial clock signal after passing through the entire transmission path, the delay line control signal is adjusted according to a difference between the analog clock signal and the initial clock signal, so as to adjust the working parameter of the adjustable delay line.
In some embodiments, referring to fig. 3, feedback module 341 is configured to receive a divided clock signal and output a feedback clock signal. Specifically, after the initial clock signal is converted into the first divided clock signal clk_even and the second divided clock signal clk_odd by the preprocessing module 31, for example, the first divided clock signal clk_even may be transmitted to the feedback module 341 to output the feedback clock signal. After receiving the feedback clock signal and the initial clock signal, the detection module 342 performs phase detection on the initial clock signal and the feedback clock signal to obtain a phase detection signal. After receiving the phase detection signals, the parameter adjusting module outputs delay line control signals to each adjustable delay line 32. In this way, the control module generates a delay control signal based on a frequency division clock signal, the plurality of adjustable delay lines adjust based on the delay control signal to generate a plurality of delay clock signals, and the delay clock signals output the target clock signals after passing through the post-processing module. Therefore, the occupied area of the control module is effectively reduced, and the integration level is increased. It should be appreciated that the frequency of the feedback clock signal and the first divided clock signal clk even are the same, the frequency of the feedback signal being half of the initial clock signal. After the detection module 342 receives the feedback clock signal and the initial clock signal, the phase discrimination module samples the initial clock signal using the rising edge of the feedback clock signal to determine the phase lead or lag of the initial clock signal. The phase detection module is insensitive to the frequency difference between the feedback clock signal and the initial clock signal, since it is based only on the rising edge of the feedback clock signal.
Referring to fig. 3, the post-processing module 33 includes: the second conversion module 331 is configured to receive a plurality of delayed clock signals, perform frequency multiplication processing on the delayed clock signals, and output frequency-multiplied clock signals; the off-chip driving module 332 is configured to receive the multiplied target clock signal and output the target clock signal.
The second conversion module corresponds to the first conversion module such that the frequency of the multiplied clock signal is equal to the frequency of the initial clock signal. For example, the first conversion module is a frequency divider, and the second conversion module is a frequency divider.
It should be understood that the frequency multiplication processing herein refers to combining a plurality of delayed clock signals to output a frequency-multiplied clock signal. Thus, the frequency multiplication processing is prevented from being carried out on one delay clock signal, and the signal distortion is avoided.
The off-chip driver module 332 may be configured to adjust the voltage at the I/O interface to compensate for the pull-up and pull-down resistance values, thereby adjusting the synchronization between the target clock signal and DQ data to ensure signal integrity and reliability.
In some embodiments, as shown in fig. 5, the delay locked loop further includes: the intermediate processing module 35 is configured to perform intermediate processing on the plurality of divided clock signals, output an intermediate clock signal, and input the intermediate clock signal to the feedback module 341, where the frequency of the intermediate clock signal is equal to the frequency of the initial clock signal.
The intermediate processing module here corresponds to the first conversion module such that the frequency of the intermediate clock signal is equal to the frequency of the initial clock signal. For example, the first conversion module is a frequency divider, and the intermediate processing module is a frequency divider.
Therefore, the intermediate processing module enables the frequencies of the feedback clock signal and the initial clock signal to be equal, and is convenient for the detection of the phase discrimination module. The working environment of the phase detection module is the same as that of the phase detection module without adopting the preprocessing module for frequency reduction in the related technology, so that the variable is reduced, and the yield is improved.
It should be noted that, in the above scheme, the adopted control module generates a delay control signal based on a frequency division clock signal, and the plurality of adjustable delay lines adjust based on the delay control signal to generate a plurality of delay clock signals. The occupied area of the control module is effectively reduced, and the integration level is increased. However, in actual production, there is a mismatch between the plurality of adjustable delay lines, the delay times generated by the plurality of adjustable delay lines cannot be completely equal, and the periodic jitter of the signal caused by the mismatch between the plurality of delay lines cannot be eliminated by adjusting based on one delay control signal. Taking the differential pair of output divided clock signals as an example, the mismatch of the dual adjustable delay lines in the phase-locked loop causes periodic jitter of the output clock, which is essentially that the dual adjustable delay lines share the same delay control signal, so that the dual adjustable delay lines cannot adapt to a single adjustable delay line. Based on this, the present application further provides a delay locked loop, referring to fig. 6, the feedback module 341 is configured to receive a plurality of divided clock signals respectively, and correspondingly output a plurality of feedback clock signals; the detection module is configured to respectively perform phase detection on the feedback clock signals and correspondingly output a plurality of phase detection signals; the parameter adjusting module is configured to respectively receive a plurality of phase detection signals and output a plurality of corresponding delay line control signals based on each phase detection signal; the plurality of adjustable delay lines are specifically configured to correspondingly receive a plurality of delay line control signals, adjust and transmit each frequency division clock signal based on each delay line control signal, and correspondingly output a plurality of delay clock signals.
In actual operation, the feedback module 341 includes a plurality of sub-feedback modules (not shown) for respectively receiving a plurality of divided clock signals, and each sub-feedback module receives a divided clock signal and correspondingly outputs a plurality of feedback clock signals. The detection module 342 includes a plurality of sub-detection modules 3421 for performing phase detection on the feedback clock signal, and each sub-detection module 3421 performs phase detection on a feedback clock signal and outputs a plurality of phase detection signals correspondingly. The parameter tuning module 343 includes a plurality of sub parameter tuning modules 3431 for respectively receiving a plurality of phase detection signals and outputting a corresponding plurality of delay line control signals based on each phase detection signal. In this way, mismatch between the multiple adjustable delay lines can be eliminated. And a plurality of frequency division clock signals can be synchronously adjusted and phase-locked through the control module, so that the efficiency is high.
In some embodiments, referring to fig. 6, the delay locked loop further comprises: the multiplexer 36 is configured to transmit a plurality of divided clock signals to the control module, and the plurality of divided clock signals sequentially pass through the control module to generate a plurality of corresponding delay line control signals, respectively. By arranging the multiplexer, the occupied area of the feedback module can be effectively reduced. In order to eliminate the mismatch between the plurality of adjustable delay lines, the number of the sub-tuning modules, the sub-detection modules and the sub-feedback modules needs to be the same as the number of the adjustable delay lines. By arranging the multiplexer, only one sub-feedback module is needed, so that the occupied area of the feedback module is greatly reduced. In actual operation, the first frequency-division clock signal is transmitted to the feedback module through an adjustable delay line and a multiplexer, and the generated feedback module signal is further transmitted to the sub-detection module and the sub-parameter-adjusting module to generate a corresponding delay line control signal, and the delay line control signal adjusts the corresponding adjustable delay line to carry out adjustment phase locking. After phase locking is finished, the multiplexer switches signal transmission, the second frequency division clock signal is transmitted to the feedback module through the other adjustable delay line and the multiplexer, the generated feedback module signal is transmitted to the other sub-detection module and the other sub-parameter adjustment module to generate a corresponding delay line control signal, and the delay line control signal adjusts the corresponding adjustable delay line to carry out adjustment phase locking. In this way, after two locks are made, the mismatch between the two adjustable delay lines can be eliminated. Meanwhile, the occupied area of the feedback module is greatly reduced, and clock periodic jitter caused by mismatch among a plurality of sub-feedback modules is avoided.
The present invention also provides a memory, see fig. 7, wherein the memory 40 comprises the delay locked loop 30 described above. It should be noted that the delay locked loop of the embodiments of the present disclosure may be applied to, but not limited to, memories, such as DRAM, SDRAM, and the like. In other analog circuits or digital circuits, the delay locked loop provided by the invention can be used for generating a target clock signal.
In summary, the present invention provides a delay locked loop, comprising: the preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal and output a plurality of frequency division clock signals, and the frequency of the frequency division clock signals is smaller than that of the initial clock signal; the plurality of adjustable delay lines are configured to respectively adjust and transmit each frequency division clock signal and output a plurality of delay clock signals; and the post-processing module is configured to post-process the plurality of delayed clock signals and output a target clock signal, wherein the frequency of the target clock signal is equal to that of the initial clock signal. The delay phase-locked loop provided by the application realizes the frequency reduction of an external clock in the loop, and increases the clock pulse width in the loop, thereby improving the noise immunity of the system and the working frequency.
The use of certain conventional english terms or letters for the sake of clarity of description of the invention is intended to be exemplary only and not limiting of the interpretation or particular use, and should not be taken to limit the scope of the invention in terms of its possible chinese translations or specific letters. It should also be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Specific examples are set forth herein to illustrate the structure and principles of the invention, and the above examples are provided only to assist in understanding the methods and core concepts of the invention. It should be noted that it will be apparent to those skilled in the art that various improvements and modifications can be made to the present invention without departing from the principles of the invention, and such improvements and modifications fall within the scope of the appended claims.
Claims (10)
1. A delay locked loop comprising:
the preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal and output a plurality of frequency division clock signals;
the plurality of adjustable delay lines are configured to respectively adjust and transmit each frequency division clock signal and output a plurality of delay clock signals;
and the post-processing module is configured to post-process the plurality of delayed clock signals and output a target clock signal, the frequency of the target clock signal is equal to that of the initial clock signal, and the phase of the target clock signal is the same as that of the initial clock signal.
2. The delay locked loop of claim 1, wherein the delay locked loop further comprises:
a control module configured to generate a delay line control signal;
the adjustable delay line is specifically configured to receive the delay line control signal, adjust and transmit each frequency division clock signal based on the delay line control signal, and output a delay clock signal.
3. The delay locked loop of claim 2, wherein the control module comprises:
a feedback module configured to receive the divided clock signal, and output a feedback clock signal based on a predetermined amount modeled by the delay component;
the detection module is configured to receive the initial clock signal and the feedback clock signal, and perform phase detection on the initial clock signal and the feedback clock signal to obtain a phase detection signal;
and the parameter adjusting module is configured to receive the phase detection signal and output the delay line control signal based on the phase detection signal.
4. A delay locked loop as claimed in claim 3, further comprising:
and the intermediate processing module is configured to perform intermediate processing on the plurality of frequency division clock signals and output an intermediate clock signal, wherein the intermediate clock signal is input to the feedback module, and the frequency of the intermediate clock signal is equal to that of the initial clock signal.
5. A delay locked loop as defined in claim 3, wherein,
the feedback module is configured to respectively receive a plurality of frequency division clock signals and correspondingly output a plurality of feedback clock signals;
the detection module is configured to respectively perform phase detection on the feedback clock signals and correspondingly output a plurality of phase detection signals;
the parameter adjusting module is configured to respectively receive a plurality of phase detection signals and output a plurality of corresponding delay line control signals based on each phase detection signal;
the adjustable delay lines are specifically configured to correspondingly receive a plurality of delay line control signals, adjust and transmit each frequency division clock signal based on each delay line control signal, and correspondingly output a plurality of delay clock signals.
6. The delay locked loop of claim 5, further comprising:
the multiplexer is configured to transmit a plurality of frequency division clock signals to the control module, and the plurality of frequency division clock signals sequentially pass through the control module to respectively generate a plurality of corresponding delay line control signals.
7. The delay locked loop of claim 1, wherein the preprocessing module comprises:
the receiving module is configured to receive the initial clock signal and output a clock signal to be processed; wherein the clock period of the clock signal to be processed is the same as the clock period of the initial clock signal;
the first conversion module is configured to receive the clock signal to be processed, perform frequency division processing on the clock signal to be processed and output a plurality of frequency division clock signals.
8. The delay locked loop of claim 1, wherein the post-processing module comprises:
the second conversion module is configured to receive a plurality of the delayed clock signals, perform frequency multiplication processing on the delayed clock signals and output a plurality of frequency multiplication clock signals;
and the off-chip driving module is configured to receive the frequency multiplication target clock signal and output the target clock signal.
9. The delay locked loop of claim 1, wherein,
the preprocessing module is configured to output a differential pair of divided clock signals.
10. A memory comprising a delay locked loop as claimed in any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310061921.8A CN116192126A (en) | 2023-01-13 | 2023-01-13 | Delay phase-locked loop and memory |
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| CN202310061921.8A CN116192126A (en) | 2023-01-13 | 2023-01-13 | Delay phase-locked loop and memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116743155A (en) * | 2023-08-14 | 2023-09-12 | 浙江力积存储科技有限公司 | Delay phase-locked loop and memory |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6304117B1 (en) * | 1997-07-29 | 2001-10-16 | Fujitsu Limited | Variable delay circuit and semiconductor integrated circuit device |
| CN101764608A (en) * | 2008-12-25 | 2010-06-30 | 北京芯技佳易微电子科技有限公司 | Bit-by-bit approaching delay phase-locked loop circuit and method for regulating input clock signal |
| US20180068699A1 (en) * | 2015-10-28 | 2018-03-08 | Samsung Electronics Co., Ltd. | Delay-locked loop circuit and semiconductor memory device including the same |
| CN113541680A (en) * | 2020-04-22 | 2021-10-22 | 三星电子株式会社 | Delay locked loop circuit and semiconductor memory device having the same |
| CN115065359A (en) * | 2022-08-11 | 2022-09-16 | 睿力集成电路有限公司 | Delay phase-locked loop, clock synchronization circuit and memory |
-
2023
- 2023-01-13 CN CN202310061921.8A patent/CN116192126A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6304117B1 (en) * | 1997-07-29 | 2001-10-16 | Fujitsu Limited | Variable delay circuit and semiconductor integrated circuit device |
| CN101764608A (en) * | 2008-12-25 | 2010-06-30 | 北京芯技佳易微电子科技有限公司 | Bit-by-bit approaching delay phase-locked loop circuit and method for regulating input clock signal |
| US20180068699A1 (en) * | 2015-10-28 | 2018-03-08 | Samsung Electronics Co., Ltd. | Delay-locked loop circuit and semiconductor memory device including the same |
| CN113541680A (en) * | 2020-04-22 | 2021-10-22 | 三星电子株式会社 | Delay locked loop circuit and semiconductor memory device having the same |
| CN115065359A (en) * | 2022-08-11 | 2022-09-16 | 睿力集成电路有限公司 | Delay phase-locked loop, clock synchronization circuit and memory |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116743155A (en) * | 2023-08-14 | 2023-09-12 | 浙江力积存储科技有限公司 | Delay phase-locked loop and memory |
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