CN105676943A - I/Q demodulation clock circuit in SoC chip - Google Patents
I/Q demodulation clock circuit in SoC chip Download PDFInfo
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- CN105676943A CN105676943A CN201511033927.6A CN201511033927A CN105676943A CN 105676943 A CN105676943 A CN 105676943A CN 201511033927 A CN201511033927 A CN 201511033927A CN 105676943 A CN105676943 A CN 105676943A
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- module
- counter
- time delay
- circuit
- soc chip
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
- H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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- Pulse Circuits (AREA)
Abstract
The invention discloses an I/Q demodulation clock circuit in an SoC chip. The I/Q demodulation clock circuit comprises an I clock generating circuit, a delay module and a counter and control circuit module; the delay module comprises multiple branch switches and delay units, the output end of the I clock generating circuit is connected to the delay units through the branch switches, the multiple delay units are sequentially connected in series and output to the input end of the counter and control circuit module, and the output end of the counter and control circuit module is connected with control ends of the multiple branch switches. Circuit operation power consumption is reduced by adopting the branch switches, and the delay module is used for adjusting the phase, so that it is unnecessary to improve the work frequency or additionally arrange a phase correction module, bandwidth limitation is avoided, the circuit is simple in structure and can be simplified and optimized through the method of module reuse, redundancy part clipping and the like, and the cost of chip obtaining is reduced. The I/Q demodulation clock circuit and method in the SoC chip can be widely applied to electronic circuit field.
Description
Technical field
The present invention relates to electronic circuit field, I/Q demodulation clock circuit in especially a kind of SoC chip.
Background technology
SoC is the abbreviation of SystemonChip, i.e. SOC(system on a chip). As its name suggests, be exactly by system core part, as microprocessor, Analog IP core, digital IP kernel and memory etc., be integrated on one chip. Numerous integrated circuit set with specific function, to chip piece, make SoC chip have the advantages such as small-sized, light weight, multi-functional, high-speed and low cost, are widely used in communication, traffic, the fields such as logistics.
Barkhausen criterion is the primary condition of guaranteeing loop oscillation, and the loop gain of negative-feedback circuit must meet the following conditions:
In the time that the loop gain of negative-feedback circuit meets above-mentioned condition, loop can produce vibration, otherwise, can not.
I/Q modulates (orthogonal modulation), is that signal source is divided into two parts, modulates respectively with carrier wave, and two carrier signals intersect. I/Q demodulation is to need equally two crossing carrier signals to carry out demodulation. I/Q modulation /demodulation is widely used in radiofrequency signal phase control system, radar, the application such as base station receiver. In I/Q modem procedue, two crossing carrier signals, we are referred to as i/q signal, and the circuit main method that present stage produces i/q signal has, two frequency sharing circuits, polyphase structure RC wave filter etc.
Two frequency sharing circuits are exactly by trigger or other circuit structures, make 1 periodic signal of 2 periodic circuit output of the every triggering of signal, and signal frequency is reduced by half. Therefore use two frequency sharing circuits to produce the common circuit of orthogonal signalling and need to be operated on the circuit working signal of twice, and need to carry out phasing to improve precision.
Polyphase structure RC wave filter mainly utilize resistance be connected with capacitive cross form ring, this structure is limited to bandwidth, and signal has decay. Concrete required capacitance resistance number need to be determined according to operating frequency simultaneously, is not easy to proofread and correct.
Summary of the invention
In order to solve the problems of the technologies described above, the object of the invention is: I/Q demodulation clock circuit simple in structure, easy to control in a kind of SoC chip, low-power consumption is provided.
The technical solution adopted in the present invention is: I/Q demodulation clock circuit in a kind of SoC chip, include I clock generation circuit, time delay module sum counter and control circuit module, described time delay module includes many group time delay branch roads, described time delay branch road includes branch switch and delay unit, the output of described I clock generation circuit is connected to delay unit by branch switch, delay unit in described many group time delay branch roads is connected successively, the delay unit output of last group time delay branch road in described many group time delay branch roads is connected to the input of counter and control circuit module, described counter is connected with the branch switch control end of many groups time delay branch road respectively with the output of control circuit module.
Further, described counter and control circuit module include:
Register, for storing control information;
Counter, counts for the number of the delay unit in running order;
Time delay module reset cell, for the duty of the delay unit of resetting;
Whether phasing unit, carry out phasing for controlling;
Preset count unit, for memory counter preset value;
Mode of operation control module, dynamically adjusts according to the work of counter preset value or according to the count value of counter for controlling time delay module.
Further, described mode of operation control module is used for controlling time delay module while working according to counter preset value, and described mode of operation control module is controlled respectively the branch switch in many group time delay branch roads according to counter preset value.
Further, when described mode of operation control module is dynamically adjusted according to the count value of counter for controlling time delay module, the branch switch that the control of described mode of operation control module is organized in time delay branch road more is opened successively until the input input signal of counter and control circuit module and the output signal of I clock generation circuit are reverse.
Further, the storing control information in described register includes 1 reset position, 1 bit correction position, 1 mode of operation position and 4 digit counter presetting bits.
Further, described time delay module includes 30 groups of time delay branch roads.
Further, described I clock generation circuit produces the oscillating current of 13.56MHz.
The invention has the beneficial effects as follows: adopt branch switch to reduce circuit operation power consumption, utilize time delay module to adjust phase place, therefore this circuit structure is without improving operating frequency and adding phase correction module, and without limit bandwidth, circuit structure is simple and can be simplified circuit and be optimized by methods such as module reuse, redundancy section cuttings, reduces chip and realizes cost.
Brief description of the drawings
Fig. 1 is electrical block diagram of the present invention;
Fig. 2 is counter and the control circuit modular circuit schematic diagram of the present invention's one specific embodiment.
Detailed description of the invention
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further:
With reference to Fig. 1, I/Q demodulation clock circuit in a kind of SoC chip, include I clock generation circuit, time delay module sum counter and control circuit module, described time delay module includes many group time delay branch roads, described time delay branch road includes branch switch and delay unit, the output of described I clock generation circuit is connected to delay unit by branch switch, delay unit in described many group time delay branch roads is connected successively, the delay unit output of last group time delay branch road in described many group time delay branch roads is connected to the input of counter and control circuit module, described counter is connected with the branch switch control end of many groups time delay branch road respectively with the output of control circuit module.
The groundwork flow process that circuit of the present invention produces I/Q clock is, utilizes the equivalent circuit of crystal oscillator to produce stable I clock, simultaneously the initial clock using the I clock that produces as Q clock. Constantly add delay unit counting to Q clock, the phase difference of Q clock and I clock is constantly increased, whether reverse by judging the input signal of input of counter and control circuit module, I/Q clock skew reaches 180 °. Now counter result just can be obtained to I/Q clock phase divided by 2 and differ 90 ° of needed delay unit numbers if phase difference reaches 180 °. In circuit, realizing divided by 2 function is mainly by the realization that moves to right of the result of register. Suppose to obtain 90 ° of required delay unit number n of phase phasic difference, can obtain for initial Q clock adds n delay unit the Q clock that differs 90 ° with I clock phase. And at this moment the control circuit of top receives whether I/Q clock skew reaches the feedback of 180 °, control circuit no longer increases delay unit number, and the constant phase difference of I/Q clock is at 90 °.
Be further used as preferred embodiment, described counter and control circuit module include:
Register, for storing control information;
Counter, counts for the number of the delay unit in running order;
Time delay module reset cell, for the duty of the delay unit of resetting;
Whether phasing unit, carry out phasing for controlling;
Preset count unit, for memory counter preset value;
Mode of operation control module, dynamically adjusts according to the work of counter preset value or according to the count value of counter for controlling time delay module.
In above-mentioned counter and control circuit module, each unit can be realized with simple selector and d type flip flop, and the schematic diagram of one of them specific implementation circuit as shown in Figure 2; Mode of operation control module, according to counter result, is realized and is utilized the data of 5 bit register positions to control the break-make of 30 delay units by multiple two input nand gates and nor gate.
Be further used as preferred embodiment, described mode of operation control module is used for controlling time delay module while working according to counter preset value, and described mode of operation control module is controlled respectively the branch switch in many group time delay branch roads according to counter preset value; Be preset value to make delay unit number just in time make I/Q clock skew be 90 °, and needn't adjust again in the later stage.
Be further used as preferred embodiment, when described mode of operation control module is dynamically adjusted according to the count value of counter for controlling time delay module, the branch switch that the control of described mode of operation control module is organized in time delay branch road more is opened successively until the input input signal of counter and control circuit module and the output signal of I clock generation circuit are reverse, and this is clock calibration process. In process, important intermediate parameters is to judge whether I/Q clock skew exceedes the parameters C lock180Deg of 180 °; In the time that I/Q clock skew exceedes 180 °, Clock180Deg is 1, otherwise is 0; In the time that Clock180Deg is 1, controlling counting module and reducing by half, add on former Q clock, produce I/Q clock and differ from differing 180 ° and become and differ 90 °, can be used as counter preset value.
Be further used as preferred embodiment, the storing control information in described register includes 1 reset position, 1 bit correction position, 1 mode of operation position and 4 digit counter presetting bits.
Reset position (position of resetting, 1): if 1, delay unit number is reset;
On-Off position (correction bit, 1): if 1, phase place is not proofreaied and correct, and the delay unit number of resetting, making delay unit lattice count perseverance is 0; If 0, allow phase place to proofread and correct;
CountOrNot position (mode of operation position, 1): if 1, delay unit number is directly set to the value arranging in ClockDelay register, and delay unit is not increased progressively to processing; If 0, allow delay unit number constantly to increase progressively, increase the phase difference between I/Q clock.
ClockDelay position (counter presetting bit, 4): for memory counter preset value. Preset value is directly set when this function is mainly considered chip production, and to make delay unit number just in time make I/Q clock skew be 90 °, and needn't adjust in the later stage again.
Be further used as preferred embodiment, described time delay module includes 30 groups of time delay branch roads.
Be further used as preferred embodiment, described I clock generation circuit produces the oscillating current of 13.56MHz.
More than that better enforcement of the present invention is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art can also make all equivalents or replacement under the prerequisite without prejudice to spirit of the present invention, and the distortion that these are equal to or replacement are all included in the application's claim limited range.
Claims (7)
1. I/Q demodulation clock circuit in a SoC chip, it is characterized in that: include I clock generation circuit, time delay module sum counter and control circuit module, described time delay module includes many group time delay branch roads, described time delay branch road includes branch switch and delay unit, the output of described I clock generation circuit is connected to delay unit by branch switch, delay unit in described many group time delay branch roads is connected successively, the delay unit output of last group time delay branch road in described many group time delay branch roads is connected to the input of counter and control circuit module, described counter is connected with the branch switch control end of many groups time delay branch road respectively with the output of control circuit module.
2. I/Q demodulation clock circuit in a kind of SoC chip according to claim 1, is characterized in that: described counter and control circuit module include:
Register, for storing control information;
Counter, counts for the number of the delay unit in running order;
Time delay module reset cell, for the duty of the delay unit of resetting;
Whether phasing unit, carry out phasing for controlling;
Preset count unit, for memory counter preset value;
Mode of operation control module, dynamically adjusts according to the work of counter preset value or according to the count value of counter for controlling time delay module.
3. I/Q demodulation clock circuit in a kind of SoC chip according to claim 2, it is characterized in that: described mode of operation control module is used for controlling time delay module while working according to counter preset value, described mode of operation control module is controlled respectively the branch switch in many group time delay branch roads according to counter preset value.
4. I/Q demodulation clock circuit in a kind of SoC chip according to claim 2, it is characterized in that: when described mode of operation control module is dynamically adjusted according to the count value of counter for controlling time delay module, the branch switch that the control of described mode of operation control module is organized in time delay branch road more is opened successively until the input input signal of counter and control circuit module and the output signal of I clock generation circuit are reverse.
5. I/Q demodulation clock circuit in a kind of SoC chip according to claim 2, is characterized in that: the storing control information in described register includes 1 reset position, 1 bit correction position, 1 mode of operation position and 4 digit counter presetting bits.
6. I/Q demodulation clock circuit in a kind of SoC chip according to claim 1, is characterized in that: described time delay module includes 30 groups of time delay branch roads.
7. I/Q demodulation clock circuit in a kind of SoC chip according to claim 1, is characterized in that: described I clock generation circuit produces the oscillating current of 13.56MHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511033927.6A CN105676943B (en) | 2015-12-31 | 2015-12-31 | I/Q demodulation clock circuits in a kind of SoC chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201511033927.6A CN105676943B (en) | 2015-12-31 | 2015-12-31 | I/Q demodulation clock circuits in a kind of SoC chip |
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| CN105676943A true CN105676943A (en) | 2016-06-15 |
| CN105676943B CN105676943B (en) | 2018-08-17 |
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| CN201511033927.6A Expired - Fee Related CN105676943B (en) | 2015-12-31 | 2015-12-31 | I/Q demodulation clock circuits in a kind of SoC chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106767745A (en) * | 2016-12-09 | 2017-05-31 | 清华大学 | A kind of signal processing method of photoelectric sensor angle measuring system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| FI104450B (en) * | 1997-10-09 | 2000-01-31 | Nokia Networks Oy | Method and circuitry for compensating for delay in power amplifier linearization loop |
| JP3636657B2 (en) * | 2000-12-21 | 2005-04-06 | Ｎｅｃエレクトロニクス株式会社 | Clock and data recovery circuit and clock control method thereof |
| JP4030482B2 (en) * | 2003-08-18 | 2008-01-09 | シャープ株式会社 | I / Q demodulation circuit |
| CN101527564B (en) * | 2008-03-06 | 2012-07-18 | 瑞昱半导体股份有限公司 | Fractional-neuronal frequency divider and method thereof |
| CN101989848A (en) * | 2009-08-03 | 2011-03-23 | 杭州国芯科技股份有限公司 | Clock generating circuit |
| CN101640524B (en) * | 2009-08-27 | 2011-08-10 | 四川和芯微电子股份有限公司 | Spread spectrum clock generating circuit |
| CN103427798B (en) * | 2013-08-21 | 2016-06-22 | 电子科技大学 | A kind of multiphase clock generation circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106767745A (en) * | 2016-12-09 | 2017-05-31 | 清华大学 | A kind of signal processing method of photoelectric sensor angle measuring system |
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Granted publication date: 20180817 Termination date: 20201231 |