CN101814916B - Phase-locked loop - Google Patents
Phase-locked loop Download PDFInfo
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- CN101814916B CN101814916B CN2010100338700A CN201010033870A CN101814916B CN 101814916 B CN101814916 B CN 101814916B CN 2010100338700 A CN2010100338700 A CN 2010100338700A CN 201010033870 A CN201010033870 A CN 201010033870A CN 101814916 B CN101814916 B CN 101814916B
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Abstract
The invention discloses a phase-locked loop. The phase-locked loop comprises a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, bonding-wire inductor, a buffer, a prescaler and a digital frequency divider, wherein the input end of the phase/frequency detector is connected with the output end of the digital frequency divider and a reference clock; the input end of the charge pump is connected with the output end of the phase/frequency detector; the input end of the loop filter is connected with the output end of the charge pump; the voltage-controlled oscillator uses a resistor as an electro-static discharge guard; the control voltage input end of the voltage-controlled oscillator is connected with the output end of the loop filter; the bonding-wire inductor is connected with the differential output end of the voltage-controlled oscillator; the differential input end of the buffer is connected to the differential output end of the voltage-controlled oscillator; the prescaler is controlled by Gray codes; the differential signal input end of the prescaler is connected with the differential output end of the buffer; the control signal input end of the prescaler is connected with a first output end of a control logic; a signal input end of the digital frequency divider is connected with an output end of the prescaler; and a control input end of the digital frequency divider is connected with a second output end of the control logic. The phase-locked loop provided by the invention has the advantages of high frequency precision and low noise.
Description
Technical field
The present invention relates to the PHASE-LOCKED LOOP PLL TECHNIQUE field, particularly a kind of have the pre-divider of Gray code control and a phase-locked loop of the voltage controlled oscillator that resistance is ESD.
Background technology
In radio frequency transceiver, phase-locked loop is the core of whole system often.In transmitter, phase-locked loop is used to frequency synthesizer and produces and to transmit or up-conversion transmits, and the frequency accuracy of phase-locked loop and phase noise have directly determined the Error Vector Magnitude that transmits; In receiver, phase-locked loop often is used to produce the local oscillation signal of down-conversion, and the frequency accuracy of phase-locked loop influences demodulation bit error rate, and the phase noise of phase-locked loop directly determines the adjacent rank channel selectivity of receiver.
About the pre-divider in the phase-locked loop, be to improve frequency characteristic, traditional method is to adopt subtracter control phase selector to realize, for example, adopts subtracter to control output phase and switches backward and eliminate burr.But control signal is directly because the difference in logical delay can cause competition; Switch to such as subtract counter output at 101 o'clock from 110, because the difference in logical delay switches to 111 from 110 earlier; Switch to 101 from 111 again; A burr will appear in the output of phase selector like this, and this burr can be identified as clock by follow-up frequency dividing circuit when serious, causes the frequency division mistake.
For the voltage controlled oscillator in the phase-locked loop, under CMOS (Complementary MetalOxide Semiconductor) technology, inductance capacitance type resonant cavity voltage controlled oscillator is because of than ring oscillator better noiseproof feature being arranged and being widely used; A kind of good implementation method is to adopt bonding line to do inductance; Not only can save a lot of chip areas, and have better noiseproof feature, for example; Adopt bonding line to do the inductance of voltage controlled oscillator; The quality factor of bonding line inductance become inductance much higher than chip integration, so noiseproof feature is good, and have saved the occupied large stretch of chip area of sheet internal inductance.But the bonding line inductance is inaccurate, can cause the deviation of voltage controlled oscillator resonance frequency, and traditional method is to come resonance frequency is proofreaied and correct through the capacitor array in the control voltage controlled oscillator.But; The output of voltage controlled oscillator is directly connected to outside the chip through bonding line, just needs ESD (Electro-Static discharge) protection, and traditional way is to adopt the very big diode of area; But have very large parasitic capacitance, this can make the scope of frequency correction seriously reduce.
Summary of the invention
The objective of the invention is provides a kind of high freuqency accuracy, low noise phase-locked loop in order to overcome defective of the prior art.
For achieving the above object, a kind of phase-locked loop according to embodiment of the present invention is provided, comprising:
Phase frequency detector, its input connects the output and the reference clock of digital frequency divider;
Charge pump, its input connects the output of said phase frequency detector;
Loop filter, its input connect said electric charge delivery side of pump;
Voltage controlled oscillator adopts resistance as electrostatic discharge protection, and its control voltage input terminal connects the output of said loop filter;
The bonding line inductance is connected the difference output end of said voltage controlled oscillator;
Buffer, its differential input end is connected to the difference output end of said voltage controlled oscillator, and its difference output end is connected to the difference output end of whole phase-locked loop;
Pre-divider, by Gray code control, its differential signal input connects the difference output end of said buffer, and its signal input end connects first output of control logic; And
Digital frequency divider, its signal input part connects the output of said pre-divider, and its control input end connects second output of control logic.
Preferably, pre-divider comprises:
Two single channel 2 frequency dividers; The differential input end of first single channel, 2 frequency dividers connects the differential input end of pre-divider; The in-phase input end of the differential input end of second single channel, 2 frequency dividers connects the in-phase output end of the I road difference output end of first single channel, 2 frequency dividers, and the inverting input of the differential input end of second single channel, 2 frequency dividers connects the reversed-phase output of the I road difference output end of first single channel, 2 frequency dividers;
Two-way 2 frequency dividers; The in-phase input end of its I road differential input end and reverse input end are connected the in-phase output end and the inverse output terminal of the I road difference output end of second single channel, 2 frequency dividers respectively, and the in-phase input end of its Q road differential input end and inverting input are connected the in-phase output end and the reversed-phase output of the Q road difference output end of second single channel, 2 frequency dividers respectively;
Phase selector comprises eight signal input parts, three input control ends, an output, and its each signal input part signal phase is than last signal input part signal lag 45 degree; When first the input control end be 0, the second the input control end be 0, the three the input control end be 0 o'clock, output is exported the signal of first signal input part; When the first input control end is that 0, the second input control end is that 0, the three input control end is 1 o'clock, the signal of output output secondary signal input; When first the input control end be 0, the second the input control end be 1, the three the input control end be 0 o'clock, output is exported the signal of the 3rd signal input part; When first the input control end be 0, the second the input control end be 1, the three the input control end be 1 o'clock, output is exported the signal of the 4th signal input part; When first the input control end be 1, the second the input control end be 0, the three the input control end be 0 o'clock, output is exported the signal of the 5th signal input part; When first the input control end be 1, the second the input control end be 0, the three the input control end be 1 o'clock, output is exported the signal of the 6th signal input part; When first the input control end be 1, the second the input control end be 1, the three the input control end be 0 o'clock, output is exported the signal of the 7th signal input part; When first the input control end be 1, the second the input control end be 1, the three the input control end be 1 o'clock, output is exported the signal of the 8th signal input part;
The Gray code down counter; Comprise input end of clock and three outputs; Its first, second, third output connects first, second, third control input end of said phase selector respectively, and wherein said three outputs are pressed gray count under the triggering of clock signal;
The Fractional-N frequency device, its input is connected to the output of said phase selector, and its output is connected to the output of whole pre-divider;
NAND gate, its two inputs connect the output and the pattern control word of said phase selector respectively, and output is connected to the input end of clock of said Gray code down counter.
Preferably, said two-way 2 frequency dividers have eight signal output parts, and each output end signal phase place is than last output end signal phase lag 45 degree.
Preferably,
First signal input part of phase selector connects first output of two-way 2 frequency dividers,
The secondary signal input of phase selector connects second output of two-way 2 frequency dividers,
The 3rd signal input part of phase selector connects the 4th output of two-way 2 frequency dividers,
The 4th signal input part of phase selector connects the 3rd output of two-way 2 frequency dividers,
The 5th signal input part of phase selector connects the 8th output of two-way 2 frequency dividers,
The 6th signal input part of phase selector connects the 7th output of two-way 2 frequency dividers,
The 7th signal input part of phase selector connects the 5th output of two-way 2 frequency dividers,
The 8th signal input part of phase selector connects the 6th output of two-way 2 frequency dividers.
Preferably, said single channel 2 frequency dividers comprise:
Two latchs; The in-phase clock input of first latch and the in-phase input end that is connected to whole single channel 2 frequency dividers after the inversion clock input of second latch links to each other, the inversion clock input of first latch and the inverting input that is connected to whole single channel 2 frequency dividers after the in-phase clock input of second latch links to each other; The in-phase output end of first latch and the I road in-phase output end that is connected to whole single channel 2 frequency dividers after the in-phase input end of second latch links to each other; The reversed-phase output of first latch and the I road reversed-phase output that is connected to whole single channel 2 frequency dividers after the inverting input of second latch links to each other; The inverting input of first latch and the Q road in-phase output end that is connected to whole single channel 2 frequency dividers after the in-phase output end of second latch links to each other, the in-phase input end of first latch and the Q road reversed-phase output that is connected to whole single channel 2 frequency dividers after the reversed-phase output of second latch links to each other.
Preferably, said two-way 2 frequency dividers comprise:
Four latchs; The in-phase clock input of first latch and the I road in-phase input end that is connected to whole two-way 2 frequency dividers after the inversion clock input of the 3rd latch links to each other; The in-phase clock input of second latch and the Q road in-phase input end that is connected to whole two-way 2 frequency dividers after the inversion clock input of quad latch links to each other; The in-phase clock input of the 3rd latch and the I road inverting input that is connected to whole two-way 2 frequency dividers after the inversion clock input of first latch links to each other, the in-phase clock input of quad latch and the Q road inverting input that is connected to whole two-way 2 frequency dividers after the inversion clock input of second latch links to each other; The in-phase output end of first latch and first output that is connected to whole two-way 2 frequency dividers after the in-phase input end of second latch links to each other; The reversed-phase output of first latch and the 5th output that is connected to whole two-way 2 frequency dividers after the inverting input of second latch links to each other; The in-phase output end of second latch and second output that is connected to whole two-way 2 frequency dividers after the in-phase input end of the 3rd latch links to each other; The reversed-phase output of second latch and the 6th output that is connected to whole two-way 2 frequency dividers after the inverting input of the 3rd latch links to each other; The in-phase output end of the 3rd latch and the 3rd output that is connected to whole two-way 2 frequency dividers after the in-phase input end of quad latch links to each other; The reversed-phase output of the 3rd latch and the 7th output that is connected to whole two-way 2 frequency dividers after the inverting input of quad latch links to each other; The in-phase output end of quad latch and the 4th output that is connected to whole two-way 2 frequency dividers after the inverting input of first latch links to each other, the reversed-phase output of quad latch and the 8th output that is connected to whole two-way 2 frequency dividers after the in-phase input end of first latch links to each other.
Preferably, said voltage controlled oscillator comprises:
Two PMOS pipes, its source electrode is all received on the supply voltage, and the grid of PMOS pipe is connected respectively to the drain and gate that the 2nd PMOS manages with drain electrode;
The four NMOS pipe; The grid of the one NMOS pipe is connected respectively to the drain and gate that the 2nd NMOS manages with drain electrode; Be connected to the drain electrode of the 3rd NMOS pipe after the source electrode of first and second NMOS pipe links to each other, the 3rd links to each other source grounding with the grid of the 4th NMOS pipe; The grid of the 4th NMOS pipe be connected to the bias current input after drain electrode links to each other
Two pads, first pad is connected to the in-phase output end of said voltage controlled oscillator, and second pad is connected to the reversed-phase output of said voltage controlled oscillator;
Capacitor array connects first pad and second pad, and the control word input of capacitor array is connected to the correction control word input of whole voltage controlled oscillator;
Four resistance; First resistance connects the drain electrode and first pad of PMOS pipe; Second resistance connects the drain electrode and second pad of the 2nd PMOS pipe, and the 3rd resistance connects the drain electrode and first pad of NMOS pipe, and the 4th resistance connects the drain electrode and second pad of the 2nd NMOS pipe;
Two voltage controlled capacitors, first voltage controlled capacitor connects the control voltage input terminal and first pad, and second voltage controlled capacitor connects the control voltage input terminal and second pad.
Technique scheme has following advantage: the burr through the pre-divider of having eliminated traditional common subtract counter control phase selector with the pre-divider of Gray code subtract counter control phase selector causes has high-precision advantage; Do in the voltage controlled oscillator of inductance at the employing bonding line; The small resistor of in branch road, connecting; Not only resistance itself is to not deterioration effect of noise, and kept the low noise advantage that bonding line is done inductance, and resistance has played the effect of ESD simultaneously; The shortcoming that the frequency correction scope of having avoided the big parasitic capacitance of conventional diode ESD to cause reduces has high freuqency accuracy, low noise advantage.
Description of drawings
The circuit block diagram of the phase-locked loop of Fig. 1 embodiment of the invention;
Fig. 2 is the circuit diagram of pre-divider of the phase-locked loop of the embodiment of the invention;
Fig. 3 is the circuit diagram of single channel 2 frequency dividers of the phase-locked loop of the embodiment of the invention;
Fig. 4 is the circuit diagram of two-way 2 frequency dividers of the phase-locked loop of the embodiment of the invention;
Fig. 5 is the circuit diagram of voltage controlled oscillator of the phase-locked loop of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.Following examples are used to explain the present invention, but are not used for limiting scope of the present invention.
The pre-divider with Gray code control of the embodiment of the invention and the phase-locked loop of the voltage controlled oscillator that resistance is ESD are as shown in Figure 1; Two inputs of phase frequency detector connect the output of reference clock and digital frequency divider respectively; Two inputs of charge pump connect two outputs of said phase frequency detector respectively, and the input of loop filter connects said electric charge delivery side of pump.The control voltage of voltage-controlled oscillator input VC that resistance is ESD connects the output of said loop filter; The correction control input end CSW that resistance is made the voltage controlled oscillator of ESD connects the correction control word, and the bonding line inductance is connected difference output end OP and the ON that resistance is made the voltage controlled oscillator of ESD.The differential input end of buffer is connected to the difference output end that said resistance is done the controlled oscillator of ESD, and the difference output end of buffer is connected to the difference output end of whole phase-locked loop.The differential signal input IP of the pre-divider of Gray code control and IN are connected the difference output end of buffer, first output of the signal input end MB connection control logic of the pre-divider of Gray code control respectively.The signal input part of digital frequency divider connects the output FO of the pre-divider of said Gray code control, and the control input end of digital frequency divider connects second output of control logic, and the input of control logic connects the frequency dividing ratio control word.
Having the pre-divider of Gray code control and the principle of PLL of the voltage controlled oscillator that resistance is ESD is; Eliminate the burr that the pre-divider of traditional common subtract counter control phase selector causes with the pre-divider of Gray code subtract counter control phase selector, had the frequency division advantage of high precision; Do in the voltage controlled oscillator of inductance at the employing bonding line; The small resistor of in branch road, connecting; Not only resistance itself is to not deterioration effect of noise, and kept the low noise advantage that bonding line is done inductance, and resistance has played the effect of ESD simultaneously; The shortcoming that the frequency correction scope of having avoided the big parasitic capacitance of diode ESD to cause reduces has high freuqency accuracy, low noise advantage.
The circuit diagram of the pre-divider of the Gray code control of the embodiment of the invention is as shown in Figure 2; The differential input end P of single channel 2 frequency divider DIV1 and N are connected the differential signal input IP and the IN of the pre-divider of whole Gray code control respectively; The in-phase input end P of the differential input end of 2 frequency divider DIV2 connects the in-phase output end I+ of the I road difference output end of 2 frequency divider DIV1, and the inverting input N of the differential input end of 2 frequency divider DIV2 connects the reversed-phase output I-of the I road difference output end of 2 frequency divider DIV1.The in-phase input end IP of the I road differential input end of two-way 2 frequency divider DIV3 connects the in-phase output end I+ of the I road difference output end of single channel 2 frequency divider DIV2; The inverting input IN of the I road differential input end of two-way 2 frequency divider DIV3 connects the reversed-phase output I-of the I road difference output end of single channel 2 frequency divider DIV2; The in-phase input end QP of the Q road differential input end of two-way 2 frequency divider DIV3 connects the in-phase output end Q+ of the Q road difference output end of single channel 2 frequency divider DIV2, and the inverting input QN of the Q road differential input end of two-way 2 frequency divider DIV3 connects the reversed-phase output Q-of the Q road difference output end of single channel 2 frequency divider DIV2.The second output P1 signal phase of two-way 2 frequency divider DIV3 is than the first output P0 phase lag signal, 45 degree; The 3rd output P2 signal phase of two-way 2 frequency dividers is than the second output P1 phase lag signal, 45 degree; The 4th output P3 signal phase of two-way 2 frequency dividers is than the 3rd output P2 phase lag signal 45 degree; The 5th output P4 signal phase of two-way 2 frequency dividers is than the 4th output P3 phase lag signal 45 degree; The 6th output P5 signal phase of two-way 2 frequency dividers is than the 5th output P4 phase lag signal 45 degree; The 7th output P6 signal phase of two-way 2 frequency dividers is than the 6th output P5 phase lag signal 45 degree, and the 8th output P7 signal phase of two-way 2 frequency dividers is than the 7th output P6 phase lag signal 45 degree.Phase selector comprises eight signal input part P0～P7 of phase place, three input control end S2～S0, an output SO.Require secondary signal input P1 signal phase than the first signal input part P0 signal lag, 45 degree; The 3rd signal input part P2 signal phase is than secondary signal input P1 signal lag 45 degree; The 4th signal input part P3 signal phase is than the 3rd signal input part P2 signal lag 45 degree; The 5th signal input part P4 signal phase is than the 4th signal input part P3 signal lag 45 degree; The 6th signal input part P5 signal phase is than the 5th signal input part P4 signal lag 45 degree, and the 7th signal input part P6 signal phase is than the 6th signal input part P5 signal lag 45 degree, and the 8th signal input part P7 signal phase is than the 7th signal input part P6 signal lag 45 degree.When the first input control end S2 is that 0, the second input control end S1 is that 0, the three input control end S0 is 0 o'clock, output is exported the signal of the first signal input part P0; When the first input control end S2 is that 0, the second input control end S1 is that 0, the three input control end S0 is 1 o'clock, the signal of output output secondary signal input P1; When the first input control end S2 is that 0, the second input control end S1 is that 1, the three input control end S0 is 0 o'clock, output is exported the signal of the 3rd signal input part P2; When the first input control end S2 is that 0, the second input control end S1 is that 1, the three input control end S0 is 1 o'clock, output is exported the signal of the 4th signal input part P3; When the first input control end S2 is that 1, the second input control end S1 is that 0, the three input control end S0 is 0 o'clock, output is exported the signal of the 5th signal input part P4; When the first input control end S2 is that 1, the second input control end S1 is that 0, the three input control end S0 is 1 o'clock, output is exported the signal of the 6th signal input part P5; When the first input control end S2 is that 1, the second input control end S1 is that 1, the three input control end S0 is 0 o'clock, output is exported the signal of the 7th signal input part P6; When the first input control end S2 is that 1, the second input control end S1 is that 1, the three input control end S0 is 1 o'clock, output is exported the signal of the 8th signal input part P7.The P0 end of phase selector PS connects the P0 end of two-way 2 frequency divider DIV3; The P1 end of PS connects the P1 end of DIV3, and the P2 end of PS connects the P3 end of DIV3, and the P3 end of PS connects the P2 end of DIV3; The P4 end of PS connects the P7 end of DIV3; The P5 end of PS connects the P6 end of DIV3, and the P6 end of PS connects the P4 end of DIV3, and the P7 end of PS connects the P5 end of DIV3.Gray code down counter GC comprises an input end of clock CLK and three output C2～C0.The first output C2 connects the first control input end S2 of said phase selector, and the second output C1 connects the second control input end S1 of said phase selector, and the 3rd output C0 connects the 3rd control input end S0 of said phase selector.Three outputs are pressed gray count under the triggering of input clock signal, the order of variation is: C2 is 1, and C1 is 0, and C0 is 0; C2 is 1, and C1 is 0, and C0 is 1; C2 is 1, and C1 is 1, and C0 is 1; C2 is 1, and C1 is 1, and C0 is 0; C2 is 0, and C1 is 1, and C0 is 0; C2 is 0, and C1 is 1, and C0 is 1; C2 is 0, and C1 is 0, and C0 is 1; C2 is 0, and C1 is 0, and C0 is 0.The C2 end of GC connects the first control input end S2 of phase selector, and the C1 end connects the second control input end S1 of phase selector, and the C0 end connects the 3rd control input end S0 of phase selector.The input of Fractional-N frequency device DIV4 is connected to the output SO of said phase selector, and the output of Fractional-N frequency device DIV4 is connected to the output FO of the pre-divider of whole Gray code control.Two inputs of NAND gate NAND connect the output FO and the pattern control word MB of said phase selector respectively, and the output of NAND gate is connected to the input end of clock CLK of said Gray code down counter.
The operation principle of the pre-divider of Gray code control is, when pattern control word MB is 0, and the invalidating signal of the input end of clock CLK of Gray code down counter GC, GC does not count, and phase selector is output as 8 frequency divisions of input signal fin; When pattern control word MB was 1, the signal of the input end of clock CLK of Gray code down counter GC was effective, and GC presses Gray code subtraction counting, and phase selector is output as 7 frequency divisions of input signal fin.Because Gray code only changes one at every turn, so there is not the problem of competition between output C2, C1 and the C0 of GC, this has just eliminated burr, has improved the precision of frequency division, and then has improved the precision of phase-lock-ring output frequency.
The circuit diagram of single channel 2 frequency dividers of the embodiment of the invention is as shown in Figure 3; The in-phase clock input CLKP of latch Latch1 and the in-phase input end P that is connected to whole single channel 2 frequency dividers after the inversion clock input CLKN of latch Latch2 links to each other, the inversion clock input CLKN of latch Latch1 and the inverting input N that is connected to whole single channel 2 frequency dividers after the in-phase clock input CLKP of latch Latch2 links to each other.The in-phase output end QP of latch Latch1 and the I road in-phase output end I+ that is connected to whole single channel 2 frequency dividers after the in-phase input end DP of latch Latch2 links to each other; The reversed-phase output QN of latch Latch1 and the I road reversed-phase output I-that is connected to whole single channel 2 frequency dividers after the inverting input DN of latch Latch2 links to each other; The inverting input DN of latch Latch1 and the Q road in-phase output end Q+ that is connected to whole single channel 2 frequency dividers after the in-phase output end QP of latch Latch2 links to each other, the in-phase input end DP of latch Latch1 and the Q road reversed-phase output Q-that is connected to whole single channel 2 frequency dividers after the reversed-phase output QN of latch Latch2 links to each other.
The circuit diagram of two-way 2 frequency dividers of the embodiment of the invention is as shown in Figure 4; The in-phase clock input CLKP of latch Latch1 and the I road in-phase input end IP that is connected to whole two-way 2 frequency dividers after the inversion clock input CLKN of latch Latch3 links to each other; The in-phase clock input CLKP of latch Latch2 and the Q road in-phase input end QP that is connected to whole two-way 2 frequency dividers after the inversion clock input CLKN of latch Latch4 links to each other; The in-phase clock input CLKP of latch Latch3 and the I road inverting input IN that is connected to whole two-way 2 frequency dividers after the inversion clock input CLKN of latch Latch1 links to each other, the in-phase clock input CLKP of latch Latch4 and the Q road inverting input QN that is connected to whole two-way 2 frequency dividers after the inversion clock input CLKN of latch Latch2 links to each other.The in-phase output end QP of latch Latch1 and the first output P0 that is connected to whole two-way 2 frequency dividers after the in-phase input end DP of latch Latch2 links to each other; The reversed-phase output QN of latch Latch1 and the 5th output P4 that is connected to whole two-way 2 frequency dividers after the inverting input DN of latch Latch2 links to each other; The in-phase output end QP of latch Latch2 and the second output P1 that is connected to whole two-way 2 frequency dividers after the in-phase input end DP of latch Latch3 links to each other; The reversed-phase output QN of latch Latch2 and the 6th output P5 that is connected to whole two-way 2 frequency dividers after the inverting input DN of latch Latch3 links to each other; The in-phase output end QP of latch Latch3 and the 3rd output P2 that is connected to whole two-way 2 frequency dividers after the in-phase input end DP of latch Latch4 links to each other; The reversed-phase output QN of latch Latch3 and the 7th output P6 that is connected to whole two-way 2 frequency dividers after the inverting input DN of latch Latch4 links to each other; The in-phase output end QP of latch Latch4 and the 4th output P3 that is connected to whole two-way 2 frequency dividers after the inverting input DN of latch Latch1 links to each other, the reversed-phase output QN of latch Latch4 and the 8th output P7 that is connected to whole two-way 2 frequency dividers after the in-phase input end DP of latch Latch1 links to each other.
The resistance of the embodiment of the invention does that the circuit diagram of voltage controlled oscillator of ESD is as shown in Figure 5, and the source electrode of PMOS pipe Mp1 and Mp2 is all received on the supply voltage VDD, and the grid of Mp1 is connected to the drain electrode of Mp2, and the grid of Mp2 is connected to the drain electrode of Mp1.The grid of NMOS pipe Mn1 is connected to the drain electrode of NMOS pipe Mn2; The grid of NMOS pipe Mn2 is connected to the drain electrode of NMOS pipe Mn1; The source electrode of Mn1 and the drain electrode that is connected to NMOS pipe Mn3 after the source electrode of Mn2 links to each other; The grid of the grid of Mn3 and NMOS pipe Mn4 links to each other, and the grid of Mn4 is connected to bias current input IB, the source electrode of Mn3 and the source grounding of Mn4 after linking to each other with draining.Pad PAD1 is connected to the in-phase output end OUTP that resistance is made the voltage controlled oscillator of ESD, and pad PAD2 is connected to the reversed-phase output OUTN that resistance is made the voltage controlled oscillator of ESD.Capacitor array Ca connects PAD1 and PAD2, and the control word input CB of capacitor array is connected to the correction control word input CSW that whole resistance is made the voltage controlled oscillator of ESD.Resistance R 1 connects drain electrode and the PAD1 of Mp1, and resistance R 2 connects drain electrode and the PAD2 of Mp2, and resistance R 3 connects drain electrode and the PAD1 of Mn1, and resistance R 4 connects drain electrode and the PAD2 of Mn2.Voltage controlled capacitor D1 connects control voltage input terminal VC and PAD1, and voltage controlled capacitor D2 connects the control voltage input terminal VC and the second pad PAD2.
The resistance of the embodiment of the invention is made the voltage controlled oscillator of ESD; The resistance value of resistance R 1, R2, R3 and R4 is very little; Almost not influence of noiseproof feature to oscillator; But play the effect of very strong esd protection, this has just been avoided the big parasitic capacitance that conventional diode ESD had, and makes that the correcting range of resonance frequency of voltage controlled oscillator is unaffected.
Can find out by above embodiment; The embodiment of the invention has been eliminated the burr that the pre-divider of traditional common subtract counter control phase selector causes through the pre-divider that adopts Gray code subtract counter control phase selector, has high-precision advantage; Do in the voltage controlled oscillator of inductance at the employing bonding line; The small resistor of in branch road, connecting; Not only resistance itself is to not deterioration effect of noise, and kept the low noise advantage that bonding line is done inductance, and resistance has played the effect of ESD simultaneously; The shortcoming that the frequency correction scope of having avoided the big parasitic capacitance of conventional diode ESD to cause reduces has high freuqency accuracy, low noise advantage.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from know-why of the present invention; Can also make some improvement and modification, these improve and modification also should be regarded as protection scope of the present invention.
Claims (7)
1. a phase-locked loop is characterized in that, said phase-locked loop comprises:
Phase frequency detector, its input connects the output and the reference clock of digital frequency divider;
Charge pump, its input connects the output of said phase frequency detector;
Loop filter, its input connect said electric charge delivery side of pump;
Voltage controlled oscillator adopts resistance as electrostatic discharge protection, and its control voltage input terminal connects the output of said loop filter;
The bonding line inductance is connected the difference output end of said voltage controlled oscillator;
Buffer, its differential input end is connected to the difference output end of said voltage controlled oscillator, and its difference output end is connected to the difference output end of whole phase-locked loop;
Pre-divider, by Gray code control, its differential signal input connects the difference output end of said buffer, and its signal input end connects first output of control logic; And
Digital frequency divider, its signal input part connects the output of said pre-divider, and its control input end connects second output of control logic;
Wherein, said voltage controlled oscillator comprises:
Two PMOS pipes, its source electrode is all received on the supply voltage, and the grid of PMOS pipe is connected respectively to the drain and gate that the 2nd PMOS manages with drain electrode;
The four NMOS pipe; The grid of the one NMOS pipe is connected respectively to the drain and gate that the 2nd NMOS manages with drain electrode; After linking to each other, the source electrode of first and second NMOS pipe is connected to the drain electrode of the 3rd NMOS pipe; The 3rd links to each other with the grid of the 4th NMOS pipe, and source grounding, the grid of the 4th NMOS pipe are connected to the bias current input after linking to each other with draining;
Two pads, first pad is connected to the in-phase output end of said voltage controlled oscillator, and second pad is connected to the reversed-phase output of said voltage controlled oscillator;
Four resistance; First resistance connects the drain electrode and first pad of PMOS pipe; Second resistance connects the drain electrode and second pad of the 2nd PMOS pipe, and the 3rd resistance connects the drain electrode and first pad of NMOS pipe, and the 4th resistance connects the drain electrode and second pad of the 2nd NMOS pipe.
2. phase-locked loop as claimed in claim 1 is characterized in that pre-divider comprises:
Two single channel 2 frequency dividers; The differential input end of first single channel, 2 frequency dividers connects the differential input end of pre-divider; The in-phase input end of the differential input end of second single channel, 2 frequency dividers connects the in-phase output end of the I road difference output end of first single channel, 2 frequency dividers, and the inverting input of the differential input end of second single channel, 2 frequency dividers connects the reversed-phase output of the I road difference output end of first single channel, 2 frequency dividers;
Two-way 2 frequency dividers; The in-phase input end of its I road differential input end and reverse input end are connected the in-phase output end and the inverse output terminal of the I road difference output end of second single channel, 2 frequency dividers respectively, and the in-phase input end of its Q road differential input end and inverting input are connected the in-phase output end and the reversed-phase output of the Q road difference output end of second single channel, 2 frequency dividers respectively;
Phase selector comprises eight signal input parts, three input control ends, an output, and its each signal input part signal phase is than last signal input part signal lag 45 degree; When first the input control end be 0, the second the input control end be 0, the three the input control end be 0 o'clock, output is exported the signal of first signal input part; When the first input control end is that 0, the second input control end is that 0, the three input control end is 1 o'clock, the signal of output output secondary signal input; When first the input control end be 0, the second the input control end be 1, the three the input control end be 0 o'clock, output is exported the signal of the 3rd signal input part; When first the input control end be 0, the second the input control end be 1, the three the input control end be 1 o'clock, output is exported the signal of the 4th signal input part; When first the input control end be 1, the second the input control end be 0, the three the input control end be 0 o'clock, output is exported the signal of the 5th signal input part; When first the input control end be 1, the second the input control end be 0, the three the input control end be 1 o'clock, output is exported the signal of the 6th signal input part; When first the input control end be 1, the second the input control end be 1, the three the input control end be 0 o'clock, output is exported the signal of the 7th signal input part; When first the input control end be 1, the second the input control end be 1, the three the input control end be 1 o'clock, output is exported the signal of the 8th signal input part;
The Gray code down counter; Comprise input end of clock and three outputs; Its first, second, third output connects first, second, third control input end of said phase selector respectively, and wherein said three outputs are pressed the Gray code countdown under the triggering of clock signal;
The Fractional-N frequency device, its input is connected to the output of said phase selector, and its output is connected to the output of whole pre-divider;
NAND gate, its two inputs connect the output and the pattern control word of said phase selector respectively, and output is connected to the input end of clock of said Gray code down counter.
3. phase-locked loop as claimed in claim 2 is characterized in that, two-way 2 frequency dividers have eight signal output parts, and each output end signal phase place is than last output end signal phase lag 45 degree.
4. phase-locked loop as claimed in claim 2 is characterized in that,
First signal input part of phase selector connects first output of two-way 2 frequency dividers,
The secondary signal input of phase selector connects second output of two-way 2 frequency dividers,
The 3rd signal input part of phase selector connects the 4th output of two-way 2 frequency dividers,
The 4th signal input part of phase selector connects the 3rd output of two-way 2 frequency dividers,
The 5th signal input part of phase selector connects the 8th output of two-way 2 frequency dividers,
The 6th signal input part of phase selector connects the 7th output of two-way 2 frequency dividers,
The 7th signal input part of phase selector connects the 5th output of two-way 2 frequency dividers,
The 8th signal input part of phase selector connects the 6th output of two-way 2 frequency dividers.
5. like each described phase-locked loop of claim 2-4, it is characterized in that said single channel 2 frequency dividers comprise:
Two latchs; The in-phase clock input of first latch and the in-phase input end that is connected to whole single channel 2 frequency dividers after the inversion clock input of second latch links to each other, the inversion clock input of first latch and the inverting input that is connected to whole single channel 2 frequency dividers after the in-phase clock input of second latch links to each other; The in-phase output end of first latch and the I road in-phase output end that is connected to whole single channel 2 frequency dividers after the in-phase input end of second latch links to each other; The reversed-phase output of first latch and the I road reversed-phase output that is connected to whole single channel 2 frequency dividers after the inverting input of second latch links to each other; The inverting input of first latch and the Q road in-phase output end that is connected to whole single channel 2 frequency dividers after the in-phase output end of second latch links to each other, the in-phase input end of first latch and the Q road reversed-phase output that is connected to whole single channel 2 frequency dividers after the reversed-phase output of second latch links to each other.
6. like each described phase-locked loop of claim 2-4, it is characterized in that said two-way 2 frequency dividers comprise:
Four latchs; The in-phase clock input of first latch and the I road in-phase input end that is connected to whole two-way 2 frequency dividers after the inversion clock input of the 3rd latch links to each other; The in-phase clock input of second latch and the Q road in-phase input end that is connected to whole two-way 2 frequency dividers after the inversion clock input of quad latch links to each other; The in-phase clock input of the 3rd latch and the I road inverting input that is connected to whole two-way 2 frequency dividers after the inversion clock input of first latch links to each other, the in-phase clock input of quad latch and the Q road inverting input that is connected to whole two-way 2 frequency dividers after the inversion clock input of second latch links to each other; The in-phase output end of first latch and first output that is connected to whole two-way 2 frequency dividers after the in-phase input end of second latch links to each other; The reversed-phase output of first latch and the 5th output that is connected to whole two-way 2 frequency dividers after the inverting input of second latch links to each other; The in-phase output end of second latch and second output that is connected to whole two-way 2 frequency dividers after the in-phase input end of the 3rd latch links to each other; The reversed-phase output of second latch and the 6th output that is connected to whole two-way 2 frequency dividers after the inverting input of the 3rd latch links to each other; The in-phase output end of the 3rd latch and the 3rd output that is connected to whole two-way 2 frequency dividers after the in-phase input end of quad latch links to each other; The reversed-phase output of the 3rd latch and the 7th output that is connected to whole two-way 2 frequency dividers after the inverting input of quad latch links to each other; The in-phase output end of quad latch and the 4th output that is connected to whole two-way 2 frequency dividers after the inverting input of first latch links to each other, the reversed-phase output of quad latch and the 8th output that is connected to whole two-way 2 frequency dividers after the in-phase input end of first latch links to each other.
7. like each described phase-locked loop of claim 2-4, it is characterized in that said voltage controlled oscillator also comprises:
Capacitor array connects first pad and second pad, and the control word input of capacitor array is connected to the correction control word input of whole voltage controlled oscillator;
Two voltage controlled capacitors, first voltage controlled capacitor connects the control voltage input terminal and first pad, and second voltage controlled capacitor connects the control voltage input terminal and second pad.
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| US8576523B2 (en) * | 2011-03-14 | 2013-11-05 | Qualcomm Incorporated | Charge pump electrostatic discharge protection |
| CN102136840B (en) * | 2011-04-22 | 2016-03-16 | 上海华虹宏力半导体制造有限公司 | Self-biased phase-locked loop |
| CN102355240B (en) * | 2011-08-02 | 2014-05-07 | 深圳市国微电子有限公司 | Clock generator used for integrated circuit |
| US8786328B2 (en) * | 2012-09-12 | 2014-07-22 | Texas Instruments Incorporated | RF logic divider |
| CN104079315B (en) * | 2014-06-24 | 2018-09-04 | 中国科学院半导体研究所 | Multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators |
| CN104135276B (en) * | 2014-06-26 | 2017-10-24 | 中国科学院半导体研究所 | A kind of Wireless RF transmitter |
| CN109387300A (en) * | 2017-08-07 | 2019-02-26 | 吕海党 | A kind of safety detector |
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| TWI618358B (en) * | 2016-01-15 | 2018-03-11 | 絡達科技股份有限公司 | Frequency divider and controlling method thereof |
| US10211837B2 (en) | 2016-01-15 | 2019-02-19 | Airoha Technology Corp. | Frequency divider and control method thereof |
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