CN102355240B - Clock generator used for integrated circuit - Google Patents
Clock generator used for integrated circuit Download PDFInfo
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- CN102355240B CN102355240B CN201110219712.9A CN201110219712A CN102355240B CN 102355240 B CN102355240 B CN 102355240B CN 201110219712 A CN201110219712 A CN 201110219712A CN 102355240 B CN102355240 B CN 102355240B
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Abstract
The invention discloses a clock generator used for an integrated circuit. The clock generator comprises that: a phase frequency detector; an integrator; a voltage controlled oscillator; a multi-mode frequency divider used for carrying out frequency division processing on four clock signals outputted by the voltage controlled oscillator and outputting a first feedback signal; a phase correlator used for calculating a phase difference between the inputted synchronization data and the four clock signals; a phase synthesizer used for carrying out line aliasing on the four clock signals outputted by the voltage controlled oscillator according to a control signal outputted by the phase correlator, and outputting a second feedback signal; a decision selector used for switching the first feedback signal or the second feedback signal selectively, outputting the signal to the phase frequency detector, allowing the four clock signals outputted by the voltage controlled oscillator and a reference clock signal to be in same frequency, and allowing a phase of frequency of the reference clock signal and a phase of the synchronization data to maintain synchronous. According to the invention, automatic loop switching is realized, a four-phase clock is directly provided, a number of sampling is raised, and the clock generator has a simplified circuit volume.
Description
Technical field
The present invention relates to a kind of integrated circuit, especially relate to a kind of clock generator that four phase clocks are provided for integrated circuit.
Background technology
In integrated circuit, along with work clock is more and more faster, the clock frequency of YiGHzWei unit cannot directly be provided by crystal oscillator, but needs a clock generator to provide corresponding system clock and sampling clock for CPU or SERDES system.
Independent phase-locked loop (the PLL of the general use of current clock generator, Phase-Locked Loop) produce system clock, owing to using large-area capacitor and using resistor to be used for building its loop filter, therefore many times cannot Embedded, need outward element, increase cost, also strengthened application difficulty simultaneously; In addition, current programme is generally used odd level oscillator, and corresponding multipath clock phase place is also asymmetric, when needs provide multi-phase clock can only by by output clock frequency division to realize, the maximum operating frequency of the system of restriction greatly; And system clock phase place is uncontrollable, be particularly applied to SERDES field, clock phase cannot be synchronized to the correct sampling location of data; The duty ratio of output clock is not satisfactory, the work schedule of remote-effects digital circuit and sampling precision.
Summary of the invention
The present invention proposes a kind of clock generator for integrated circuit, uses many loops to realize synchronizeing of the frequency of system clock and phase place and target clock or data, and automatically between a plurality of loops, switches according to operating state.
The present invention adopts following technical scheme to realize: a kind of clock generator for integrated circuit, and it comprises:
Phase frequency detector, for detection of the reference clock signal phase place of input and the phase difference between feedback signal, produces output signals UP and output signal DN;
Be connected to the integrator of phase frequency detector output, for output signals UP and output signal DN are carried out to integral operation;
Be connected to the filter at zero point of phase frequency detector reversed-phase output, for loop being carried out to filtering after integrator stable output;
Control end connects the voltage controlled oscillator of integrator and filter output, for exporting the 4 tunnels clock signal of phase difference 90 degree successively;
The multi-modulus frequency divider that connects voltage controlled oscillator output, for 4 tunnel clock signals of voltage controlled oscillator output are carried out to frequency division processing, output the first feedback signal;
The phase correlator that connects voltage controlled oscillator output, for calculating the phase difference between the synchrodata of input and 4 tunnel clock signals of voltage controlled oscillator output, converts the control signal of control phase synthesizer to;
The phase synthesizer that connects respectively voltage controlled oscillator output, phase correlator output, for the 4 tunnel clock signal line aliasings to voltage controlled oscillator output according to the control signal of phase correlator output, output the second feedback signal;
Be connected to the judgement selector between multi-modulus frequency divider output, phase synthesizer output and the feedback input end of phase frequency detector, for optionally the first feedback signal being switched and is exported to phase frequency detector, make 4 tunnel clock signals and the reference clock signal same frequency of voltage controlled oscillator output, and after the clock signal and reference clock signal same frequency of voltage controlled oscillator output, control optionally the second feedback signal is switched and exported to phase frequency detector, the phase place of reference clock signal and the phase preserving of synchrodata are synchronizeed.
Preferably, integrator comprises:
The interconnective PMOS of grid and the 2nd PMOS, and the source electrode of the 2nd PMOS connects the drain electrode of the 3rd PMOS that is subject to the control of phase frequency detector output signals UP;
The interconnective NMOS of grid and the 2nd NMOS, and the source electrode of the 2nd NMOS connects the drain electrode of the 3rd NMOS that is subject to phase frequency detector output signal DN control;
The drain electrode of the drain electrode of the 2nd PMOS, the 2nd NMOS connects the grid of integration metal-oxide-semiconductor and the grid of the 4th PMOS respectively, by the drain electrode output of the 4th PMOS, controls electric current to voltage controlled oscillator.
Preferably, described clock generator also comprises:
Two inverters that connect phase frequency detector outputs, for by phase frequency detector output signals UP and output signal DN anti-phase be respectively output signals UP B and output signal DNB;
Be connected to the filter at zero point between two inverter output and voltage controlled oscillator control end.
Preferably, zero point, filter comprised:
Interconnective the 5th PMOS of grid and the 6th PMOS, and the source electrode of the 6th PMOS connects the drain electrode of the 7th PMOS that is subject to inverter output signals UP B control;
Interconnective the 5th NMOS of grid and the 6th NMOS, and the source electrode of the 6th NMOS connects the drain electrode of the 7th NMOS that is subject to inverter output signal DNB control;
The drain electrode of the drain electrode of the 6th PMOS, the 6th NMOS connect respectively for the input resistance with voltage controlled oscillator together form the 8th nmos source of output equivalent resistance, as the 9th NMOS grid of filtering mos capacitance.
Preferably, by regulate integrator internal gain X and zero point filter the ratio of internal gain Y reduce the size of integration metal-oxide-semiconductor;
Wherein, the internal gain X of integrator is: X=a*Gmp4, and a is dimension scale, and a=the one PMOS/two PMOS=the one NMOS/two NMOS, Gmp4 is the transadmittance gain of the 4th PMOS;
Zero point, the internal gain Y of filter was: Y=b, b is dimension scale, b=the 5th PMOS/six PMOS=five NMOS/six NMOS.
Preferably, X/Y is below 0.1 or 0.1.
Preferably, voltage controlled oscillator comprises:
The delay cell of level Four cascade, forms four groups of differential clock signals;
Output in each delay cell is connected in series respectively an amplifier, and four groups of differential clock signals amplify output by 4 amplifier buffers respectively.
Preferably, judgement selector comprises:
For the reference source counter that the reference count signal of input is counted;
For the feedback counter that the first feedback signal of multi-modulus frequency divider output is counted;
Be connected to the trigger comparator of reference source counter output, for count results and the threshold value comparison obtaining with reference to source counter, until the count results of reference source counter reaches certain threshold value, export a triggering signal;
Connect respectively the output of reference source counter, the mould calculator of the output of the output of feedback counter, trigger comparator, for the mould between computing reference source counter and feedback counter count value;
Be connected to the threshold judgement device of mould calculator output, for according to the mould of mould calculator output, select the second feedback signal of the first feedback signal of multi-modulus frequency divider output or phase synthesizer output to switch to phase frequency detector.
Preferably, phase correlator comprises:
Phase calculation circuit, for calculating the phase place residual of the synchrodata of input;
Be connected to the decoder of phase calculation circuit output end, phase place residual for the output of phase calculation circuit is translated into the binary control signal DECOUT<0:7> of 8, and the phase place residual of control signal DECOUT<0:7> is mapped on four interval phase place circle diagrams of a 0-360 degree;
The DAC that connects decoder output, for simulating control level IP and IN according to two of binary control signal DECOUT<0:7> generation control phase synthesizer.
Preferably, phase calculation circuit comprises:
4 registers, for the synchrodata of input is sampled respectively, sampling clock is respectively 4 clock signals of voltage controlled oscillator output, and 4 registers are exported respectively sampled data Q0, sampled data Q90, sampled data Q180 and sampled data Q270;
4 exclusive-OR operators, make XNOR operation for then respectively tetra-groups of sampled data Q0 and sampled data Q90, sampled data Q90 and sampled data Q180, sampled data Q180 and sampled data Q270, sampled data Q270 and sampled data Q0 being exported to sampled datas;
Accumulator, is connected to the output of 4 exclusive-OR operators, for to the Output rusults of 4 exclusive-OR operators zero adding, a criterion subtracting does cumulative operation, accumulation result is current phase place residual.
Compared with prior art, the present invention has following beneficial effect:
1, the present invention uses many loops, can realize the frequency of system clock and phase place simultaneously with the synchronizeing of target clock or data, and automatically between a plurality of loops, switch according to the operating state of system.
2, the clock generator that the present invention proposes directly provides four phase clocks, can improve sampling number, sample rate in SERDES application is improved more than 30%, and can be simultaneously provide system clock and sampling clock for CPU or SERDES system.
3, the present invention does not use resistance, and replaces with cheap MOS device, can be applied in the digit chip of pure CMOS, particularly there is no the capacitor of enormous size, and all circuit are all completely at core Embedded, and volume is simplified.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of many loops high-frequency clock generator;
Fig. 2 is the circuit diagram of integrator;
Fig. 3 is the circuit diagram of filter at zero point;
Fig. 4 is the circuit diagram of voltage controlled oscillator;
Fig. 5 is the circuit diagram of delay cell in Fig. 4;
Fig. 6 is the schematic diagram of judgement selector;
Fig. 7 is the schematic diagram of phase correlator;
Fig. 8 is the schematic diagram of phase calculation circuit in Fig. 7;
Fig. 9 is the schematic diagram of DAC in Fig. 7;
Figure 10 is the circuit diagram of phase synthesizer.
Embodiment
As shown in Figure 1, the clock generator that the present invention proposes comprises: phase frequency detector (phase and frequency detector, PFD) 1, it has the reference input of input reference clock signal (reference clock) and the feedback input end of feedback signal (feedback clock), and 2 outputs that are respectively output signals UP and output signal DN; Two outputs of phase frequency detector 1 directly connect integrator (integrator) 2, and two outputs of phase frequency detector 1 connect filter at zero point (Filter) 3 by 2 inverters 9 respectively; Connect integrator 2 outputs and zero point filter 3 outputs voltage controlled oscillator (Voltage Controlled Oscillator, VCO) 4; Be connected in multi-modulus frequency divider (multimode divider) 5 and the phase synthesizer (phase combiner) 6 of voltage controlled oscillator 4 outputs in parallel, and multi-modulus frequency divider 5 connects respectively the feedback input end of phase frequency detector 1 with phase synthesizer 6 by the judgement selector (decision/choose) 7 being connected; Reception is from the phase correlator (phase correlator) 8 of the synchrodata DATA of outside input, and it connects phase synthesizer 6 and voltage controlled oscillator 4.
Phase frequency detector (PFD) 1 is a phase comparison device, is used for detecting reference clock signal (reference clock) phase place of input and the phase difference between feedback signal (feedback).When the rising edge of the reference clock signal of reference input input is ahead of the rising edge of feedback signal of feedback input end input, the output signals UP of PFD is set to 1, and output signal DN is 0; When the rising edge of feed back input end signal arrives, it is narrow pulse that UP becomes ' 0 ', DN; Otherwise when the rising edge of feed back input end signal is ahead of the rising edge of reference input end signal, the output signal DN of PFD is set to ' 1 ', and output signals UP keeps ' 0 '; When the rising edge of reference input end signal arrives, it is a very narrow pulse that DN becomes ' 0 ', UP.The time span that output signals UP or DN are set to high level equals the phase difference of reference input end signal and feed back input end signal.When loop-locking, the output signal of phase frequency detector 1 all remains on low level.
The frequency feedback loop that wherein phase frequency detector 1, integrator 2, zero point, filter 3, voltage controlled oscillator 4, multi-modulus frequency divider 5 formed, for being stabilized to the output frequency of voltage controlled oscillator 4 target frequency with the reference clock signal of inputting (reference clock) same frequency.
And phase frequency detector 1, integrator 2, zero point filter 3, voltage controlled oscillator 4, phase synthesizer 6 and the phase feedback loop that forms of phase correlator 8, for the synchrodata DATA to input by the Phase synchronization of the reference clock signal (reference clock) of the reference input input of phase frequency detector 1.Wherein, the synchrodata DATA of input can be the data that are sampled, and can be also the synchronised clock that other system passes over simultaneously.
The mode of operation of frequency feedback loop, phase feedback loop is to judge switching by judgement selector 7.First feedback signal (Feedback1 clock) of multi-modulus frequency divider 5 output outputs is that the clock signal of voltage controlled oscillator 4 outputs is carried out to frequency division generation; Second feedback signal (Feedback2 clock) of phase synthesizer 6 output outputs is that the clock signal of voltage controlled oscillator 4 outputs is carried out to the synthetic generation of phase place.When judgement selector 7 is selected to export the first feedback signal switching of multi-modulus frequency divider 5 outputs to phase frequency detector 1 between multi-modulus frequency divider 5 and phase synthesizer 6, now adjudicate the first feedback signal that the feedback signal (feedback clock) of selector 7 outputs is multi-modulus frequency divider 5 outputs; Same, when judgement selector 7 is selected to export the second feedback signal switching of phase synthesizer 6 outputs to phase frequency detector 1, the feedback signal of now adjudicating selector 7 outputs is the second feedback signal of phase synthesizer 6 outputs.
First the clock generator that the present invention proposes will be operated in Frequency Synchronization pattern (that is: frequency feedback loop work).When clock generator of the present invention starts, the first feedback signal of multi-modulus frequency divider 5 outputs will be judged selector 7 acquiescence gatings automatically to phase frequency detector 1.Concrete operating process is as follows: first by phase frequency detector 1, the first feedback signal of reference clock signal (reference clock) and the multi-modulus frequency divider of input 5 outputs is compared, convert two of phase frequency detector 1 to export short signal UP/DN control signals with reference to the frequency between clock signal and these two clock signals of the first feedback signal and phase error.When the frequency of reference clock signal or phase place surpass the frequency of the first feedback signal or phase place, UP output is high and DN output is low, otherwise UP output is low and DN output is high.
The UP/DN signal of phase frequency detector 1 output is directly exported to integrator 2, and after two inverters 9 are anti-phase, exports respectively UPB/DNB signal to filter 3 at zero point.When integrator 2 receives after UP/DN signal, will carry out integration to UP/DN signal, and integral result be outputed to the FREQUENCY CONTROL port of voltage controlled oscillator 4; Until the centre frequency of voltage controlled oscillator 4 reaches after locking frequency, the integrator 2 now impulse density of UP/DN signal approaches, and gain becomes zero, and frequency feedback loop starts by filter 3 controls at zero point; Zero point, filter 3 was mainly followed the tracks of inhibition to frequency feedback loop noise in bandwidth range.
Therefore, voltage controlled oscillator 4 is stabilized on fixed clock frequency under filter 3 actings in conjunction at integrator 2 and zero point.Wherein, clock signal clk 0, CLK90, CLK180 and the CLK270 of voltage controlled oscillator 4 output 4 road same frequencys, this 4 tunnel clock signal is phase difference 90 degree successively; This 4 tunnel clock signal can provide the multiple application such as SERDES sampling, CPU, bus synchronous etc. to use.
Shown in Fig. 2, integrator 2 comprises: the interconnective PMOS MP1 of grid and the 2nd PMOS MP2; The grid of the one PMOS MP1 meets reference current I altogether with drain electrode, and source electrode is connected with voltage VDD; The source electrode of the 2nd PMOS MP2 connects the drain electrode of the 3rd PMOS MP3, and the source electrode of the 3rd PMOS MP3 connects voltage VDD, and grid is connected with phase frequency detector 1 output UP signal; The interconnective NMOS MN1 of grid and the 2nd NMOS MN2; The grid of the one NMOS MN1 and drain electrode meet the reference current I with a PMOS MP1 grid homology altogether, and source electrode is connected with voltage VDD; The source electrode of the 2nd NMOS MN2 connects the drain electrode of the 3rd NMOS MN3, and the source electrode of the 3rd NMOS MN3 connects voltage VDD, and grid is connected with phase frequency detector 1 output UD signal; And the drain electrode of the drain electrode of the 2nd PMOS MP2, the 2nd NMOS MN2 all connects the grid of integration metal-oxide-semiconductor MPbig and the grid of the 4th PMOS MP4, and the source electrode of the drain electrode of integration metal-oxide-semiconductor MPbig, source electrode and the 4th PMOS MP4 all connects voltage VDD, and the drain electrode output current IO UT voltage controlled oscillator 4 of the 4th PMOS MP4.
The one PMOS MP1, a NMOS MN1 amplify by homology reference current I mirror image the output current that forms the 2nd PMOS MP2 and the 2nd NMOS MN2 respectively, and the 2nd PMOS MP2, the 2nd NMOS MN2 are subject to respectively by the control of the 3rd PMOS MP3, the 3rd NMOS MN3 of the UP/DN signaling switch of phase frequency detector 1 output and to integration metal-oxide-semiconductor MPbig output current, integration metal-oxide-semiconductor MPbig becomes to export to the 4th PMOS MP4 after voltage and carry out gain conversions to current integration, the 4th PMOS MP4 output control electric current I OUT to voltage controlled oscillator 4 as master control electric current.
Wherein, integration metal-oxide-semiconductor MPbig volume accounts for whole system more than 1/4.Wherein the internal gain X of integrator is: X=a*Gmp4; A is size (SIZE) ratio, a=the one PMOS MP1/ the 2nd PMOS MP2=the one NMOS MN1/ the 2nd NMOS MN2, and Gmp4 is the transadmittance gain of the 4th PMOS MP4.
As shown in Figure 3, zero point, filter 3 comprised: five PMOS MP5, six PMOS MP6, seven PMOS MP7, five NMOS MN5, six NMOS MN6 and the seven NMOS MN7 identical with the indirect relation of a PMOS MP1, the 2nd PMOS MP2, the 3rd PMOS MP3, a NMOS MN1, the 2nd NMOS MN2 and the 3rd NMOS MN3, wherein, the grid of the grid of the 7th PMOS MP7, the 7th NMOS MN7 connects respectively UPB/DNB signal (the UP/DN signal of phase frequency detector 1 output obtains UPB/DNB signal after inverter 9 is anti-phase); And the drain electrode of the drain electrode of the 6th NMOS MN6 and the 6th PMOS MP6 is connected and output current IO UT to the control end of voltage controlled oscillator 4, and the drain electrode of the drain electrode of the 6th NMOS MN6 and the 6th PMOS MP6 is all connected the 8th NMOS MN8 and the 9th NMOS MN9 in parallel.
The 5th PMOS MP5, the 5th NMOS MN5 give the 6th PMOS MP6, the 6th NMOS MN6 with reference to electric current I difference scaled mirror, but ratio multiplication factor is different from integrator 2; And by switch the 7th PMOS MP7, the 7th NMOS MN7, controlling output current respectively, the 7th PMOS MP7, the 7th NMOS MN7 accept UPB/DNB signal as switching signal.The drain electrode output current IO UT of the drain electrode of the 6th NMOS MN6 and the 6th PMOS MP6 will directly export to voltage controlled oscillator 4 control ends without conversion.
Wherein the grid of the 8th NMOS MN8 connects power supply, for together forming output equivalent resistance R equal with the input resistance of voltage controlled oscillator 4, the 9th NMOS MN9 is as filtering mos capacitance, and this electric capacity does not need very large, only with Requal, forms RC filter.
Wherein, zero point, filter 3 internal gain Y was: Y=b, b is size (SIZE) ratio, b=the 5th PMOS MP5/ the 6th PMOS MP6=the 5th NMOS MN5/ the 6th NMOS MN6.
In integrator 2 and zero point filter 3, X/Y is regulated to 0.1 left and right, just the size of integration metal-oxide-semiconductor MPbig can be reduced to 0.1 original left and right, further adjusting can taper to this integration metal-oxide-semiconductor MPbig below 1/10, facilitates integrated.Therefore, the present invention by regulate integrator 2 and zero point filter 3 internal gain, can effectively reduce integrated the chip size of clock generator of the present invention (chip size is CHIP AREA).
As shown in Figure 4, voltage controlled oscillator (VCO) 4 comprises: the delay cell of level Four cascade, form four groups of differential clocks, and the output of each delay cell is connected in series respectively an amplifier, and clock signal is amplified output by amplifier buffer.Be different from three grades of delay cells, three grades of delay cell output phases do not meet symmetrical requirement, therefore can only utilize one group.And this level Four delay cell can produce the symmetrical clock of 90 degree phase differences, four groups of clocks can utilize simultaneously, if therefore four signals are applied simultaneously.More than actual samples efficiency can reach 0.75*4=3 quilt.Wherein 0.75 is the actual frequency coefficient of sampling level Four voltage controlled oscillator 4, and 4 for allow sampling data passageway number simultaneously.
In conjunction with as Fig. 5 institute, the delay cell of level Four cascade has identical structure, take one of them delay cell to describe as example.Delay cell comprises:
Each delay cell comprises respectively: the difference oscillator consisting of two inverter U1 and U2; Two coupled transfer door T1 and T2, be used for the input-output cross-coupling of two inverter U1 and U2, to reduce deflection, improve greatly output duty cycle, the DC equilibrium point (DC balance) that simultaneously also can destroy four-level generator prevents voltage controlled oscillator 4 failures of oscillations and under metastable state state.
Wherein, a NMOS and a PMOS's is formed in parallel; And in two inverter U1 and U2, the source electrode of each PMOS be drawn out to together formation control port IOUT control export and is connected to integrator 2 and zero point filter 3, acceptance is from the control signal of integrator 2 and filter 3.
At frequency feedback loop, complete in the process of Frequency Synchronization, judgement selector 7 is by the monitoring remaining operating state, with the loop that automatically switches.Be below the concrete operation principle of judgement selector 7:
As shown in Figure 6, judgement selector 7 comprises: for reference source counter and the feedback counter for first feedback signal (Feedback1 clock) of multi-modulus frequency divider 5 outputs is counted that the reference count signal (REF) of input is counted; Be connected to the trigger comparator of reference source counter output, for count results and the threshold value comparison obtaining with reference to source counter, until the count results of reference source counter reaches certain threshold value, export a triggering signal; Connect respectively the output of reference source counter, the mould calculator of the output of the output of feedback counter, trigger comparator, for the mould between computing reference source counter and feedback counter count value, the remainder after being namely divided by between computing reference source counter and feedback counter count value; Be connected to the threshold judgement device of mould calculator output, for selecting according to the mould value (remainder) of mould calculator output, second feedback signal (Feedback2 clock) of first feedback signal (feedback1 clock) of multi-modulus frequency divider 5 outputs or phase synthesizer 6 outputs switched to phase frequency detector 1.
Specifically, first judgement selector 7 is counted with reference to (REF) and feedback clock (feedback1 clock) input respectively by reference to source counter and feedback counter.Until the count results of reference source counter reaches certain threshold value, trigger comparator makes mould calculator start the remainder after mould between computing reference source counter and feedback counter count value is namely divided by output triggering level, remainder will be adjudicated through threshold judgement device, when enough hour of numerical value, mean frequency basic synchronization, judgement selector 7 is switched to phase feedback loop, i.e. second feedback signal (Feedback2 clock) of gating phase synthesizer 6 outputs is to phase frequency detector 1.
After being switched to phase feedback loop, phase correlator 8 and phase synthesizer 6 start to enter operating state.Wherein, phase correlator 8 is responsible for calculating the phase difference between the synchrodata DATA of input and the output clock of voltage controlled oscillator 4, and convert thereof into can control phase synthesizer 6 control signal, make four phase clock signal (CLK0 of 6 pairs of voltage controlled oscillators of phase synthesizer, 4 outputs, CLK90, CLK180 and CLK270) carry out aliasing and obtain a new clock signal of same frequency (i.e. the second feedback signal) with new clock phase, and this is fed back to phase frequency detector 1 for correcting voltage controlled oscillator 4 clock phases with frequently new clock signal, until the clock phase of voltage controlled oscillator 4 is consistent with the phase place of synchrodata DATA.
In conjunction with Fig. 7, phase correlator 8 structures and operation principle are as follows:
First the synchrodata DATA of input enters phase calculation circuit, calculates corresponding phase place residual, then exports to decoder; Decoder carries out decoding to this phase place residual, and the binary control signal DECOUT<0:7> that it is translated into 8 controls DAC(Digital-to-Analog Converter digital-analog convertor) and phase synthesizer 6; And decoder is mapped to the phase place residual of this control signal DECOUT<0:7> on four interval phase place circle diagrams of a 0-360 degree, corresponding A 1:0-90 degree, A2:90-180 degree, A3:180-270 degree, four groups of phase control pair of A4:270-0 degree, and control DAC and produce two simulation control level IP and the IN for control phase synthesizer 6.
Schematic diagram in conjunction with the circuit of phase calculation shown in Fig. 8.Its working method is as follows: first the synchrodata DATA of input is respectively through four register samplings, sampling clock is respectively the four phase clock signals (CLK0, CLK90, CLK180 and CLK270) of voltage controlled oscillator 4 outputs, and four registers are exported respectively Q0, Q90, Q180, tetra-sampled datas of Q270; Then, by 4 exclusive-OR operators, respectively Q0 and Q90, Q90 and Q180, Q180 and Q270, Q270 and tetra-groups of output sampled signals of Q0 being done to XNOR operates, operating result export to accumulator zero adding, a criterion subtracting does cumulative operation, accumulation result is current phase place residual.
After the decoded device translation of phase place residual, will enter DAC, the detailed circuit diagram of DAC as shown in Figure 9.DAC is an analog current change-over circuit, for being converted into corresponding binary system electric current by latter 5 of decoder output, wherein SA1 ~ SA6 and SB1 ~ SB6 are complementary switch corresponding to 6 (being DECOUT<2:7>) after decoder.DAC consists of two groups of quadrature current transducers respectively, each transducer contains a R2R electric resistance array (R2R ladder), be used for the electric current output of R2R ladder with an operational amplifier, two groups of signals of SA/SB are for being strobed into VCOM or two voltage signals of VPLUS by corresponding resistance terminal point, two voltage signals are constant signals of independent from voltage, and are produced by special reference circuit.VCOM/VPLUS will produce corresponding binary system current component after accessing R2R electric resistance array by switch, after several groups of switching currents are synthetic, through operational amplifier, be output into IP or IN current component, and further gating is exported to two phase place attenuators of phase synthesizer 6 correspondences.Get Vdelta=VPLUS-VCOM, the current ratio that each switch is controlled is as shown in table 1 below:
Table 1
Wherein, the circuit diagram of phase synthesizer 6 as shown in figure 10, by four groups of amplitude fading cell formations, the gating of every group of unit is done DECOUT<0:1> decoding by the front two of decoder and is obtained that tetra-gating signals of ST0/ST90/ST180/ST270 are controlled and the corresponding S0/S90/S180/S270 of conducting exports IP/IN to DAC, and only have two adjacent amplitude fading cell operation at every turn, corresponding tetra-phase place regions of A1 ~ A4, attenuation units be input as 4 groups of VCO output clock CLK0/CLK90/CLK180/CLK270, it will to these four clocks wherein two groups do corresponding decay, to form the synthetic component of two quadratures of synthetic clock.Concrete decode results is as shown in table 2 below:
Table 2
The attenuation amplitude of each attenuation units is controlled by the output current IP/IN of DAC.After attenuation units gating, the output current of DAC just can be linked into by switch as0/as90/as180/as270 the VC(VC0/VC90/VC180/VC270 of attenuator) point, for generation of decay bias voltage, in addition the output of attenuator connects together, produce synthetic clock signal, to offer phase frequency detector 1, make phasing.
Now with a kind of operating state, specifically introduce.As Figure 10, when decode results is positioned at the clock phase in A0 region for synthesizing, ST0/ST90 signal becomes significance bit and opens MOS switch MNs3 and MNs8, makes MNs1/MNs2 and MNs6/MNs7 accept the IP/IN electric current from DAC from VC0 and VC90; According to IP/IN size of current, the grid of MNs4/MNs9 is produced to corresponding voltage bias, make the electric current of MNs4/MNs9 be equal to the output current IP/IN of DAC; And the electric discharge of MNs4/MNs9 is subject to these two switches controls of MNs5/MNs10, their switching signal is respectively CLK0/CLK90; So far two amplitudes are subject to the electric current of DAC control by two phaseswitch conductings of quadrature, and resultant current will be by CLKOUT output clock.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. for a clock generator for integrated circuit, it is characterized in that, described clock generator comprises:
Phase frequency detector, for detection of the reference clock signal phase place of input and the phase difference between feedback signal, produces output signals UP and output signal DN;
Be connected to the integrator of phase frequency detector output, for output signals UP and output signal DN are carried out to integral operation;
Be connected to the filter at zero point of phase frequency detector reversed-phase output, for carry out filtering after integrator stable output;
Control end connects the voltage controlled oscillator of integrator output terminal, for exporting the 4 tunnels clock signal of phase difference 90 degree successively;
The multi-modulus frequency divider that connects voltage controlled oscillator output, for 4 tunnel clock signals of voltage controlled oscillator output are carried out to frequency division processing, output the first feedback signal;
The phase correlator that connects voltage controlled oscillator output, for calculating the phase difference between the synchrodata of input and 4 tunnel clock signals of voltage controlled oscillator output, converts the control signal of control phase synthesizer to;
The phase synthesizer that connects respectively voltage controlled oscillator output, phase correlator output, for the 4 tunnel clock signals to voltage controlled oscillator output according to the control signal of phase correlator output
mix stack, output the second feedback signal;
Be connected to the judgement selector between multi-modulus frequency divider output, phase synthesizer output and the feedback input end of phase frequency detector, for optionally the first feedback signal being switched and is exported to phase frequency detector, make 4 tunnel clock signals and the reference clock signal same frequency of voltage controlled oscillator output, and after the clock signal and reference clock signal same frequency of voltage controlled oscillator output, control optionally the second feedback signal is switched and exported to phase frequency detector, the phase place of reference clock signal and the phase preserving of synchrodata are synchronizeed;
Integrator comprises:
The interconnective PMOS of grid and the 2nd PMOS, and the source electrode of the 2nd PMOS connects the drain electrode of the 3rd PMOS that is subject to the control of phase frequency detector output signals UP;
The interconnective NMOS of grid and the 2nd NMOS, and the source electrode of the 2nd NMOS connects the drain electrode of the 3rd NMOS that is subject to phase frequency detector output signal DN control;
The drain electrode of the drain electrode of the 2nd PMOS, the 2nd NMOS connects the grid of integration metal-oxide-semiconductor and the grid of the 4th PMOS respectively, by the drain electrode output of the 4th PMOS, controls electric current to voltage controlled oscillator.
2. according to claim 1 for the clock generator of integrated circuit, it is characterized in that, described clock generator also comprises:
Two inverters that connect between phase frequency detector output and zero point filter input end are output signals UP B and output signal DNB for phase frequency detector output signals UP and output signal DN are distinguished anti-phase.
3. according to claim 2 for the clock generator of integrated circuit, it is characterized in that, zero point, filter comprised:
Interconnective the 5th PMOS of grid and the 6th PMOS, and the source electrode of the 6th PMOS connects the drain electrode of the 7th PMOS that is subject to inverter output signals UP B control;
Interconnective the 5th NMOS of grid and the 6th NMOS, and the source electrode of the 6th NMOS connects the drain electrode of the 7th NMOS that is subject to inverter output signal DNB control;
The drain electrode of the drain electrode of the 6th PMOS, the 6th NMOS connect respectively for the input resistance with voltage controlled oscillator together form the 8th nmos source of output equivalent resistance, as the 9th NMOS grid of filtering mos capacitance.
4. according to claim 3 for the clock generator of integrated circuit, it is characterized in that, by regulate integrator internal gain X and zero point filter the ratio of internal gain Y reduce the size of integration metal-oxide-semiconductor;
Wherein, the internal gain X of integrator is: X=a*Gmp4, and a is dimension scale, and a=the one PMOS/two PMOS=the one NMOS/two NMOS, Gmp4 is the transadmittance gain of the 4th PMOS;
Zero point, the internal gain Y of filter was: Y=b, b is dimension scale, b=the 5th PMOS/six PMOS=five NMOS/six NMOS.
5. according to claim 4 for the clock generator of integrated circuit, it is characterized in that, X/Y is below 0.1 or 0.1.
6. according to claim 1 for the clock generator of integrated circuit, it is characterized in that, voltage controlled oscillator comprises:
The delay cell of level Four cascade, forms four groups of differential clock signals;
Output in each delay cell is connected in series respectively an amplifier, and four groups of differential clock signals amplify output by 4 amplifier buffers respectively.
7. according to claim 1 for the clock generator of integrated circuit, it is characterized in that, judgement selector comprises:
For the reference source counter that the reference count signal of input is counted;
For the feedback counter that the first feedback signal of multi-modulus frequency divider output is counted;
Be connected to the trigger comparator of reference source counter output, for count results and the threshold value comparison obtaining with reference to source counter, until the count results of reference source counter reaches certain threshold value, export a triggering signal;
Connect respectively the output of reference source counter, the mould calculator of the output of the output of feedback counter, trigger comparator, for the mould between computing reference source counter and feedback counter count value;
Be connected to the threshold judgement device of mould calculator output, for according to the mould of mould calculator output, select the second feedback signal of the first feedback signal of multi-modulus frequency divider output or phase synthesizer output to switch to phase frequency detector.
8. according to claim 1 for the clock generator of integrated circuit, it is characterized in that, phase correlator comprises:
Phase calculation circuit, for calculating the phase place residual of the synchrodata of input;
Be connected to the decoder of phase calculation circuit output end, phase place residual for the output of phase calculation circuit is translated into the binary control signal DECOUT<0:7> of 8, and the phase place residual of control signal DECOUT<0:7> is mapped on four interval phase place circle diagrams of a 0-360 degree;
The DAC that connects decoder output, for simulating control level IP and IN according to two of binary control signal DECOUT<0:7> generation control phase synthesizer.
9. according to claim 8 for the clock generator of integrated circuit, it is characterized in that, phase calculation circuit comprises:
4 registers, for the synchrodata of input is sampled respectively, sampling clock is respectively 4 clock signals of voltage controlled oscillator output, and 4 registers are exported respectively sampled data Q0, sampled data Q90, sampled data Q180 and sampled data Q270;
4 exclusive-OR operators, make XNOR operation for then respectively tetra-groups of sampled data Q0 and sampled data Q90, sampled data Q90 and sampled data Q180, sampled data Q180 and sampled data Q270, sampled data Q270 and sampled data Q0 being exported to sampled datas;
Accumulator, is connected to the output of 4 exclusive-OR operators, for to the Output rusults of 4 exclusive-OR operators zero adding, a criterion subtracting does cumulative operation, accumulation result is current phase place residual.
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