CN104079315B - Multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators - Google Patents
Multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators Download PDFInfo
- Publication number
- CN104079315B CN104079315B CN201410287623.1A CN201410287623A CN104079315B CN 104079315 B CN104079315 B CN 104079315B CN 201410287623 A CN201410287623 A CN 201410287623A CN 104079315 B CN104079315 B CN 104079315B
- Authority
- CN
- China
- Prior art keywords
- frequency
- output
- signal
- controlled oscillator
- voltage controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a kind of multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators, the generator is distributed by rational frequency, it can be achieved that the differential signal output that the output of I/Q carrier waves and 5~10GHz, 1.5~3GHz that 0.1~5GHz is continuously covered continuously cover；Simultaneously, by configuring programmable charge pump (102), loop filter (103) parameter, multichannel voltage controlled oscillator (104) and corresponding first multiple selector (105), Pyatyi removes two divided-frequency link (109) and corresponding second multiple selector (110), third multiple selector (112), the carrier signal under different loop bandwidths, out of phase noise, different power consumption water product, the various frequencies of variable locking time can be generated, realizes the generation of multi-standard performance reconfigurable type multiple I/Q quadrature carriers.
Description
Technical field
The present invention relates in wireless communications application radio frequency radio transceiver technical field more particularly to a kind of multi-standard
Energy reconfigurable type multiple I/Q quadrature carrier generators, the generator are based on fraction division structure, can generate 0.1~5GHz and continuously cover
The differential signal output that the I/Q carrier waves of lid export and 5~10GHz, 1.5~3GHz are continuously covered.
Background technology
Frequency synthesizer is the important component of transceiver, it provides local oscillated signal for transceiver, it
Performance quality directly decides the performance level of receive-transmit system, and its power consumption also tends to occupy the very big ratio of transceiver overall power
Weight.In recent years, being constantly progressive with wireless communication technique, more and more transceivers develop to multimode multi-standard, occur
Many broadband multi-bands meet the single terminal end transceiver chip of a variety of communication standards.It is such as the key composition of transceiver
Frequency synthesizer needs local oscillation signal frequency range to be offered very wide in receive-transmit system, and lock is required under distinct communication standards
Fix time, phase noise performance etc. it is different, if realized respectively with multiple frequency synthesizers, often system is made to answer
Hydridization, cost will be also difficult to control.In order to reduce cost, integrated level is improved, it would be desirable to have single frequency synthesizer that can meet
To the demand of local oscillation signal under various communication standards；Meanwhile if frequency synthesizer performance (including locking time, power consumption water
Flat, phase noise etc.) it can realize reconstruct, its application will be made to become more flexible.
Invention content
In view of this, the main purpose of the present invention is to provide a kind of multi-standard performance reconfigurable type multiple I/Q quadrature carriers hairs
Raw device, can meet demand of the transceiver to the local oscillator of the various standards of 5GHz or less frequency ranges.The multi-standard performance is restructural
Multichannel voltage controlled oscillator need at least cover 5~10GHz in Formulas I/Q quadrature carrier generators, in this way by except two divided-frequency link
It is possible that the orthogonal i/q signal output of 0.1~5GHz of generation.
In order to achieve the above objectives, the present invention provides a kind of multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators, should
I/Q quadrature carrier generators include：Phase frequency detector, the output for reference signal and programmable multi-modulus frequency divider to input
The frequency and phase of signal are compared；Programmable charge pump is controlled by phase frequency detector output signal, generates charge and discharge electricity
Stream, and then charge and discharge are carried out to loop filter, change its output voltage；Loop filter is used for programmable charge pump
Charge and discharge electric current converts the analog voltage of multichannel control oscillator in order to control；Multichannel voltage controlled oscillator is controlled by the analog voltage
System generates required phase lock loop locks frequency range；First multiple selector is used for the output signal of multichannel voltage controlled oscillator
Which chosen into row of channels, to determine voltage controlled oscillator providing frequency of oscillation by；Except two pre-dividers, for first will to be come from
The output signal of multiple selector is carried out except two pre- frequency dividings, to reduce the maximum operating frequency that may be programmed multi-modulus frequency divider；It can compile
Journey multi-modulus frequency divider, the frequency dividing ratio for controlling phaselocked loop major loop, the final locking frequency for determining phaselocked loop；Major loop exports
Buffer, for exporting phaselocked loop major loop signal；Pyatyi removes two divided-frequency link, the I/Q for generating 0.1~5GHz
Signal, and two-way is divided to be respectively outputted to Receiver And Transmitter；Second multiple selector and third multiple selector, for five
Grade is chosen except the output signal of two divided-frequency link into row of channels；To receiver output buffer and transmitter output buffer is arrived,
For the two paths of signals to be respectively outputted to Receiver And Transmitter；Input buffer, for receive external input signal into
Enter Pyatyi and removes two divided-frequency link.
It can be seen from the above technical proposal that the invention has the advantages that：1) multi-standard provided by the invention
Can reconfigurable type multiple I/Q quadrature carrier generators, using standard CMOS process, single-chip integration is realized, meet practical application it is low at
This requirement, same chip provide the I/Q local oscillated signals of all frequency ranges in 0.1~5GHz of covering.Meanwhile the present invention uses
Multichannel voltage controlled oscillator, programmable charge pump, loop filter, the first multiple selector, the second multiple selector, third multichannel
The modules such as selector so that power consumption levels, phase lock loop lock on time, loop bandwidth and the phase noise of the carrier generator
Energy etc. can realize reconstruct.2) multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators provided by the invention, as a result of
Programmable charge pump, charging and discharging currents can be programmed configuration, thus the automatic adjustment to loop bandwidth may be implemented.3) originally
The multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators provided are invented, multichannel is voltage-controlled to shake due to being used in phaselocked loop
Device is swung, the whole tuning range of voltage controlled oscillator covers 5~10GHz and 1.5~3GHz, and forms the multichannel voltage controlled oscillator
Each independent voltage controlled oscillator characteristic it is different, characteristic differ place will include：Frequency coverage difference, power consumption
Horizontal different, phase noise performance difference, composed structure are different.4) multi-standard performance reconfigurable type multiple I/Q provided by the invention is being just
It is for the buffer the parallel combined structure designed by different operating frequency range to hand over carrier generator, used first multiple selector
At to not only targetedly enhance carrying load ability but also reduce the work(of the cycle of phase-locked loop when different frequency range is applied
Water consumption is flat.5) multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators provided by the invention, using programmable multi-modulus frequency divider
Come complete on a large scale frequency dividing ratio control, to realize phaselocked loop major loop 5~10GHz and 1.5~3GHz Frequency Locking,
It also disclosure satisfy that different reference frequency configuration (10~50MHz) requirements simultaneously.6) multi-standard performance provided by the invention can weigh
Structure Formulas I/Q quadrature carrier generators exports phaselocked loop major loop local oscillator using major loop output buffer, it should be noted that
It is that major loop output signal is differential signal rather than i/q signal.The local oscillation signal of major loop output is 5~10GHz and 1.5
~3GHz can provide signal source output for other chips.7) multi-standard performance reconfigurable type multiple I/Q quadrature carriers provided by the invention
Generator, generates the i/q signal of 0.1~5GHz using Pyatyi except two divided-frequency link, and final output is to receiver and transmitting
Machine.Except two divided-frequency can ensure that there is the i/q signal of output good matching, Pyatyi to export except the cascade of two-divider
Frequency is minimum can to reach 0.1GHz or less.8) multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators provided by the invention,
The selection that two divided-frequency chain output signal access is removed to Pyatyi is realized using the second multiple selector and third multiple selector,
Output signal is finally respectively supplied to receiver output buffer and arrives transmitter output buffer.
Description of the drawings
Fig. 1 is a kind of multi-standard performance reconfigurable type multiple I/Q quadrature carrier generator system block diagrams provided by the invention；
Fig. 2 is that may be programmed charge in multi-standard performance reconfigurable type multiple I/Q quadrature carrier generator systems provided by the invention
One example circuit block diagram of pump；
Fig. 3 is multi-standard performance reconfigurable type multiple I/Q quadrature carrier generator system loop filters provided by the invention
An example circuit diagram；
Fig. 4, which is that multichannel is voltage-controlled in multi-standard performance reconfigurable type multiple I/Q quadrature carrier generator systems provided by the invention, to shake
Swing the example circuit diagram of a voltage controlled oscillator in device；
Fig. 5, which is that multichannel is voltage-controlled in multi-standard performance reconfigurable type multiple I/Q quadrature carrier generator systems provided by the invention, to shake
It swings and frequency preset function can be achieved in device to realize an example electricity of the mixed signal voltage controlled oscillator of loop quick lock in
Lu Tu；
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
The present invention proposes a kind of multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators, it is a kind of frequency synthesizer.
Due in 5GHz frequency ranges below, having concentrated wireless communication standards much more very, such as wireless wide area network 2G~3G, wirelessly
Wide area network 4G, Metropolitan Area Network (MAN), WLAN, wireless body area network, medical communication, digital broadcasting DTV etc., thus this hair
The bright rate-adaptive pacemaker range by the quadrature carrier generator is designed in 5GHz or less.Meanwhile major loop provides output port, it can
To provide the differential signal output of 5~10GHz；And it divides output par, c and then provides external signal and be input to except two divided-frequency link
Port, between chip realize MIMO provide platform.
Fig. 1 is the system block diagram of multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators provided by the invention, the carrier wave
Generator includes：Phase frequency detector 101, programmable charge pump 102, loop filter 103, multichannel voltage controlled oscillator 104, first
Multiple selector 105 removes two pre-dividers 106, may be programmed multi-modulus frequency divider 107, major loop output buffer 108, Pyatyi is removed
Two divided-frequency link 109, the second multiple selector 110 arrive receiver output buffer 111, third multiple selector 112, to hair
Penetrate machine output buffer 113, input buffer 114, nonvolatile memory 115, digital processing unit 116.
Phase frequency detector 101 is used for the frequency of the output signal to the reference signal and programmable multi-modulus frequency divider 107 of input
Rate and phase are compared.Phase frequency detector 101 generates corresponding pulse voltage according to the difference on the frequency and phase difference of two signals
Signal, with this come drive charge pump to loop filter carry out charge and discharge.One input terminal of phase frequency detector 101 and outside
Reference signal FrefConnection, the output signal F of another input terminal and programmable multi-modulus frequency divider 107divConnection, output end with
The input terminal of programmable charge pump 102 connects.The output voltage Pulse Width Control programmable charge pump 102 of phase frequency detector 101
Charge and discharge.
Programmable charge pump 102 is controlled by 101 output signal of phase frequency detector, charge and discharge electric current is generated, to change ring
The control voltage of path filter output.The input terminal of programmable charge pump 102 is connect with the output end of phase frequency detector 101, defeated
Outlet is connect with the input terminal of loop filter 103, meanwhile, output C [3 of the working condition by digital processing unit 116:0] it controls
System.Programmable charge pump 102 is preferably that charge and discharge electric current can configure charge pump, and in of the invention, it is carried out by 4 position digital signals
Control, size of current can be adjusted to 15I from unitary current I, so as to the loop bandwidth using digital processing unit 116 to phaselocked loop
It is adjusted.
Loop filter 103 is realized using low-pass filter, for turning the charge and discharge electric current of programmable charge pump 102
Turn to the analog voltage of control multichannel voltage controlled oscillator 104.The input terminal of the loop filter 103 and programmable charge pump 102
Output end connection, output end connect with the input terminal of multichannel voltage controlled oscillator 104.
Multichannel voltage controlled oscillator 104, the oscillator signal for generating required 5~10GHz and 1.5~3GHz, oscillation frequency
Rate is by digital signal A [2:0]、B[6:0]、P[5:0] and the output voltage of loop filter 103 codetermines.Wherein, [2 A:0]
For the selection of voltage controlled oscillator, it has 3 control bits, each controls the Enable Pin of corresponding voltage controlled oscillator respectively, when
It needs to choose one of voltage controlled oscillator when being worked, corresponding control bit is configured to high level, other all controls
Position is then configured to low level；B[6:0] it is used for the selection of sub-band, it there are 7 control bits, each controls voltage controlled oscillation respectively
The bit switch of capacitor array in device changes capacitor array integral capacitor value size by opening, turning off switch, to change pressure
Control the frequency of oscillation of oscillator；P[5:0] to contain the preset signal of the mixed signal voltage controlled oscillator of frequency preset module
Setting, as A [2:When 0] choosing the mixed signal voltage controlled oscillator and being worked, preset module is according to P [5:0] configuration with come
The output voltage of loop filter generates control voltage and is applied to voltage controlled oscillator core in the heart jointly, to generate required shake
Swing frequency.The input terminal of multichannel voltage controlled oscillator 104 is connect with the output end of loop filter 103, output end and the first multichannel
The input terminal of selector 105 connects, meanwhile, output A [2 of the working condition by digital processing unit 116:0]、B[6:0]、P[5:
0] control.Multichannel voltage controlled oscillator 104 contains three mutually independent voltage controlled oscillators, wherein the pressure controlled by A [2]
It controls oscillator and covers 5~10GHz frequency ranges, there is extraordinary phase noise performance；The voltage controlled oscillator controlled by A [1]
1.5~3GHz frequency ranges are covered, there is low-down power consumption；There is frequency preset work(by the voltage controlled oscillator of A [0] controls
Can, so as to realize quick lock in, greatly shorten locking time.According to practical application request, (such as power consumption requirements, frequency range are wanted
Ask, locking time requirement, phase noise requirements etc.), digital processing unit 116 chooses some voltage controlled oscillator and works, structure
At phaselocked loop major loop, the frequency configuration of wide-band may be implemented except two divided-frequency link 109 for cooperation Pyatyi.
First multiple selector 105, for choosing the output signal of multichannel voltage controlled oscillator 104 into row of channels, with certainly
It is fixed specifically which voltage controlled oscillator to provide frequency of oscillation by.The input terminal of the multiple selector 105 and multichannel voltage controlled oscillator
104 output end connection, output end respectively with except two pre-dividers 106, Pyatyi except two divided-frequency link 109 and major loop output it is slow
Rush the output end connection of device 108；Meanwhile working condition is by the output MUX1 [2 of digital processing unit 116:0] control.First
Multiple selector 105 for the buffer the parallel combined designed by different operating frequency range by constituting, each buffer is by MUX1
[2:0] control individually can be opened or be closed, and the buffer does not consume power consumption after closing.
Except two pre-dividers 106, for carrying out the output signal from the first multiple selector 105 except two pre- frequency dividings,
To reduce the maximum operating frequency that may be programmed multi-modulus frequency divider 107, power consumption is saved.This except two pre-dividers 106 input terminal with
The output end of multiple selector 105 connects, and output end is connect with the output end of programmable multi-modulus frequency divider 107.
Programmable multi-modulus frequency divider 107 is used for controlling the signal F that phaselocked loop feeds back to phase frequency detector 101divFrequency dividing
Than the final locking frequency for determining phaselocked loop.Due to reference signal FrefFrequency be certain, FdivFrequency finally also will be with
FrefUnanimously, its frequency dividing ratio will be changed by changing the configuration of programmable multi-modulus frequency divider 107, to finally change voltage controlled oscillator
Frequency of oscillation, realize the control to locking frequency.This may be programmed the input terminal of multi-modulus frequency divider 107 and removes two pre-dividers
106 output end connection, output end are connect with the input terminal of phase frequency detector 101, meanwhile, working condition is by digital processing unit
116 output M [11:0] control.In the present invention, programmable multi-modulus frequency divider 107 controls its frequency dividing by 12 position digital signals
Than size, it is made of 8 grade of 2/3 frequency unit and 4 frequency dividing ratio extension logic units, frequency dividing ratio ranging from 16~511, with
Meet the job requirement of broadband phase-looked loop.
Major loop output buffer 108 is for exporting phaselocked loop major loop signal.The major loop output buffer
108 input terminal is connect with the output end of multiple selector 105, and output end is defeated to provide phaselocked loop major loop local oscillation signal outside piece
Go out.
Pyatyi is used for generating the i/q signal of 0.1~5GHz except two divided-frequency link 109, and two-way is divided to be respectively outputted to receive
Machine and transmitter.The Pyatyi is buffered except the input terminal of two divided-frequency link 109 and the first multiple selector 105, external signal input
The output end of device 114 connects, and output end connects with the output end of the second multiple selector 110 and third multiple selector 112 respectively
It connects；Meanwhile working condition is by the output N [4 of digital processing unit 116:0] control.Pyatyi is except two divided-frequency link 109 is by 5
It is constituted except two-divider cascades, per level-one except two-divider is all made of current mode logic (CML), the defeated of I/Q forms can be generated
Go out signal.It is controlled preceding N by 5 position digital signals1(1≤N1≤ 5) grade removes the unlatching of two-divider, and minimum 2 are removed, most to realize
Height is exported except 32 frequency dividing.
Second multiple selector 110 and third multiple selector 112, the output for removing two divided-frequency link 109 to Pyatyi
Signal is chosen into row of channels.The input terminal of second multiple selector 110 with Pyatyi except 109 output end of two divided-frequency link is connect, it is defeated
Outlet is connect with to receiver output buffer 111, meanwhile, output MUX2 [4 of the working condition by digital processing unit 116:0]
Control.The input terminal of third multiple selector 112 and Pyatyi are connect except the output end of two divided-frequency link 109, output end with arrive
Transmitter output buffer 113 connects, meanwhile, output MUX3 [4 of the working condition by digital processing unit 116:0] control.
The buffer structure that second multiple selector 110 and third multiple selector 112 are directed to by 5 designed by different operating frequency range
At they are connected to Pyatyi except the every level-one of two divided-frequency link 109 removes the output end of two-divider, respectively by believing with 5 bit digitals
Number control the wherein opening of some buffer and shutdown.When Pyatyi removes the preceding N of two divided-frequency link 1091(1≤N1≤ 5) grade removes two points
When frequency device is opened, meaning frequency synthesizer needs to choose N1Grade is exported except the divided down version of two-divider, thus second
With this grade except the buffer that two-divider is connected will be opened in multiple selector 110 or third multiple selector 112, and it is other slow
Device is rushed by Close All, to realize the selection of required frequency.
It is used to two paths of signals being respectively outputted to receiver output buffer 111 and to transmitter output buffer 113
Receiver And Transmitter.Input terminal to receiver output buffer 111 is connect with the output end of multiple selector 2 110, defeated
Outlet for piece outside receiver local oscillation signal is provided.To the input terminal and multiple selector 3 112 of transmitter output buffer 113
Output end connection, output end for piece outside transmitter local oscillation signal is provided.
Input buffer 114 enters Pyatyi except two divided-frequency link 109 for receiving external input signal.The input buffer
114 input terminal connection external signal input, output end is with Pyatyi except the input terminal of two divided-frequency link 109 is connect.
Major loop output buffer 108 arrives receiver output buffer 110, arrives the realization pair of transmitter output buffer 112
Output signal buffers, and enhances its carrying load ability, makes to be isolated outside signal and piece in piece.
Nonvolatile memory 115, input terminal are connect with the output of digital processing unit 116, output end and digital processing
The input connection of device 116, READ and WRITE control reading and the ablation process of the nonvolatile memory 115 respectively.
Digital processing unit 116, input terminal receive externally input programmed configurations data and come from non-volatile memories
115 read data of device, output end and programmable charge pump 102, multichannel voltage controlled oscillator 104, the first multiple selector
105, may be programmed multi-modulus frequency divider 107, N grade except two divided-frequency link 109, the second multiple selector 110, to receiver output buffer
Device 111, third multiple selector 112 are connected to transmitter output buffer 113 and input buffer 114.Digital processing unit
The number configuration of the 116 entire multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators of control, inside further comprise Σ Δ tune
Device module processed, frequency sampling module, frequency comparison module, linear interpolation computing module.
Based on the system block diagram of the multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators described in Fig. 1, Fig. 2 gives
One example circuit block diagram of programmable charge pump 102 provided by the invention.The charge pump is the fully differential electricity of current programmable
Lotus pumps, and is made of programmable reference current module 201 and 202 two parts of charge pump core module.Its input signal UP and DN by
Phase frequency detector 101 provides, and output signal OUTP and OUTN are then supplied to loop filter 103.Programmable reference current module
201 by 4 bit digital signal C [3:0] it controls, realizes that output reference current size is adjusted to 15I from unitary current I.Charge pump
Nucleus module 202 is controlled by input signal UP and DN, and when UP is high, OUTP and OUTN are to loop filter for output signal
103 charge, its output voltage is made to increase；When DN is high, output signal OUTP and OUTN carries out loop filter 103
Electric discharge makes its output voltage decline.The size of current of charge and discharge is then equal to the reference electricity that programmable reference current 201 is provided
The adjustment to PLL loop bandwidth may be implemented by adjusting the size of charge and discharge electric current in the size of stream.Source charge point
Not by pipe discharge, eliminate charge share effect, and effectively reduce the current source turn-off time.Current replication branch
In switch corresponding with its respectively
Based on the system block diagram of the multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators described in Fig. 1, Fig. 3 gives
One example circuit diagram of loop filter 103 provided by the invention.The loop filter is that differential-input differential exports three ranks
Low-pass filter can realize the adjusting to loop characteristics such as loop bandwidths by adjusting device parameters.Input terminal CPOUT_P and
CPOUT_N is provided by the output OUTP and OUTN of programmable charge pump 102 respectively, and output end VC_P and VC_N be then supplied to it is more
Road voltage controlled oscillator 104 is as control voltage.The loop filter 103 is by resistance RP2,RP3,RN2,RN3With capacitance CP1,CP2,CP3,
CN1,CN2,CN3Composition.Wherein, CP1,CP2,RP3One end all connect with CPOUT_P, and CP1The other end and GND () connect,
CP2The other end and RP2One end connection, RP3The other end then connect with VC_P；RP2One end and CP2Connection, the other end then with
GND connections；One end of CP3 is connect with VC_P, and the other end is then connect with GND.CN1,CN2,RN3One end all connect with CPOUT_N,
And CN1The other end connect with GND, CN2The other end and RN2One end connection, RN3The other end then connect with VC_N；RN2's
One end and CN2Connection, the other end are then connect with GND；CN3One end connect with VC_N, the other end is then connect with GND.Based on Fig. 1
The system block diagram of the multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators, Fig. 4 give multichannel provided by the invention
The example circuit diagram of a voltage controlled oscillator in voltage controlled oscillator 104.The voltage controlled oscillator uses NMOS, PMOS or more complementation
Cross coupling structure.It is by PMOS cross-coupled pair pipes Mp1,Mp2, NMOS cross-coupled pair pipes Mn1,Mn2, switch K, inductance L, with
And 7 bit capacitor arrays 401, radio frequency MOS varactor module 402 collectively form.Wherein, Mp1, Mp2Source electrode link together,
And connect with one end of switch K, and the other end of K is then connect with supply voltage VDD.K is by the output from digital processing unit 116
A [2] is controlled, and when it is high, K is closed；When it is low, K is disconnected, which will not work.Mp1Drain electrode and Mn1
Drain electrode, Mn2Grid, Mp2Grid connection, and its grid then with Mp2Drain electrode, Mn2Drain electrode, Mn1Grid connection.Mn1,
Mn2Source electrode link together, and with GND () be connected.One end of inductance L is connected to Mp1Drain electrode, the other end is connected to Mp2
Drain electrode.The output end OUT_P of oscillator signal is connected to Mp1Drain electrode, OUT_N is then connected to Mp2Drain electrode, and the two connect
To the input terminal of the first multiple selector 105.One end of 7 bit capacitor arrays 401 is connected to Mp1Drain electrode, the other end is connected to
Mp2Drain electrode, it is by the output B [6 from digital processing unit 116:0] it controls, B [6:0] each controls 7 bits electricity respectively
Hold opening and the shutdown of a capacitance in array 401.As B [6:0] a certain position in from low get higher when, corresponding capacitance is beaten
It opens, the integral capacitor value of capacitor array increases, and the frequency of oscillation of voltage controlled oscillator reduces；As B [6:0] a certain position in becomes from height
When low, corresponding capacitance shutdown, the integral capacitor value of capacitor array reduces, and the frequency of oscillation of voltage controlled oscillator increases, to shape
At the coarse tuning to voltage controlled oscillator frequency of oscillation.One end of radio frequency MOS varactor module 402 is connected to Mp1Drain electrode, separately
One end is connected to Mp2Drain electrode, its capacitance size controlled by the output VC_P and VC_N for carrying out loop filter 103,
The variation of VC_P and VC_N is so that the capacitance of MOS varactor module 402 changes, to have adjusted shaking for voltage controlled oscillator
Frequency is swung, the fine tuning to voltage controlled oscillator frequency of oscillation is formd.Due to tail current source pipe and to its offer biasing
Biasing circuit is a prodigious noise source, and the 1/f noise of their pipes will deteriorate voltage controlled oscillator in the form of mixing
Phase noise, so selection anury current forms；This is conducive to optimize phase but also the oscillation amplitude of signal increased simultaneously
Position noiseproof feature.Entire frequency band is divided into 128 sub-bands by the voltage controlled oscillator using 7 bit capacitor arrays, is reduced voltage-controlled
The tuning range of voltage controlled oscillator has been expanded in the gain of oscillator；In addition, varactor uses accumulation-mode MOS varactor, control electricity
Pressure is inputted using difference form, to extend the frequency coverage of each sub-band.The voltage controlled oscillator frequency of oscillation model
5~10GHz of covering is enclosed, its main feature is that frequency of oscillation is high, tuning range is big, and phase noise performance is good.
Based on the system block diagram of the multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators described in Fig. 1, Fig. 5 gives
Frequency preset function can be achieved in multichannel voltage controlled oscillator 104 provided by the invention to realize the mixing letter of loop quick lock in
One example circuit diagram of number voltage controlled oscillator.The mixed signal voltage controlled oscillator is by preset module 501 and voltage controlled oscillator core
The heart 502 forms.The input terminal of preset module 501 is connect with the output end VC_P and VC_N of loop filter 103, output end then with
Keep under strict control oscillator core 502 input terminal connection；Meanwhile it is by the output signal P [5 from digital processing unit 116:0] control
System.The input terminal of voltage controlled oscillator core 502 is connect with the output end of preset module 501, output end OUT_P and OUT_N then with
The input terminal of first multiple selector 105 connects；Meanwhile it is by output signal A [0] and B [6 from digital processing unit 116:
0] control.The structure of voltage controlled oscillator core 502 is identical as the structure of voltage controlled oscillator shown in Fig. 4, should when A [0] is high
Voltage controlled oscillator core opens work, and when A [0] is low, which is stopped.B[6:0] it is voltage-controlled to control this
The working condition of 7 bit capacitor arrays in oscillator core.Control signal P [5 from digital processing unit 116:0] and B [6:0]
The output frequency of the voltage controlled oscillator is codetermined.When the multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators
When the mixed signal voltage controlled oscillator is worked in selection multichannel voltage controlled oscillator 104, there are two kinds of operating modes for system, divide
It Wei not operating mode 1 and operating mode 2.In operating mode 1, the control voltage of preset module loop filter in future 103
Input disconnects, and the input of preset module is biased to the fixed level of internal generation, by adjusting the defeated of digital processing unit 116
Go out P [5:0] and B [6:0], output frequency is recorded successively, and is written into nonvolatile memory 115.In this way, corresponding to every
A kind of P [5:0] and B [6:0] number combination, all there are one fixed rate-adaptive pacemakers for voltage controlled oscillator.This is that a frequency is adopted
Sample process, we in fact obtain P [5:0]、B[6:0] with the mapping relations of output frequency, which is stored in non-
In volatile memory 115, to avoid the increased workload of calibration institute and power consumption penalty is repeated.It is preset in operating mode 2
The input of module is connected to the control voltage output for carrying out loop filter 103.Digital processing unit 116 extracts non-volatile memories
The mapping relations stored in device, the number that required frequency is obtained by frequency comparison module and linear interpolation computing module are matched
Set P [5:0] and B [6:0], P [5 is set:0] and B [6:0] after by the output frequency of mixed signal voltage controlled oscillator be preset to
The very close place of required frequency, then reaches final locking by loop adjustment.When major loop frequency needs to carry out saltus step
When, digital processing unit 116 adjusts P [5:0]、B[6:0] and the control signal M [11 of programmable multi-modulus frequency divider 107:0], from
And the output frequency of mixed signal voltage controlled oscillator is preset to another frequency point within the very short time, due to controlling voltage
Variation is very small, thus will realize that loop relocks in a short period of time.The characteristics of mixed signal voltage controlled oscillator is
The loop-locking time can be largely reduced, but due to the presence of preset module, power consumption increased, phase noise performance
It can be declined.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect
Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the protection of the present invention
Within the scope of.
Claims (6)
1. a kind of multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators, using standard CMOS process, single-chip integration is realized,
It includes：
Phase frequency detector (101), the frequency of the output signal for the reference signal and programmable multi-modulus frequency divider (107) to input
Rate and phase are compared；
Programmable charge pump (102) is controlled by phase frequency detector (101) output signal, generates charge and discharge electric current, and then to ring
Path filter carries out charge and discharge, changes its output voltage；
Loop filter (103), for converting the charge and discharge electric current of programmable charge pump (102), multichannel is voltage-controlled in order to control shakes
Swing the analog voltage of device (104)；
Multichannel voltage controlled oscillator (104) is controlled the phase lock loop locks frequency range needed for generating by the analog voltage；
First multiple selector (105), for choosing the output signal of multichannel voltage controlled oscillator (104) into row of channels, with certainly
It is fixed which voltage controlled oscillator to provide frequency of oscillation by；
Except two pre-dividers (106), for carrying out the output signal from the first multiple selector (105) except two pre- frequency dividings,
To reduce the maximum operating frequency that may be programmed multi-modulus frequency divider (107)；
Programmable multi-modulus frequency divider (107), the frequency dividing ratio for controlling phaselocked loop major loop, the final locking frequency for determining phaselocked loop
Rate；
Major loop output buffer (108), for exporting phaselocked loop major loop signal；
Pyatyi removes two divided-frequency link (109), the i/q signal for generating 0.1~5GHz, and two-way is divided to be respectively outputted to receiver
And transmitter；
Second multiple selector (110) and third multiple selector (112), for removing the defeated of two divided-frequency link (109) to Pyatyi
Go out signal to choose into row of channels；
To receiver output buffer (111) and transmitter output buffer (113) is arrived, it is defeated for distinguishing the two paths of signals
Go out to Receiver And Transmitter；
Input buffer (114) enters Pyatyi except two divided-frequency link (109) for receiving external input signal；
Wherein, programmable charge pump (102) is that charge and discharge electric current can configure charge pump, input terminal and phase frequency detector (101)
Output end connection, output end connect with the input terminal of loop filter (103), and working condition is by digital processing unit (116)
First output control, so as to using digital processing unit (116) loop bandwidth of phaselocked loop is adjusted；
Multichannel voltage controlled oscillator (104) generates the oscillator signal of required 5~10GHz and 1.5~3GHz, and frequency of oscillation is by number
The output voltage of signal A, B, P and loop filter (103) codetermines, and A is used for the selection of voltage controlled oscillator, and B is for son frequency
The selection of band, P are somebody's turn to do to contain the setting of the preset signal of the mixed signal voltage controlled oscillator of frequency preset module when A chooses
When mixed signal voltage controlled oscillator is worked, preset module is total to according to the configuration of P with the output voltage for carrying out loop filter
It is applied to voltage controlled oscillator core in the heart with control voltage is generated, to the frequency of oscillation needed for generation, wherein A, B and P is respectively
Second, third of digital processing unit (116) is exported with the 4th；
Multichannel voltage controlled oscillator (104) contains three mutually independent voltage controlled oscillators, wherein the first voltage controlled oscillator covering 5
~10GHz frequency ranges, the second voltage controlled oscillator cover 1.5~3GHz frequency ranges, and third voltage controlled oscillator has frequency pre-
Set function, can realize quick lock in, shorten locking time, by digital processing unit (116) choose some voltage controlled oscillator into
Row work constitutes phaselocked loop major loop；
The input terminal of first multiple selector (105) is connect with the output end of multichannel voltage controlled oscillator (104), output end respectively with
Except two pre-dividers (106), Pyatyi remove the input terminal connection of two divided-frequency link (109) and major loop output buffer (108),
Working condition is controlled by the 5th output of digital processing unit (116), and the first multiple selector (105) is by being directed to different operating frequency range
Designed buffer the parallel combined is constituted, each buffer is controlled by the 5th output of digital processing unit (116), can be independent
It opens or closes, the buffer does not consume power consumption after closing.
2. multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators according to claim 1, which is characterized in that frequency discrimination
One input terminal of phase discriminator (101) and external reference signal FrefConnection, another input terminal and programmable multi-modulus frequency divider
(107) output signal FdivConnection, phase frequency detector (101) generate phase according to the difference on the frequency and phase difference of two input signals
The pulse voltage signal answered, with this come drive charge pump to loop filter (103) carry out charge and discharge.
3. the multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators stated according to claim 1, which is characterized in that programmable
The input terminal of multi-modulus frequency divider (107) is connect with the output end except two pre-dividers (106), output end and phase frequency detector
(101) input terminal connection may be programmed sixth output of the working condition by digital processing unit (116) of multi-modulus frequency divider (107)
Control.
4. multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators according to claim 3, which is characterized in that Pyatyi
Except two divided-frequency link (109) is used for generating the i/q signal of 0.1~5GHz, and two-way is divided to be respectively outputted to Receiver And Transmitter,
The Pyatyi removes the input terminal and the first multiple selector (105), external signal input buffer (114) of two divided-frequency link (109)
Output end connection, output end respectively with the output end of the second multiple selector (110) and third multiple selector (112) company
It connects, Pyatyi removes seventh control that exports of the working condition by digital processing unit (116) of two divided-frequency link (109).
5. multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators according to claim 4, which is characterized in that Pyatyi
Except two divided-frequency link (109) by 5 except two-divider cascade is constituted, per level-one except two-divider is all made of current mode logic,
The output signal that I/Q forms can be generated is controlled preceding N by 5 position digital signals1(1≤N1≤ 5) grade removes the unlatching of two-divider, with
Realize minimum 2, highest of removing except 32 frequency dividing exports.
6. multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators according to claim 5, which is characterized in that second
The buffer structure that multiple selector (110) and third multiple selector (112) are directed to by 5 designed by different operating frequency range
At this 5 buffers are connected to Pyatyi except every level-one of two divided-frequency link (109) removes the output end of two-divider, respectively by 5
Position digital signal controls the wherein opening of some buffer and shutdown, when Pyatyi removes the preceding N of two divided-frequency link (109)1(1≤N1≤
5) when grade is opened except two-divider, it is meant that frequency synthesizer needs to choose N1Grade is defeated except the divided down version progress of two-divider
Go out, thus the buffer that two-divider is connected is removed with this grade in the second multiple selector (110) or third multiple selector (112)
It will open, and other buffers are by Close All, to realize the selection of required frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410287623.1A CN104079315B (en) | 2014-06-24 | 2014-06-24 | Multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410287623.1A CN104079315B (en) | 2014-06-24 | 2014-06-24 | Multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104079315A CN104079315A (en) | 2014-10-01 |
| CN104079315B true CN104079315B (en) | 2018-09-04 |
Family
ID=51600384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410287623.1A Active CN104079315B (en) | 2014-06-24 | 2014-06-24 | Multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104079315B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9941892B2 (en) | 2014-06-24 | 2018-04-10 | Institute Of Semiconductors, Chinese Academy Of Sciences | Multi-standard performance reconfigurable I/Q orthogonal carrier generator |
| CN106656169B (en) * | 2015-11-03 | 2023-11-24 | 张伟林 | High-resistance digital phase discriminator with full-automatic locking working state |
| CN107947791B (en) * | 2017-12-21 | 2021-04-09 | 北京遥感设备研究所 | Rapid frequency switching micro system based on integrated phase-locked loop chip |
| CN109756225A (en) * | 2018-12-27 | 2019-05-14 | 复旦大学 | A kind of frequency synthesizer applied to multi-mode millimetre-wave attenuator |
| CN117254805B (en) * | 2023-11-20 | 2024-05-28 | 深圳市华普微电子股份有限公司 | SUB-1G full-frequency coverage frequency integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101741379A (en) * | 2009-12-09 | 2010-06-16 | 中国科学院半导体研究所 | Frequency complex for fast locking phaselocked loop |
| CN102122955A (en) * | 2010-12-07 | 2011-07-13 | 中国科学院半导体研究所 | Multistandard I/Q (In-Phase/Quadrature-Phase) carrier generating device based on fractional frequency-dividing frequency synthesizer |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7812679B2 (en) * | 2005-11-29 | 2010-10-12 | Motorola, Inc. | Multi-band frequency generation method and apparatus |
| TWI329423B (en) * | 2007-01-19 | 2010-08-21 | Faraday Tech Corp | Wide-locking range phase locked loop using adaptive post division technique |
| CN101814916B (en) * | 2010-01-11 | 2012-02-08 | 清华大学 | Phase-locked loop |
| KR101199780B1 (en) * | 2010-06-11 | 2012-11-12 | (주)에프씨아이 | Apparatus and method for frequency calibration in frequency synthesizer |
| CN103501175B (en) * | 2013-10-24 | 2016-02-10 | 清华大学 | A kind of millimeter wave phase-locked loop |
-
2014
- 2014-06-24 CN CN201410287623.1A patent/CN104079315B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101741379A (en) * | 2009-12-09 | 2010-06-16 | 中国科学院半导体研究所 | Frequency complex for fast locking phaselocked loop |
| CN102122955A (en) * | 2010-12-07 | 2011-07-13 | 中国科学院半导体研究所 | Multistandard I/Q (In-Phase/Quadrature-Phase) carrier generating device based on fractional frequency-dividing frequency synthesizer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104079315A (en) | 2014-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104079315B (en) | Multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators | |
| CN106067814B (en) | A kind of high-precision broadband multi-phase clock generator of low noise | |
| US8081034B2 (en) | Frequency synthesizer for integrated circuit radios | |
| US20040075506A1 (en) | Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications | |
| CN102201819B (en) | Frequency synthesis source applied by DDS short-wave transmitter based on CPLD design | |
| Deng et al. | A 5-GHz CMOS frequency synthesizer with an injection-locked frequency divider and differential switched capacitors | |
| CN101807914B (en) | Frequency self-correction phase lock loop adopting bonding wire as electric inductance of oscillator | |
| CN102868397A (en) | Self-correcting frequency synthesizer capable of optimizing properties of voltage-controlled oscillator and optimizing method of self-correcting frequency synthesizer | |
| CN102684685B (en) | Phase locked loop and method thereof | |
| CN103762979B (en) | Broadband frequency source for LTE channel simulator | |
| CN108712169A (en) | Low-power consumption phase-locked loop frequency synthesizer | |
| CN106341141A (en) | SDR-based agile multi-mode multipath transmit-receive device | |
| CN107623521A (en) | A kind of pll clock generator | |
| CN103178840B (en) | A kind of phase-locked loop circuit and its method of work | |
| CN101505169A (en) | Frequency synthesizer and frequency synthesis method thereof | |
| WO2004082160A1 (en) | Mutti-band frequency synthesizer | |
| CN104242930B (en) | A kind of frequency synthesizer applied to wireless transceiver system | |
| CN103166634B (en) | The method of adjustment and device of inductance capacitance parallel resonance chamber resonant frequency | |
| CN101483435A (en) | Dual circuit frequency synthesizer and tuning method thereof | |
| Lin et al. | Spur minimization techniques for ultra-low-power injection-locked transmitters | |
| US7872535B2 (en) | Phase locked loop with capacitive loop filter | |
| CN110289858A (en) | A kind of thin stepping frequency agility collaboration system in broadband | |
| US9941892B2 (en) | Multi-standard performance reconfigurable I/Q orthogonal carrier generator | |
| CN205754277U (en) | A kind of wideband voltage controlled oscillator | |
| CN110277991A (en) | A kind of wideband voltage controlled oscillator for supporting low gain to change |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |