CN102201819B - Frequency synthesis source applied by DDS short-wave transmitter based on CPLD design - Google Patents
Frequency synthesis source applied by DDS short-wave transmitter based on CPLD design Download PDFInfo
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Abstract
The invention relates to a frequency synthesis source applied by a DDS short-wave transmitter based on a CPLD design. The frequency synthesis source mainly comprises a direct digital synthesis circuit, a high-speed DAC transformation circuit, a tracking filter circuit and a gain control circuit, a controller and a phase locked crystal oscillator. According to the invention, the high-speed DAC transformation circuit converts frequency data output by direct digital synthesis circuit to a sine frequency signal; and the tracking filter circuit filters components of stray and harmonic wave in the high-speed DAC transformation circuit, and the gain control circuit enables the output of the direct digital synthesis circuit to be stable in amplitude within a frequency range. In addition, the controller comprises a microprocessor and a microcomputer, wherein the microprocessor is connected with the microcomputer through an interface circuit of the microcomputer, and frequency arrangement and transition of working mode are realized by an upper computer. The phase locked crystal oscillator generates a clock source signal with ultrahigh frequency and high stability, and the clock source signal is used as a clock signal of the frequency synthesis source. The frequency synthesis source applied by a DDS short-wave transmitter based on a CPLD design provided in the invention has advantages of high frequency accuracy and high distinguishability, short switching time of frequency signals, constant output amplitude, and simple and high-reliable circuit.
Description
Technical field
The present invention relates to the frequency synthesizer technical field, particularly a kind of short-wave band transmitter based on complex programmable device (CPLD) employing direct digital frequency synthesis technology is used the frequency synthesized signal source.
Background technology
At present, in the shortwave transmitting set, need Frequency Synthesizes Source to produce the short frequency pumping signal of required 1.5MHz～30MHz, its characteristic is directly connected to the performance index of shortwave transmitting set.Now, along with a large amount of uses of short wave communication equipment, channel is more and more crowded, disturbs increasingly, causes the continuous deterioration of electromagnetic environment, and we require the frequency synthesis source noise lower, spuious less.In addition, the development of the short wave communication new technology such as frequency hopping is also had higher requirement to performance index such as the scope of frequency scanning and switch speeds thereof.We wish the prompt change of the output frequency of synthesized source, and band limits is as far as possible wide.
Adopt the frequency of phase locking combiner circuit, can be subject to the restriction of frequency interval and frequency switching time, be difficult to meet frequency hopping communications and become and the requirement of switching at a high speed output frequency is prompt; Adopt Direct Digital Frequency Synthesizers, have the fast characteristics of frequency switch speed, can reach tens of nanosecond orders, but special-purpose DDS chip is because its internal structure is fixed, and generally adopt serial port setting, use in some cases inconvenient.
At first Direct Digital Frequency Synthesizers samples to the waveform that needs produce, and, with depositing the sinusoidal waveform memory after the sampled value digitlization in, then tables look-up data reading by phase accumulator again, then through the high-speed DAC transducer, converts the sinusoidal analog quantity of ladder to.Special-purpose DDS integrated chip is integrated in chip internal with the high-speed DAC transducer, and the DDS frequency synthesizer circuit of the Programmable Device Designs such as employing FPGA needs specialized high-speed DAC converter chip, has increased complexity and the cost of system.
The DAC transducer is output as the sinusoidal analog quantity of ladder, needs the output of filter smoothing DAC transducer, with the unnecessary spuious and harmonic signal of filtering.In typical case's application of general special-purpose DDS integrated chip, the filter of recommending is wideband low pass or broadband band-pass filter.The upper frequency limit of wideband low pass filter depends on the upper limit of DDS output frequency, if the bandwidth of band pass filter has surpassed the octave of output frequency, they to the spuious and harmonic signal of high-speed DAC transducer output basically incapability be power, especially when output frequency is higher sampled point seldom, filtering this moment is special can understand non-constant.If proportion is followed the tracks of the arrowband frequency-selective filtering, because it has very high Q value, resonance point is positioned at center frequency points all the time, can fundamentally solve the bad problem of wideband low pass filter filtering performance.Fig. 4 has provided respectively broadband belt pass filter and the characteristic of following the tracks of the arrowband frequency-selective filtering, and obviously, the characteristic of following the tracks of the arrowband frequency-selective filtering is much better than the former.
Summary of the invention
Technical problem to be solved by this invention is: provide a kind of DDS short-wave transmitter Frequency Synthesizes Source of the CPLD of employing design, the problem that exists to solve above-mentioned prior art.
The present invention solves its technical problem and adopts following technical scheme:
DDS short-wave transmitter Frequency Synthesizes Source provided by the invention, it is a kind of DDS short-wave transmitter Frequency Synthesizes Source of the CPLD of employing design, this Frequency Synthesizes Source mainly is comprised of direct digital synthesis circuit, high-speed DAC translation circuit, tracking filter and gain control circuit, controller and phase-locked crystal oscillator source, and wherein: the high-speed DAC translation circuit becomes the sinusoidal frequency signal with the frequency data Bian Change of direct digital synthesis circuit output; Spuious and harmonic component in tracking filter and gain control circuit filtering high-speed DAC Bian Change circuit, gain control circuit makes Frequency Synthesizes Source keep the output of amplitude stabilization in frequency range; Controller comprises microprocessor and microcomputer, by microprocessor, realizes the setting of frequency and the operation of working method, and perhaps microprocessor passes through the microcomputer interface circuit connected with computer, and realizes setting and the working method De Zhuan Change of frequency by host computer; Phase-locked crystal oscillator source produces the high steady clock source signals of hyperfrequency, as the clock signal of this Frequency Synthesizes Source.
Described Direct Digital Frequency Synthesizers is comprised of the data register that connects successively with the signal of telecommunication, phase accumulator and sinusoidal waveform question blank, wherein: data register produces the frequency control word of parallel or serial, by inquiry sinusoidal waveform question blank, obtain corresponding frequency control data, this frequency control data walks abreast and inputs to phase accumulator by data register.
Described phase accumulator, its figure place is chosen flexibly according to the desired resolution of Direct Digital Frequency Synthesizers.
Parallel or the serial of the frequency control word of controller output input to data register, the parallel phase accumulator that inputs to of the frequency control data of data register storage,, by inquiry sinusoidal waveform question blank, obtain corresponding ladder sine wave shape.
Described high-speed DAC translation circuit is comprised of the register that connects successively with the signal of telecommunication and position diverter switch, R-2R resistor network and buffer amplifier.
Described tracking filter and gain control circuit are mainly cut Change tracking filter amplifier and gain control circuit, output wave band electrical analogue switch, broadband buffer amplifier and amplitude by the input wave band electrical analogue switch, the subrane that are connected successively with the signal of telecommunication and are picked up slowdown monitoring circuit and form.
Described tracking filter and gain control circuit, it adopts subrane Qie Change circuit that the frequency range Qie Change of high-speed DAC Bian Change circuit output is become four wave bands, every wave band is first through band filter filtering, amplify through following the tracks of selective frequency amplifier circuit again, spuious and Resonance Wave Composition in sinusoidal ladder frequency signal is eliminated, then utilized gain control circuit that the interior output amplitude of frequency range of output is stablized.
Described phase-locked crystal oscillator source is comprised of variable frequency divider, external loop filter and the ultraharmonics crystal oscillator of the phase discriminator that connects successively with the signal of telecommunication, CPLD design.
The 10MHz temperature compensating crystal oscillator is adopted in described phase-locked crystal oscillator source, by phased lock loop, locks the ultraharmonics crystal oscillator.
Described 10MHz temperature compensating crystal oscillator can be accepted the Synchronization Control of the high steady 10MHz signal of outer input, makes oneself the output of locking ultraharmonics crystal oscillator reach very high frequency stability.
Above-mentioned DDS short-wave transmitter Frequency Synthesizes Source provided by the invention, it uses in the shortwave transmitting set of the short frequency pumping signal that works in 1.5MHz～30MHz.
The present invention compared with prior art has advantages of following main:
1. adopt the Direct Digital frequency synthesizer circuit of CPLD design, taken into account frequency switch speed that the Direct Digital Frequency Synthesizers special integrated chip has reach soon the complex programmable device flexibly, control dual characteristics easily.
2., based on the high-speed DAC circuit of CPLD, saved special-purpose DAC integrated chip, memory cell is selected flexibly, and is low in energy consumption, fast response time, and greatly reduce the complexity of cost and circuit.
3. designed tracking filter selective frequency amplifier circuit, accomplish that really each Frequency point is in best resonance condition, eliminates significantly the spuious and Resonance Wave Composition in sinusoidal ladder frequency signal, greatly improved the spectral purity of output frequency signal.
4. designed gain control amplifying circuit has improved the amplitude-frequency characteristic of output signal greatly, has reduced the uneven degree in reference frequency output.
5. the 10MHz temperature compensating crystal oscillator is selected in phase-locked crystal oscillator source, by phased lock loop, locks the ultraharmonics crystal oscillator.But the high steady 10MHz clock signal of outer input simultaneously is Synchronization Control 10MHz temperature compensating crystal oscillator also, can make oneself the output of locking ultraharmonics crystal oscillator reach very high frequency stability.
6. designed controller and microcomputer interface circuit, be easy to realize the setting of frequency and the conversion of working method, and function upgrading is convenient.
7. work in short-wave transmitter 1.5MHz～30MHz frequency range Inner, output has to hang down makes an uproar mutually, reached-90dBc/Hz(@10kHz skew), more than having improved 20dB than the same frequency range DDS frequency synthesizer that does not adopt the narrow-band tracking selective frequency filter circuit, be highly suitable for the carrier source as the short-wave band transmitter.
8. adopt the ultraharmonics crystal oscillator of high-performance compensation crystal oscillator locking, when frequency is 140MHz, survey noise level to reach-120dBc/Hz(@lkHz skew), it is supplied with the DDS chip as the reference frequency.
In a word, working stability of the present invention is reliable and low in energy consumption, and resolution is high, has realized that the victory of output frequency becomes and switching at a high speed, has particularly greatly reduced the spuious and harmonic component of output.
Description of drawings
Fig. 1 is structured flowchart of the present invention.
Fig. 2 is the circuit structure diagram of high-speed DAC conversion of the present invention.
Fig. 3 is the fundamental diagram of mat woven of fine bamboo strips triband of the present invention.
Fig. 4 is the characteristic comparison diagram of narrow band tracking filter of the present invention and broadband band-pass filter.
Fig. 5 is concrete structure block diagram of the present invention.
Embodiment
The invention will be further described below in conjunction with embodiment and accompanying drawing.
The DDS short-wave transmitter Frequency Synthesizes Source of employing provided by the invention CPLD design, its structure be as shown in Figure 5: comprise direct digital synthesis circuit, high-speed DAC translation circuit, tracking filter and gain control circuit, phase-locked crystal oscillator source, controller.Wherein: in Fig. 5, empty frame (1) is that it is comprised of the data register that connects successively with the signal of telecommunication, phase accumulator and sinusoidal waveform question blank by the Direct Digital Frequency Synthesizers (DDS) of complex programmable designs.Empty frame (2) is the high-speed DAC translation circuit by the complex programmable designs, and with reference to figure 2, it is comprised of the register that connects successively with the signal of telecommunication and position diverter switch, R-2R resistor network and buffer amplifier.Empty frame (3) is tracking filter and gain control circuit, with reference to figure 3, it by the input wave band electrical analogue switch that connects successively with the signal of telecommunication, subrane tracking filter amplifier and gain control, output wave band electrical analogue switch, broadband buffer amplifier and amplitude are picked up survey etc. forms.Empty frame (4) is phase-locked crystal oscillator source, and it is comprised of variable frequency divider, external loop filter and the ultraharmonics crystal oscillator of the phase discriminator that connects successively with the signal of telecommunication, CPLD design.Empty frame (5) is controller, comprises microprocessor and microcomputer, and the interface circuit of microprocessor comprises keyboard, demonstration, D/A1 and D/A2, A/D, serial port circuit etc.; Microcomputer can be realized operation to microprocessor by serial port circuit or USB.
But described direct digital synthesis circuit is designed by complexity coder spare CPLD.Referring to Fig. 1 and Fig. 5, it comprises the parts such as data register, phase accumulator, sinusoidal waveform question blank.Wherein the data register storing frequencies is controlled data (frequency control word), has the serial/parallel data input function, and serial input comes self-controller or microcomputer, and parallel data, from CPLD, can realize fast frequency-hopped function.The parallel phase accumulator that inputs to of the frequency control data of data register, can be chosen according to the desired resolution of frequency synthesizer flexibly by the figure place of the phase accumulator of CPLD design.The high m parallel-by-bit of phase accumulator output sequence inputs to the sinusoidal waveform question blank by CPLD design, and the memory capacity of sinusoidal waveform question blank has considered DDS precision, error and taken the factor such as resource, generally selects 256 or 512 memory cell.Wherein parallel input phase accumulator circuit how many positions that need to walk abreast, determined by clock frequency and resolution.
The structure of described phase accumulator circuit is as shown in add28 in Fig. 2.Because the operating frequency of DDS depends on selected CPLD,, if from cost performance, consider to select general CPLD, in order to guarantee the reliability of work, CPLD is operated in below 200MHz,
If,, be minimum resolution, can calculate resolution and be: Hz.
The structure of described sinusoidal waveform memory circuitry is as shown in Sin256 in Fig. 3, and obviously memory cell is larger, and sampled point resolution more at most is higher.But this conclusion is only effective when lower frequency, and when frequency was very high, most of sample values were rejected.So compromise selection 256 byte memory unit, every byte eight-digit binary number, totally eight bit address line eight bit data lines.The high eight-bit parallel join of sinusoidal waveform memory and parallel input phase accumulator, other positions are rejected.
Above-mentioned CPLD can be the CPLD of the MAX II series of ALTERA company, can be also the CPLD of XILINX or other company.
As shown in Figures 2 and 3, it has provided the structure by one 8 high-speed DAC Bian Change circuit of CPLD design to described high-speed DAC translation circuit.DAC256 in figure is fast data buffer register and the high speed Wei Qie Change switch of CPLD design, and their operating frequencies and selected CPLD operating frequency are suitable, can meet the requirement of short-wave transmitter Frequency Synthesizes Source to the DAC change-over circuit fully.External high precision reference voltage source and low error R-2R resistor network are subjected to the control of Wei Qie Change switch, and its output output after transporting at a high speed the amplification of grate amplifier buffer becomes sinusoidal ladder frequency signal output with the frequency data Bian Change of sinusoidal waveform question blank.
Resistance value in the R-2R resistor network is less, and response speed is higher, but just higher to the requirement of reference voltage source.The access of R-2R resistor network is subjected to the control of high speed Wei Qie Change switch, and its output is exported through transporting at a high speed after the grate amplifier buffer amplifies, and the frequency data Bian Change of sinusoidal waveform question blank is become sinusoidal ladder frequency signal output.Obviously remove sinusoidal fundamental frequency signal place in output, also comprised many spuious and harmonic components, need by the filter circuit filtering.
Tracking filter of the present invention and gain control circuit, by input subrane diverter switch, band broadband filter, follow the tracks of frequency-selecting, control amplifying circuit etc. with gain and form.Tracking filter and the gain control circuit of mat woven of fine bamboo strips triband have been provided in Fig. 3, complete the electric circuit constitute is as shown in Figure 5: the frequency range Qie Change of 1.5MHz～30MHz is become four wave bands, the wave band commutation circuit adopts high-speed analog switch, wherein the frequency range of the mat woven of fine bamboo strips one wave band is 1.5MHz～8MHz, because its frequency is lower, sampled point is more, therefore elliptic function filter can obtain desirable output waveform.The frequency range Fen Do of the mat woven of fine bamboo strips two～four wave bands is 8MHz～12MHz, and 12MHz～19MHz and 19MHz～30MHz, the topped coefficient of its frequency are less than 1.6, therefore easily adopt voltage-controlled tracking filter circuit.
Described gain control circuit is with reference to figure 3 and Fig. 5, and the DDS and high-speed DAC change Change circuit and the amplifying circuit etc. that are designed by CPLD all have certain amplitude-frequency characteristic, produce distortion.Gain control circuit is according to the amplitude-frequency characteristic of system, amplitude detection circuit (detection and ADC change-over circuit) by frequency control word and signal output part, DAC by controller provides gain-controlled voltage, effectively compensation amplitude-frequency characteristic error, stablize the interior output amplitude of frequency range of 1.5MHz～30MHz.
Described tracking filter and gain control circuit, its course of work is: first with two～four wave bands of high-speed DAC Bian Change circuit output respectively through broadband buffer amplifier filtering, then through tracking selective frequency amplifier circuit separately, amplify.Follow the tracks of the DAC output that voltage-controlled tuning voltage is taken from controller, its output voltage size is determined by frequency control word, and the variable capacitance diode in output voltage control loop makes the tracking selective frequency amplifier circuit be in the optimal tuning state.After such processing, can effectively eliminate the spuious and Resonance Wave Composition in sinusoidal ladder frequency signal.Gain control circuit, according to the amplitude-frequency characteristic of system, provides gain-controlled voltage by frequency control word by another DAC, effectively compensates the amplitude-frequency characteristic error, and the interior output amplitude of reference frequency output of 1.5MHz～30MHz is stablized.
Described tracking filter circuit is actually a controlled frequency selective amplifier of gain, and the amplifying device of selecting is dual gate FET 3SK223, also can adopt similar model, and the very convenient mat woven of fine bamboo strips two grids amplitude of carrying out of utilizing is controlled.Described broadband buffer amplifier is selected AD603, also can adopt similar model, also the very convenient control that gains.
described phase-locked crystal oscillator source, can select the 10MHz temperature compensating crystal oscillator, referring to Fig. 5, by external phase discriminator, the variable frequency divider of CPLD design, the phase-locked loop locking ultraharmonics crystal oscillator that external loop filter and ultraharmonics crystal oscillator form, its locking ultraharmonics crystal oscillator method is: by by phase discriminator, variable frequency divider, the phased lock loop that loop filter and ultraharmonics crystal oscillator form, high steady 10MHz signal by temperature compensating crystal oscillator output, as reference source locking ultraharmonics crystal oscillator, can make 10MHz crystal oscillator and ultraharmonics crystal oscillator characteristic complementary.The 10MHz crystal oscillator also can be subjected to the Synchronization Control of the high steady 10MHz clock signal of outer input simultaneously, and oneself can reach very high frequency stability at the output of locking ultraharmonics crystal oscillator, as master clock signal of the present invention.
Described phase-locked loop can adopt phase-locked chip 74LVC4046, also can adopt above-mentioned CPLD design, but prescaler completed by programming device, ultraharmonics crystal oscillator and buffer circuit adopt gate circuit 74LVC04.
Described controller be mainly used to configure by the frequency control word in the data register of CPLD design and working method thereof, spectrum conversion control, voltage-controlled narrow-band tracking is tuning, gain-controlled voltage and output amplitude detection circuit etc.By revising the frequency control word of the data register in CPLD, system can obtain the synthetic output of 1.5MHz～30MHz frequency range Inner optional frequency.This controller is AT91RM9200 or other single-chip microcomputer of atmel corp, also can select the ARM single-chip microcomputer.
Described interface circuit, referring to Fig. 5, mainly contains: DAC, output amplitude detection and serial port circuit etc. are controlled in keyboard input, liquid crystal display, wave band control, the voltage-controlled DAC of tracking filter, gain.Wherein the keyboard input arranges operating frequency and mode and provides demonstration with liquid crystal display; The voltage-controlled DAC of tracking filter provides corresponding voltage-controlled voltage according to frequency control word, makes the tracking filter circuit be in all the time the optimal tuning state; Gain control DAC and output amplitude are picked up slowdown monitoring circuit can control the output voltage of DAC simultaneously according to frequency control word and output amplitude size by ride gain, make output high-frequency signal maintenance amplitude-Ding in whole reference frequency output.
Described microcomputer, it connects controller (Fig. 1 and Fig. 5) by interface circuit, is realized setting and the working method De Zhuan Change of frequency by the upper computer software interface.
Above-described embodiment provided by the invention, be based on Direct Digital frequency synthesis (DDS) technology of complex programmable device (CPLD), the Direct Digital frequency synthesizer circuit that it is designed, having taken into account Direct Digital Frequency Synthesizers has the frequency switch speed and reaches soon the flexible characteristics of complex programmable device, particularly adopt the circuit of the high-speed DAC based on CPLD from wound, saved special-purpose DAC integrated chip and synthesized the waveform that is stored in memory.Referring to Fig. 4, adopt subrane to follow the tracks of frequency-selecting filter filtering, can effectively eliminate the spuious and Resonance Wave Composition in sinusoidal ladder frequency signal, make output waveform very perfect.In addition,, according to frequency control word and in conjunction with the fluctuation of output amplitude, by output gain, control voltage, can effectively compensate DDS amplitude-frequency characteristic error, make the output amplitude in its frequency range stable.
The above, be only preferred embodiment of the present invention, not structure of the present invention done any pro forma restriction.Any simple modification, equivalent variations that every foundation technical spirit of the present invention is done above embodiment, all still belong in the scope of technical scheme of the present invention, technical scheme of the present invention also can be used for the DDS synthesized source of other purposes of local oscillator information source of short-wave receiver.
Claims (8)
1. DDS short-wave transmitter Frequency Synthesizes Source, the DDS short-wave transmitter Frequency Synthesizes Source that it is characterized in that a kind of CPLD of employing design, this Frequency Synthesizes Source mainly is comprised of direct digital synthesis circuit, high-speed DAC translation circuit, tracking filter and gain control circuit, controller and phase-locked crystal oscillator source, and wherein: the high-speed DAC translation circuit becomes the sinusoidal frequency signal with the frequency data Bian Change of direct digital synthesis circuit output; Spuious and harmonic component in tracking filter and gain control circuit filtering high-speed DAC translation circuit, gain control circuit makes Frequency Synthesizes Source keep the output of amplitude stabilization in frequency range; Controller comprises microprocessor and microcomputer, by microprocessor, realizes the setting of frequency and the operation of working method, and perhaps microprocessor passes through the microcomputer interface circuit connected with computer, and realizes setting and the working method De Zhuan Change of frequency by host computer; Phase-locked crystal oscillator source produces the high steady clock source signals of hyperfrequency, as the clock signal of this Frequency Synthesizes Source; Described high-speed DAC translation circuit is comprised of the register that connects successively with the signal of telecommunication and position diverter switch, R-2R resistor network and buffer amplifier; Described tracking filter mainly is comprised of the input wave band electrical analogue switch that is connected successively with the signal of telecommunication, subrane switching tracking filter amplifier and gain control circuit, output wave band electrical analogue switch, broadband buffer amplifier and amplitude detection circuit with gain control circuit; Described DDS, CPLD, DAC are respectively that Direct Digital is synthetic, the english abbreviation of complex programmable device, steering D/A conversion.
2. DDS short-wave transmitter Frequency Synthesizes Source according to claim 1, it is characterized in that described Direct Digital Frequency Synthesizers is comprised of the data register that connects successively with the signal of telecommunication, phase accumulator and sinusoidal waveform question blank, wherein: data register produces the frequency control word of parallel or serial, by inquiry sinusoidal waveform question blank, obtain corresponding frequency control data, this frequency control data walks abreast and inputs to phase accumulator by data register.
3. DDS short-wave transmitter Frequency Synthesizes Source according to claim 2, is characterized in that described phase accumulator, and its figure place is chosen flexibly according to the desired resolution of Direct Digital Frequency Synthesizers.
4. DDS short-wave transmitter Frequency Synthesizes Source according to claim 1, it is characterized in that described tracking filter and gain control circuit, it adopts the subrane commutation circuit that the frequency range of high-speed DAC translation circuit output is switched to four wave bands, every wave band is first through band filter filtering, amplify through following the tracks of selective frequency amplifier circuit again, spuious and Resonance Wave Composition in sinusoidal ladder frequency signal is eliminated, then utilized gain control circuit that the interior output amplitude of frequency range of output is stablized.
5. DDS short-wave transmitter Frequency Synthesizes Source according to claim 1, is characterized in that described phase-locked crystal oscillator source is comprised of variable frequency divider, external loop filter and the ultraharmonics crystal oscillator of the phase discriminator that connects successively with the signal of telecommunication, CPLD design.
6. DDS short-wave transmitter Frequency Synthesizes Source according to claim 5, is characterized in that described phase-locked crystal oscillator source employing 10MHz temperature compensating crystal oscillator, by phased lock loop, locks the ultraharmonics crystal oscillator.
7. DDS short-wave transmitter Frequency Synthesizes Source according to claim 6, is characterized in that the high surely Synchronization Control of 10MHz signal of the outer input of described 10MHz temperature compensating crystal oscillator acceptance, makes the output of own locking ultraharmonics crystal oscillator reach frequency stability.
8. in claim 1 to 7, the described DDS short-wave transmitter of arbitrary claim, with the purposes of Frequency Synthesizes Source, is characterized in that described Frequency Synthesizes Source uses in the shortwave transmitting set of the short frequency pumping signal that works in 1.5MHz～30MHz.
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| CN102684807B (en) * | 2012-05-21 | 2018-05-04 | 中兴通讯股份有限公司 | A kind of clock recovery method and device |
| TWI552431B (en) | 2012-09-04 | 2016-10-01 | 深圳市華星光電技術有限公司 | Communication apparatus equipped with switchable antenna |
| CN103716063A (en) * | 2012-10-09 | 2014-04-09 | 林卓毅 | Communication apparatus capable of antenna switching |
| CN103346874B (en) * | 2013-06-20 | 2017-04-19 | 桂林电子科技大学 | Digital communication clock synchronization system based on DDS |
| CN103944540A (en) * | 2014-05-08 | 2014-07-23 | 成都雷电微力科技有限公司 | Triangular wave signal generator |
| CN104142430A (en) * | 2014-07-07 | 2014-11-12 | 盐城工学院 | RLC measuring instrument and measuring method |
| CN105515575A (en) * | 2015-12-05 | 2016-04-20 | 青岛盛嘉信息科技有限公司 | Sinusoidal signal frequency generator |
| CN108712167B (en) * | 2018-05-24 | 2021-11-23 | 南京熊猫电子股份有限公司 | Standard frequency distribution module with self-adaptive frequency selection characteristic |
| CN108599783A (en) * | 2018-05-24 | 2018-09-28 | 南京熊猫电子股份有限公司 | A kind of frequency distribution module that frequency is configurable |
| CN110176929A (en) * | 2019-06-20 | 2019-08-27 | 常州国光数据通信有限公司 | A kind of binary channels local oscillator source module receiving system simultaneously for shortwave two-way |
| CN110988760B (en) * | 2019-12-06 | 2024-05-28 | 天津大学 | Digital signal detection system of Mx cesium light pump magnetometer |
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