CN201063116Y - Low frequency signal source for arbitrary waveform - Google Patents
Low frequency signal source for arbitrary waveform Download PDFInfo
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- CN201063116Y CN201063116Y CNU2007201020879U CN200720102087U CN201063116Y CN 201063116 Y CN201063116 Y CN 201063116Y CN U2007201020879 U CNU2007201020879 U CN U2007201020879U CN 200720102087 U CN200720102087 U CN 200720102087U CN 201063116 Y CN201063116 Y CN 201063116Y
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Abstract
The utility model relates to an arbitrary waveform low-frequency signal source, which is modified based on the existing direct digital synthesis technology. The main modifying point lies in that a phase accumulator used in DDS established by a small scale integrated circuit is utilized. The phase accumulator used for the direct digital synthesis consists of a frequency-controlled letter flip-latch, a 12-bit address adder, a 12-bit address flip-latch, a waveform memorizer and a waveform digital flip-latch. The utility has the benefits that the utility model is characterized by low price and high speed and can provide arbitrary waveforms; a designing idea and a specific circuit of the utility model can be widely used for the design of FPGA and CPLD; besides, the utility model can provide cheap experimental instruments for electrical and electronic laboratories in universities.
Description
Technical field
The utility model relates to a kind of random waveform low frequency signal source, be a kind of random waveform low frequency signal source that the Direct Digital synthetic (DDS:Direct Digital Synthesis) of building with small scale integration is used phase accumulator that has, belong to instrument, field of instrumentation technology.
Background technology
The virtual signal source is under control of microcomputer, can export the virtual instrument of required random waveform signal after the process D/A conversion to by a series of data of calculating or storage obtains.
The main method that produces at present low frequency signal has two kinds of direct modeling method and Direct Digital methods.
The direct modeling method generally all is to produce original waveform by the free oscillation device, convert original waveform to other waveform through change-over circuit then, needed waveform will be through amplifying and the output of decay back, the waveform catalog that obvious this mode produces is limited, a kind of waveform of every increase, all will increase corresponding change-over circuit, it is very complicated that entire circuit becomes, and it almost is impossible the most important thing is to produce the needed complicated wave form arbitrarily of user.
The Direct Digital method is to adopt synthetic (the DDS:Direct Digital Synthesis) technology of Direct Digital to realize the method for signal, can produce needed complicated wave form arbitrarily, and phase accumulator is the core of DDS virtual signal source circuit.The DDS technology has that frequency inverted speed is fast, frequency resolution is high, be easy to outstanding features such as control.This technology development in recent years gets very fast, but its phase accumulator is integrated in chip internal, can't understand the implementation procedure of its physical circuit, and this is very big for user's application limitations, such as can't directly using in FPGA, the CPLD of widespread use at present.The phase accumulator of DDS chip AD9851 commonly used is like this.
The waveform of the Direct Digital synthetic technology output of using at present is limited, can only export square wave or sine wave such as DDS chip AD9851 commonly used.
Summary of the invention
Technical problem to be solved in the utility model provides a kind of random waveform low frequency signal source that the DDS that builds with small scale integration uses phase accumulator that has.
The technical scheme that its technical matters that solves the utility model adopts:
The utility model is to improve to form on the basis of existing Direct Digital synthetic technology, and its main improvement is to adopt the DDS phase accumulator of building with small scale integration.
Concrete technical scheme of the present utility model is as follows:
The utility model includes single chip machine controlling circuit, low frequency filtering and amplifying circuit; It is characterized in that it also includes signal source circuit; The input end of the output termination signal source circuit of single chip machine controlling circuit, the output termination low-pass filtering of signal source circuit and the input end of amplifying circuit, low pass filtered involves the signal output part of this signal source of output termination of amplifying circuit; Described signal source circuit is formed with phase accumulator, D/A converter, 8 ternary data buffers, reference clock circuit, channel to channel adapters by the Direct Digital of building with small scale integration is synthetic; The synthetic phase accumulator of using of described Direct Digital is by the frequency control word latch, 12 bit address totalizers, 12 bit address latchs, wave memorizer, the Wave data latch is formed, the input end of frequency control word latch connects the P0 mouth of the single-chip microcomputer in the single chip machine controlling circuit by data bus, the input end of the output termination 12 bit address totalizers of frequency control word latch, the input end of the output termination 12 bit address latchs of 12 bit address totalizers, one tunnel output of 12 bit address latchs connects the input end of 12 bit address totalizers, one road input end of its another road output welding wave storer, another road input end of wave memorizer connects the P0 mouth of the single-chip microcomputer in the single chip machine controlling circuit through 8 ternary data buffers, one tunnel output of wave memorizer connects the input end of 12 bit address totalizers, the input end of its another road output welding wave data latches, the input end of the output termination D/A converter of Wave data latch; The output termination low-pass filtering of D/A converter and the input end of the follower in the amplifying circuit; One road input end of reference clock circuit connects the output terminal of vibration, frequency division and timer conter circuit in the single chip machine controlling circuit, the output terminal of reference clock circuit connects the clock end of 12 bit address latchs, Wave data latch, D/A converter respectively, the sheet choosing end of the output terminal welding wave storer of reference clock circuit; The input end of channel to channel adapter connects the P0 mouth of the single-chip microcomputer in the single chip machine controlling circuit, and one tunnel output of channel to channel adapter connects the input end of reference clock circuit, and its another road output connects low pass filtered and involves the input end that 8 in the amplifying circuit selects 1 analogue selector.
The beneficial effects of the utility model are as follows:
(1) has low price, characteristics at a high speed, and random waveform can be provided.
(2) design philosophy of the present utility model and physical circuit can be widely used in FPGA and the CPLD design.
(3) can provide cheap experimental apparatus for university electrotechnical, electronic laboratory.
Description of drawings
Fig. 1 is a theory diagram of the present utility model.
Fig. 2 is the schematic diagram of single chip machine controlling circuit of the present utility model.
Fig. 3 is the schematic diagram of signal source circuit of the present utility model.
Fig. 4 involves the schematic diagram of amplifying circuit for low pass filtered of the present utility model.
Embodiment
By the embodiment shown in Fig. 1-4 as can be known, it includes single chip machine controlling circuit, low frequency filtering and amplifying circuit; It is characterized in that it also includes signal source circuit; The input end of the output termination signal source circuit of single chip machine controlling circuit, the output termination low-pass filtering of signal source circuit and the input end of amplifying circuit, low pass filtered involves the signal output part of this signal source of output termination of amplifying circuit; Described signal source circuit is formed with phase accumulator, D/A converter, 8 ternary data buffers, reference clock circuit, channel to channel adapters by the Direct Digital of building with small scale integration is synthetic; The synthetic phase accumulator of using of described Direct Digital is by the frequency control word latch, 12 bit address totalizers, 12 bit address latchs, wave memorizer, the Wave data latch is formed, the input end of frequency control word latch connects the P0 mouth of the single-chip microcomputer in the single chip machine controlling circuit by data bus, the input end of the output termination 12 bit address totalizers of frequency control word latch, the input end of the output termination 12 bit address latchs of 12 bit address totalizers, one tunnel output of 12 bit address latchs connects the input end of 12 bit address totalizers, one road input end of its another road output welding wave storer, another road input end of wave memorizer connects the P0 mouth of the single-chip microcomputer in the single chip machine controlling circuit through 8 ternary data buffers, one tunnel output of wave memorizer connects the input end of 12 bit address totalizers, the input end of its another road output welding wave data latches, the input end of the output termination D/A converter of Wave data latch; The output termination low-pass filtering of D/A converter and the input end of the follower in the amplifying circuit; One road input end of reference clock circuit connects the output terminal of vibration, frequency division and timer conter circuit in the single chip machine controlling circuit, the output terminal of reference clock circuit connects the clock end of 12 bit address latchs, Wave data latch, D/A converter respectively, the sheet choosing end of the output terminal welding wave storer of reference clock circuit; The input end of channel to channel adapter connects the P0 mouth of the single-chip microcomputer in the single chip machine controlling circuit, and one tunnel output of channel to channel adapter connects the input end of reference clock circuit, and its another road output connects low pass filtered and involves the input end that 8 in the amplifying circuit selects 1 analogue selector.
Described frequency control word latch is made up of integrated package U15, input end 3 pin of integrated package U15,4 pin, 7 pin, 8 pin, 13 pin, 14 pin, 17 pin, 18 pin connect the 39-32 pin of the single-chip microcomputer U1 in the single chip machine controlling circuit respectively, 11 pin of integrated package U15 connect 16 pin of the single-chip microcomputer U1 in the single chip machine controlling circuit, and 1 pin of integrated package U15 connects 27 pin of single-chip microcomputer U1.
Described 12 bit address totalizers are made up of integrated package U9-U11, input end 6 pin of integrated package U9,2 pin, 15 pin, 11 pin connect output terminal 2 pin, 5 pin, 6 pin, 9 pin of integrated package U15 respectively, carry end 9 pin of integrated package U9 connect 7 pin of integrated package U10, the 7 pin ground connection of integrated package U9; Input end 6 pin of integrated package U10,2 pin, 15 pin, 11 pin connect output terminal 12 pin, 15 pin, 16 pin, 19 pin of integrated package U15 respectively, and carry end 9 pin of integrated package U10 connect 7 pin of integrated package U11; 6 pin of integrated package U11,2 pin, 15 pin, 11 pin are ground connection respectively, and carry end 9 pin of integrated package U11 are empty pin.
Described 12 bit address latchs are made up of integrated package U12-U13; Input end 3 pin of integrated package U12,4 pin, 6 pin, 11 pin connect integrated package U9 output terminal 4 pin, 1 pin, 13 pin, 10 pin respectively, output terminal 4 pin, 1 pin that input end 13 pin of integrated package U12,14 pin meet integrated package U10 respectively; Output terminal 2 pin of integrated package U18,5 pin, 7 pin, 10 pin connect input end 5 pin, 13 pin, 14 pin, 12 pin of integrated package U9 respectively, input end 5 pin, 3 pin that output terminal 12 pin of integrated package U12,15 pin meet integrated package U10 respectively, 1 pin of integrated package U12 connects 4 pin of single-chip microcomputer U1; Output terminal 13 pin, 10 pin that input end 3 pin of integrated package U13,4 pin meet integrated package U10 respectively, input end 6 pin of integrated package U13,11 pin, 13 pin, 14 pin connect output terminal 4 pin, 1 pin, 13 pin, 10 pin of integrated package U11 respectively, input end 14 pin, 12 pin that output terminal 2 pin of integrated package U13,5 pin meet integrated package U10 respectively, output terminal 7 pin of integrated package U13,10 pin, 12 pin, 15 pin connect input end 5 pin, 3 pin, 14 pin, 12 pin of integrated package U11 respectively; 1 pin of integrated package U13 connects 4 pin of single-chip microcomputer U1.
Described wave memorizer is made up of integrated package U14 and peripheral cell thereof or a door U7C, two-way end 21 pin of integrated package U14, the 23-25 pin, the 2-3 pin connects output terminal 2 pin of integrated package U12 respectively, 5 pin, 7 pin, 10 pin, 12 pin, 15 pin, the two-way end 4-9 pin of integrated package U14 connects output terminal 2 pin of integrated package U13 respectively, 5 pin, 7 pin, 10 pin, 12 pin, 15 pin, two-way end 21 pin of integrated package U14, the 23-25 pin connects input end 5 pin of integrated package U9 respectively, 3 pin, 14 pin, 12 pin, the two-way end 2-5 pin of integrated package U14 connects input end 5 pin of integrated package U10 respectively, 3 pin, 14 pin, 12 pin, the two-way end 6-9 pin of integrated package U14 connects input end 5 pin of integrated package U11 respectively, 3 pin, 14 pin, 12 pin, 10 pin of integrated package U14,14 pin are ground connection respectively, 26 pin of integrated package U14,28 pin connect respectively+5V, or input end 1 pin of door U7C connects 16 pin of single-chip microcomputer U1, or input end 2 pin of door U7C connect output terminal 10 pin of the 3-8 code translator U2 in the single chip machine controlling circuit, or output terminal 3 pin of door U7C connect 27 pin of integrated package U14.
Described Wave data latch is made up of integrated package U18, and input end 3 pin of integrated package U18,4 pin, 7 pin, 8 pin, 13 pin, 14 pin, 17 pin, 18 pin connect output terminal 11-13 pin, the 15-19 pin of integrated package U14 respectively, the 1 pin ground connection of integrated package U18.
Described D/A converter is by integrated package U19 and peripheral cell resistance R 4-R6 thereof, capacitor C 6-C8, voltage stabilizing diode D1 forms, the input end 18-11 pin of integrated package U19 connects output terminal 2 pin of integrated package U18 respectively, 5 pin, 6 pin, 9 pin, 12 pin, 15 pin, 16 pin, 19 pin, 2 pin of integrated package U19,5 pin, 7 pin, 8 pin connect respectively+5V, 1 pin of integrated package U19,9 pin are ground connection respectively, capacitor C 6 is connected between 3 pin and ground of integrated package U19, resistance R 4 be connected on after voltage stabilizing diode D1 connects+9V and ground between, resistance R 5 be connected between the positive pole and ground of voltage stabilizing diode after R6 connects, capacitor C 7, in parallel after the C8 parallel connection with resistance R 6, the positive pole of capacitor C 8 connects 4 pin of integrated package U19, and output terminal 6 pin of integrated package U19 connect input end 12 pin that low pass filtered involves the follower U23D in the amplifying circuit.
Described 8 ternary data buffers are made up of integrated package U17, input end 2 pin of integrated package U17,4 pin, 6 pin, 8 pin, 11 pin, 13 pin, 15 pin, 17 pin connect the 39-32 pin of single-chip microcomputer U1 respectively, output terminal 18 pin of integrated package U17,16 pin, 14 pin, 12 pin, 9 pin, 7 pin, 5 pin, 3 pin connect 11-13 pin, the 15-19 pin of integrated package U14 respectively, and 1 pin of integrated package U17,19 pin connect output terminal 10 pin of the 3-8 code translator U4 in the single chip machine controlling circuit respectively.
Described channel to channel adapter is made up of integrated package U16, input end 3 pin of integrated package U16,4 pin, 7 pin, 8 pin, 13 pin, 14 pin, 17 pin, 18 pin connect the 39-32 pin of single-chip microcomputer U1 respectively, the low pass filtered that output terminal 12 pin of integrated package U16,9 pin, 6 pin connects respectively involves the input end 9-11 pin of 8 analog switch U25 in the amplifying circuit, and 1 pin of integrated package U16,11 pin connect 27 pin, 16 pin of single-chip microcomputer U1 respectively.
Described reference clock circuit is by frequency selector U21 and peripheral cell and door U20A-U20D, or door U7D, U22A, not gate U8D forms, the input end 11-9 pin of frequency selector U21 connects output terminal 19 pin of integrated package U16 respectively, 16 pin, 15 pin, input end 3 pin of frequency selector U21,4 pin connect output terminal 13 pin of the timer conter U4 in the single chip machine controlling circuit respectively, 17 pin, input end 1 pin of frequency selector U21,2 pin connect 5 pin of the integrated package U5A in the frequency dividing circuit in the single chip machine controlling circuit respectively, 5 pin of integrated package U5B, the 12-15 pin of frequency selector U21 connects+5V, the 7 pin ground connection of frequency selector U21; With input end 4 pin of door U20B, output terminal 5 pin that 5 pin meet frequency selector U21 respectively, with input end 9 pin of door U20C, output terminal 5 pin that 10 pin meet frequency selector U21 respectively, with output terminal 6 pin of door U20B; Or input end 4 pin, output terminal 5 pin that 5 pin meet frequency selector U21 respectively of door U7D; Connect output terminal 8 pin with door U20C respectively with input end 12 pin, 13 pin of door U20D, connect 22 pin of integrated package U14 with output terminal 11 pin of door U20D; With input end 1 pin, 2 pin of door U20A connect respectively the 3-8 code translator U2 in the single chip machine controlling circuit 10 pin, with output terminal 8 pin of door U20C, connect clock end 9 pin of integrated package U12, U13 respectively with output terminal 3 pin of door U20A; Connect sheet choosing end 20 pin of integrated package U14 with output terminal 3 pin of door U20A; Or input end 9 pin, 10 pin of door U22A connect respectively or output terminal 6 pin of door U7D, or output terminal 8 pin of door U22A connect clock end 11 pin of integrated package U18; Input end 5 pin of not gate U8D connect or the door U7D output terminal 6 pin, output terminal 6 pin of not gate U8D connect clock end 10 pin of integrated package U19.
In single chip machine controlling circuit shown in Figure 1, it is made up of single-chip microcomputer U1 and peripheral cell crystal Y1, resistance R 1, capacitor C 1-C3,3-8 code translator U2, parallel port U3 and peripheral cell thereof or door U7A, U7B, not gate U8A, interface J1, vibration, frequency division and timer conter circuit; Vibration, frequency division and timer conter circuit are made up of timer conter U4, oscillator, frequency dividing circuit.
Oscillator is made up of crystal Y2, not gate U8B, U8C, resistance R 2, R3, capacitor C 4, C5; Frequency dividing circuit is made up of integrated package U5A, U5B, U5C; Timer conter is made up of integrated package U4.Interface 11 is connected with host computer.
Involve in the amplifying circuit in low pass filtered shown in Figure 4, it by follower, low pass filtered involve attenuator circuit, amplifying circuit is formed; Follower is made up of integrated package U23D, resistance R 7, capacitor C 9; Low pass filtered involves attenuator circuit to be made up of 8 path analoging switch U25, resistance R 11-R17, filter capacitor C11-C17; Amplifying circuit is made up of operational amplifier U23A-U23C, variable resistor integrated package U24, not gate U8EA, U8FB, resistance R 8-R10, capacitor C 10, diode D2, interface J2, J3.
The principle of work and the design philosophy of present embodiment are as follows:
The signal source circuit of present embodiment is responsible for the data that are stored among the wave memorizer U14 are handled, and carries out the D/A conversion; Low pass filtered involves amplifying circuit to be responsible for the data after the D/A conversion are carried out low-pass filtering treatment, and regulates, and reduces the distortion of signal, and the precision of holding signal is smaller or equal to 5%; Single chip machine controlling circuit is responsible for whole flow process is controlled.
1, single chip machine controlling circuit (see figure 2):
That as shown in Figure 2, single-chip microcomputer adopts is AT89C51.Single-chip microcomputer is the control core of total system, and other each module work is being coordinated in its control.Present embodiment adopts the direct control mode based on the metadata cache technology.
The control of wave memorizer: when D/A converter U19 worked, the sample value of promptly reading among the wave memorizer U14 was delivered to D/A converter.As shown in Figure 3, when the CE of wave memorizer and OE signal were effective, wave memorizer was for reading effectively, when the rising edge of the frequency selector U21 in the reference clock circuit arrives, sample value among the readable wave memorizer U14 of going out arrives Wave data latch U18, prepares to carry out the D/A conversion.Calculate below and latch the address that 4K*8 wave memorizer U14 uses in this clock period at rising edge clock, to the typical delay time that data are stablized in 4K*8 wave memorizer U14 output since 12 bit address latch U12, U13.This time equal 12 bit address latch U12, U13 typical delay time+wave memorizer U14 (7C185) address effectively arrives the maximum time=4.5ns+20ns=24.5ns of valid data output, the time of the next rising edge clock of distance is 33.3ns-24.5ns=8.8ns.
By Fig. 2,3 as can be known, when D/A converter was worked, the sheet of U17 choosing end (1 pin, 19 pin) was 1, and U7C is output as 1 simultaneously, makes that the write signal of wave memorizer U14 is 1, and single-chip microcomputer can not be write wave memorizer; And when the frequency selector U21 in the reference clock circuit is output as arbitrary value among D5～D7, this moment, D/A converter was not worked, when sending decoded signal Y5, single-chip microcomputer chooses wave memorizer U14, and when the WR signal is effective (this moment, U7C was output as 0), the sheet choosing end of U17 is 0, and single-chip microcomputer can write sampled data among the wave memorizer U14 through U17.
The control of D/A converter: when D/A converter U19 pin CLK input 30M clock, clock high level and low level respectively are 16.65ns.TLC5602 (D/A converter U19) work schedule requirement, at locked rising edge clock poke word signal D0-D7, finish the D/A data-switching one time through behind about 25ns, DSR should be more than or equal to 16.5ns to the time of clock rising edge, and data hold time should be more than or equal to 12.5ns behind the rising edge clock.Because the time of the next rising edge clock of wave memorizer U14 data coverage is 8.8ns, therefore can not be directly latch digital signal D0-D7 with the rising edge of clock.The way that solves is with the rising edge of clock is first data D0-D7 to be latched among the Wave data latch U18, the 30M clock is added to the CLK pin of TLC5602 (D/A converter U19) after through 1 phase inverter paraphase, promptly adding 1 inverter delay and latch digital signal D0 after the time at the negative edge of 30M clock---D7 is to TLC5602, and each phase inverter typical delay time is 3.8ns.Wave data latch U18 adopts 74F377, and its typical delay time from CLK to Q is 3ns, DSR to time of clock upper edge more than or equal to 4.1ns, data hold time is more than or equal to 0.5ns behind the rising edge clock.3ns DSR behind the rising edge of clock is about 16ns apart from time of TLC5602 latch data signal.Adopting delay TLC5602 to latch way adjusted of time again makes it satisfy the sequential requirement.
2, signal source circuit (see figure 3):
Frequency control word K is deposited among the frequency control word latch U15 phase place that once increases as totalizer by single-chip microcomputer; The sampled data of the waveform one-period that will produce deposits among the wave memorizer U14.Under the control of reference clock, each clock period makes totalizer increase frequency control word K value, and the output of totalizer is read Wave data and is converted to the correspondent voltage signal through D/A as the address of reading wave memorizer U14.Because frequency control word K can only round numerical value, so signal source can not produce the signal of cline frequency.For continuously adjustable signal source, the user can select optional frequency, at this moment just may produce error, generally will guarantee frequency relative error within the specific limits.
In order to guarantee certain precision, K can not be too little.In order to solve this contradiction, the one-period of the periodic signal that present embodiment will be exported carries out sample quantization, gathers 256 sampling points altogether, deposits in the wave memorizer, and each sample value is deposited 16 times continuously, and 256 sample values are extended for 4096 sample values.
Phase accumulator wherein adopts 3 74F283 cascades to expand and forms (U9-U11).Say it is 12 quick totalizers capable of circulation from function.Each clock comes interim, and the determined phase increment K of value in the totalizer and frequency control word adds up once, and the result still is stored in the totalizer, prepares for adding up next time.After phase accumulator counting is full, but Automatic Cycle add up again, so output phase can keep continuous variation, this has just guaranteed the continuity of output waveform.Below analyze when the highest 30MHz clock (cycle is 33.3ns), phase accumulator is finished the sequential of additive operation.By the canonical parameter of SN74F283 as can be known, SN74F283 from data effectively to the typical delay time that the most significant digit totalizer produces carry be 5.3ns, from data effectively to the typical delay time of summation output be 6.6ns.Because a SN74F283 chip can only realize that 4 binary carry look aheads add entirely, to realize that so 12 totalizers will be made up of 3 SN74F283, adopt the cascaded carry method, i.e. 12 totalizers of 3 SN74F283 work in series realizations.Then 4 totalizers among the most significant digit SN74F283 need be waited for after preceding two SN74F283 produce carry and could work, and it finishes the summation operation required time is 5.3+5.3+6.6=17.2ns.12 bit address latch U12, U13 latch the address that 4K*8 wave memorizer U14 uses in this clock period with rising edge clock, the typical delay time is 4.5ns, totalizer begins to calculate then, the DSR of 12 bit address latchs to the clock rise time should be more than or equal to 5ns, three's sum is 26.7, less than 33.3ns.So totalizer can be finished the calculating of address+K in the 33.3ns of one-period.
Wherein wave memorizer U14 adopts 7C 185, is used to store the range value of the periodic function of out of phase.Because the output of phase accumulator is continuous linear change in time, can't directly utilize with the phase information of N bit expression, must convert phase information to amplitude information and be stored in the wave memorizer.
At first the one-period to the periodic signal that will export carries out sample quantization, gathers 4096 sampling points altogether, deposits in the wave memorizer.Phase differential between per two addresses is 360 °/4096.Adopting the switching rate of D/A converter is 30MHz, D/A converter is for signal that to export a frequency be 1MHz, 30 sample values of phase output weekly promptly will be exported a sample value every 4096/30=136.53 at interval from 4096 sample values of the one-period of output waveform.In the practical operation, can only round numbers 137, take out a sample value after, storage address increases by 137, takes out next sample value.The mould that utilizes 12 bit address of storer is 4096 these characteristics, and can read continuously that the address differs is each sample value of 137.In order to reduce frequency, the address that can reduce adjacent two sample values is spaced apart 136,135 ... etc.
By above analysis, frequency control word K can only round numerical value, so signal source can not produce the signal of cline frequency.For continuously adjustable signal source, the user can select optional frequency, at this moment just may produce error, generally will guarantee frequency relative error within the specific limits.The maximum absolute error of present embodiment is that fc/ (2*2N) (fc is a clock frequency), relative error are 1/ (2K).
3, low pass filtered involves the amplifying circuit (see figure 4):
As shown in Figure 4, after follower U23D amplified ± 25mv decays by 8 grades of attenuators to the input signal of ± 5V, select 1 analogue selector U25 to select corresponding signal with one 8, final unified decaying to ± 25mV is added to the input end that enlargement factor is fixed as 40 amplifier (being made of first order U23C and second level amplifier U23A).Follower U23D mainly is in order to improve input impedance and to reduce output impedance.First order U23C and second level U23A two-stage enlargement factor distribution principle are as follows: under the principle that guarantees high frequency band, improve the enlargement factor of the first order as far as possible, here first order enlargement factor is 8, second level enlargement factor is 5, do the signal to noise ratio (S/N ratio) that can improve amplifier like this, the second level is large signal amplifier simultaneously, and the large-signal bandwidth ratio small signal bandwidth of device is narrow, and the enlargement factor I is to reduce the requirement of second level amplifier amplifier bandwidth.
Claims (10)
1. random waveform low frequency signal source, it includes single chip machine controlling circuit, low frequency filtering and amplifying circuit; It is characterized in that it also includes signal source circuit; The input end of the output termination signal source circuit of single chip machine controlling circuit, the output termination low-pass filtering of signal source circuit and the input end of amplifying circuit, low pass filtered involves the signal output part of this signal source of output termination of amplifying circuit; Described signal source circuit is formed with phase accumulator, D/A converter, 8 ternary data buffers, reference clock circuit, channel to channel adapters by the Direct Digital of building with small scale integration is synthetic; The synthetic phase accumulator of using of described Direct Digital is by the frequency control word latch, 12 bit address totalizers, 12 bit address latchs, wave memorizer, the Wave data latch is formed, the input end of frequency control word latch connects the P0 mouth of the single-chip microcomputer in the single chip machine controlling circuit by data bus, the input end of the output termination 12 bit address totalizers of frequency control word latch, the input end of the output termination 12 bit address latchs of 12 bit address totalizers, one tunnel output of 12 bit address latchs connects the input end of 12 bit address totalizers, one road input end of its another road output welding wave storer, another road input end of wave memorizer connects the P0 mouth of the single-chip microcomputer in the single chip machine controlling circuit through 8 ternary data buffers, one tunnel output of wave memorizer connects the input end of 12 bit address totalizers, the input end of its another road output welding wave data latches, the input end of the output termination D/A converter of Wave data latch; The output termination low-pass filtering of D/A converter and the input end of the follower in the amplifying circuit; One road input end of reference clock circuit connects the output terminal of vibration, frequency division and timer conter circuit in the single chip machine controlling circuit, the output terminal of reference clock circuit connects the clock end of 12 bit address latchs, Wave data latch, D/A converter respectively, the sheet choosing end of the output terminal welding wave storer of reference clock circuit; The input end of channel to channel adapter connects the P0 mouth of the single-chip microcomputer in the single chip machine controlling circuit, and one tunnel output of channel to channel adapter connects the input end of reference clock circuit, and its another road output connects low pass filtered and involves the input end that 8 in the amplifying circuit selects 1 analogue selector.
2. random waveform low frequency signal source according to claim 1, it is characterized in that the frequency control word latch is made up of integrated package U15, input end 3 pin of integrated package U15,4 pin, 7 pin, 8 pin, 13 pin, 14 pin, 17 pin, 18 pin connect the 39-32 pin of the single-chip microcomputer U1 in the single chip machine controlling circuit respectively, 11 pin of integrated package U15 connect 16 pin of the single-chip microcomputer U1 in the single chip machine controlling circuit, and 1 pin of integrated package U15 connects 27 pin of single-chip microcomputer U1.
3. random waveform low frequency signal source according to claim 2, it is characterized in that described 12 bit address totalizers are made up of integrated package U9-U11, input end 6 pin of integrated package U9,2 pin, 15 pin, 11 pin connect output terminal 2 pin, 5 pin, 6 pin, 9 pin of integrated package U15 respectively, carry end 9 pin of integrated package U9 connect 7 pin of integrated package U10, the 7 pin ground connection of integrated package U9; Input end 6 pin of integrated package U10,2 pin, 15 pin, 11 pin connect output terminal 12 pin, 15 pin, 16 pin, 19 pin of integrated package U15 respectively, and carry end 9 pin of integrated package U10 connect 7 pin of integrated package U11; 6 pin of integrated package U11,2 pin, 15 pin, 11 pin are ground connection respectively, and carry end 9 pin of integrated package U11 are empty pin.
4. random waveform low frequency signal source according to claim 3 is characterized in that described 12 bit address latchs are made up of integrated package U12-U13; Input end 3 pin of integrated package U12,4 pin, 6 pin, 11 pin connect integrated package U9 output terminal 4 pin, 1 pin, 13 pin, 10 pin respectively, output terminal 4 pin, 1 pin that input end 13 pin of integrated package U12,14 pin meet integrated package U10 respectively; Output terminal 2 pin of integrated package U18,5 pin, 7 pin, 10 pin connect input end 5 pin, 13 pin, 14 pin, 12 pin of integrated package U9 respectively, input end 5 pin, 3 pin that output terminal 12 pin of integrated package U12,15 pin meet integrated package U10 respectively, 1 pin of integrated package U12 connects 4 pin of single-chip microcomputer U1; Output terminal 13 pin, 10 pin that input end 3 pin of integrated package U13,4 pin meet integrated package U10 respectively, input end 6 pin of integrated package U13,11 pin, 13 pin, 14 pin connect output terminal 4 pin, 1 pin, 13 pin, 10 pin of integrated package U11 respectively, input end 14 pin, 12 pin that output terminal 2 pin of integrated package U13,5 pin meet integrated package U10 respectively, output terminal 7 pin of integrated package U13,10 pin, 12 pin, 15 pin connect input end 5 pin, 3 pin, 14 pin, 12 pin of integrated package U11 respectively; 1 pin of integrated package U13 connects 4 pin of single-chip microcomputer U1.
5. random waveform low frequency signal source according to claim 4, it is characterized in that described wave memorizer is made up of integrated package U14 and peripheral cell thereof or a door U7C, two-way end 21 pin of integrated package U14, the 23-25 pin, the 2-3 pin connects output terminal 2 pin of integrated package U12 respectively, 5 pin, 7 pin, 10 pin, 12 pin, 15 pin, the two-way end 4-9 pin of integrated package U14 connects output terminal 2 pin of integrated package U13 respectively, 5 pin, 7 pin, 10 pin, 12 pin, 15 pin, two-way end 21 pin of integrated package U14, the 23-25 pin connects input end 5 pin of integrated package U9 respectively, 3 pin, 14 pin, 12 pin, the two-way end 2-5 pin of integrated package U14 connects input end 5 pin of integrated package U10 respectively, 3 pin, 14 pin, 12 pin, the two-way end 6-9 pin of integrated package U14 connects input end 5 pin of integrated package U11 respectively, 3 pin, 14 pin, 12 pin, 10 pin of integrated package U14,14 pin are ground connection respectively, 26 pin of integrated package U14,28 pin connect respectively+5V, or input end 1 pin of door U7C connects 16 pin of single-chip microcomputer U1, or input end 2 pin of door U7C connect output terminal 10 pin of the 3-8 code translator U2 in the single chip machine controlling circuit, or output terminal 3 pin of door U7C connect 27 pin of integrated package U14.
6. random waveform low frequency signal source according to claim 5, it is characterized in that described Wave data latch is made up of integrated package U18, input end 3 pin of integrated package U18,4 pin, 7 pin, 8 pin, 13 pin, 14 pin, 17 pin, 18 pin connect output terminal 11-13 pin, the 15-19 pin of integrated package U14 respectively, the 1 pin ground connection of integrated package U18.
7. random waveform low frequency signal source according to claim 6, it is characterized in that described D/A converter is by integrated package U19 and peripheral cell resistance R 4-R6 thereof, capacitor C 6-C8, voltage stabilizing diode D1 forms, the input end 18-11 pin of integrated package U19 connects output terminal 2 pin of integrated package U18 respectively, 5 pin, 6 pin, 9 pin, 12 pin, 15 pin, 16 pin, 19 pin, 2 pin of integrated package U19,5 pin, 7 pin, 8 pin connect respectively+5V, 1 pin of integrated package U19,9 pin are ground connection respectively, capacitor C 6 is connected between 3 pin and ground of integrated package U19, resistance R 4 be connected on after voltage stabilizing diode D1 connects+9V and ground between, resistance R 5 be connected between the positive pole and ground of voltage stabilizing diode after R6 connects, capacitor C 7, in parallel after the C8 parallel connection with resistance R 6, the positive pole of capacitor C 8 connects 4 pin of integrated package U19, and output terminal 6 pin of integrated package U19 connect input end 12 pin that low pass filtered involves the follower U23D in the amplifying circuit.
8. random waveform low frequency signal source according to claim 7, it is characterized in that described 8 ternary data buffers are made up of integrated package U17, input end 2 pin of integrated package U17,4 pin, 6 pin, 8 pin, 11 pin, 13 pin, 15 pin, 17 pin connect the 39-32 pin of single-chip microcomputer U1 respectively, output terminal 18 pin of integrated package U17,16 pin, 14 pin, 12 pin, 9 pin, 7 pin, 5 pin, 3 pin connect 11-13 pin, the 15-19 pin of integrated package U14 respectively, and 1 pin of integrated package U17,19 pin connect output terminal 10 pin of the 3-8 code translator U4 in the single chip machine controlling circuit respectively.
9. random waveform low frequency signal source according to claim 8, it is characterized in that described channel to channel adapter is made up of integrated package U16, input end 3 pin of integrated package U16,4 pin, 7 pin, 8 pin, 13 pin, 14 pin, 17 pin, 18 pin connect the 39-32 pin of single-chip microcomputer U1 respectively, the low pass filtered that output terminal 12 pin of integrated package U16,9 pin, 6 pin connects respectively involves the input end 9-11 pin of 8 analog switch U25 in the amplifying circuit, and 1 pin of integrated package U16,11 pin connect 27 pin, 16 pin of single-chip microcomputer U1 respectively.
10. random waveform low frequency signal source according to claim 9, it is characterized in that described reference clock circuit is by frequency selector U21 and peripheral cell and door U20A-U20D, or door U7D, U22A, not gate U8D forms, the input end 11-9 pin of frequency selector U21 connects output terminal 19 pin of integrated package U16 respectively, 16 pin, 15 pin, input end 3 pin of frequency selector U21,4 pin connect output terminal 13 pin of the timer conter U4 in the single chip machine controlling circuit respectively, 17 pin, input end 1 pin of frequency selector U21,2 pin connect 5 pin of the integrated package U5A in the frequency dividing circuit in the single chip machine controlling circuit respectively, 5 pin of integrated package U5B, the 12-15 pin of frequency selector U21 connects+5V, the 7 pin ground connection of frequency selector U21; With input end 4 pin of door U20B, output terminal 5 pin that 5 pin meet frequency selector U21 respectively, with input end 9 pin of door U20C, output terminal 5 pin that 10 pin meet frequency selector U21 respectively, with output terminal 6 pin of door U20B; Or input end 4 pin, output terminal 5 pin that 5 pin meet frequency selector U21 respectively of door U7D; Connect output terminal 8 pin with door U20C respectively with input end 12 pin, 13 pin of door U20D, connect 22 pin of integrated package U14 with output terminal 11 pin of door U20D; With input end 1 pin, 2 pin of door U20A connect respectively the 3-8 code translator U2 in the single chip machine controlling circuit 10 pin, with output terminal 8 pin of door U20C, connect clock end 9 pin of integrated package U12, U13 respectively with output terminal 3 pin of door U20A; Connect sheet choosing end 20 pin of integrated package U14 with output terminal 3 pin of door U20A; Or input end 9 pin, 10 pin of door U22A connect respectively or output terminal 6 pin of door U7D, or output terminal 8 pin of door U22A connect clock end 11 pin of integrated package U18; Input end 5 pin of not gate U8D connect or the door U7D output terminal 6 pin, output terminal 6 pin of not gate U8D connect clock end 10 pin of integrated package U19.
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| CNU2007201020879U CN201063116Y (en) | 2007-07-30 | 2007-07-30 | Low frequency signal source for arbitrary waveform |
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| CNU2007201020879U CN201063116Y (en) | 2007-07-30 | 2007-07-30 | Low frequency signal source for arbitrary waveform |
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