CN102201819A - Frequency synthesis source applied by DDS short-wave transmitter based on CPLD design - Google Patents
Frequency synthesis source applied by DDS short-wave transmitter based on CPLD design Download PDFInfo
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Abstract
The invention relates to a frequency synthesis source applied by a DDS short-wave transmitter based on a CPLD design. The frequency synthesis source mainly comprises a direct digital synthesis circuit, a high-speed DAC transformation circuit, a tracking filter circuit and a gain control circuit, a controller and a phase locked crystal oscillator. According to the invention, the high-speed DAC transformation circuit converts frequency data output by direct digital synthesis circuit to a sine frequency signal; and the tracking filter circuit filters components of stray and harmonic wave in the high-speed DAC transformation circuit, and the gain control circuit enables the output of the direct digital synthesis circuit to be stable in amplitude within a frequency range. In addition, the controller comprises a microprocessor and a microcomputer, wherein the microprocessor is connected with the microcomputer through an interface circuit of the microcomputer, and frequency arrangement and transition of working mode are realized by an upper computer. The phase locked crystal oscillator generates a clock source signal with ultrahigh frequency and high stability, and the clock source signal is used as a clock signal of the frequency synthesis source. The frequency synthesis source applied by a DDS short-wave transmitter based on a CPLD design provided in the invention has advantages of high frequency accuracy and high distinguishability, short switching time of frequency signals, constant output amplitude, and simple and high-reliable circuit.
Description
Technical field
The present invention relates to the frequency synthesizer technical field, particularly a kind of short-wave band transmitter based on complex programmable device (CPLD) employing direct digital frequency synthesis technology is used the frequency synthesized signal source.
Background technology
At present, in the shortwave transmitting set, need the frequency synthesis source to produce the short frequency pumping signal of required 1.5MHz～30MHz, its characteristic is directly connected to the performance index of shortwave transmitting set.Now, along with a large amount of uses of short wave communication equipment, channel is more and more crowded, disturbs increasingly, causes the continuous deterioration of electromagnetic environment, and we require the frequency synthesis source noise lower, spuious littler.In addition, the development of short wave communication new technology such as frequency hopping is also had higher requirement to performance index such as the scope of frequency scanning and switch speeds thereof.We wish the prompt change of the output frequency of synthesized source, and band limits is wide as far as possible.
Adopt the frequency of phase locking combiner circuit, can be subject to the restriction of frequency interval and frequency inverted time, be difficult to satisfy frequency hopping communications the prompt requirement that becomes and switch at a high speed of output frequency; Adopt Direct Digital Frequency Synthesizers, have the fast characteristics of frequency switch speed, can reach tens of nanosecond orders, still special-purpose DDS chip is fixed owing to its internal structure, and generally adopts serial port setting, uses inconvenient in some cases.
Direct Digital Frequency Synthesizers is at first sampled to the waveform that needs produce, and will deposit the sinusoidal waveform memory after the sampled value digitlization in, then tables look-up by phase accumulator again data are read, and converts the sinusoidal analog quantity of ladder to through the high-speed DAC transducer again.Special-purpose DDS integrated chip is integrated in chip internal with the high-speed DAC transducer, and the DDS frequency synthesizer circuit of programming device designs such as employing FPGA needs specialized high-speed DAC converter chip, has increased the complexity and the cost of system.
The DAC transducer is output as the sinusoidal analog quantity of ladder, needs the output of filter smoothing DAC transducer, with the unnecessary spuious and harmonic signal of filtering.In the typical case of general special-purpose DDS integrated chip used, the filter of being recommended was wideband low pass or broadband band-pass filter.The upper frequency limit of wideband low pass filter depends on the upper limit of DDS output frequency, if the bandwidth of band pass filter has surpassed the octave of output frequency, they to the spuious and harmonic signal of high-speed DAC transducer output basically incapability be power, especially when output frequency is higher sampled point seldom, filtering this moment is special can understand non-constant.If adopt frequency-tracking arrowband frequency-selective filtering, because it has very high Q value, resonance point is positioned at center frequency points all the time, can fundamentally solve the bad problem of wideband low pass filter filtering performance.Fig. 4 has provided broadband bandpass filtering and the characteristic of following the tracks of the arrowband frequency-selective filtering respectively, and obviously, the characteristic of following the tracks of the arrowband frequency-selective filtering is much better than the former.
Summary of the invention
Technical problem to be solved by this invention is: provide a kind of DDS short-wave transmitter of the CPLD of employing design to use the frequency synthesis source, to solve the problem that above-mentioned prior art exists.
The present invention solves its technical problem and adopts following technical scheme:
DDS short-wave transmitter provided by the invention is used the frequency synthesis source, the DDS short-wave transmitter that is a kind of CPLD of employing design is used the frequency synthesis source, this frequency synthesis source mainly is made up of direct digital synthesis circuit, high-speed DAC translation circuit, tracking filter and gain control circuit, controller and phase-locked crystal oscillator source, and wherein: the high-speed DAC translation circuit becomes the sinusoidal frequency signal with the frequency data Bian Change of direct digital synthesis circuit output; Spuious and harmonic component in tracking filter and the gain control circuit filtering high-speed DAC Bian Change circuit, gain control circuit makes the frequency synthesis source keep the output of amplitude stabilization in frequency range; Controller comprises microprocessor and microcomputer, realizes the setting of frequency and the operation of working method by microprocessor, and perhaps microprocessor connects microcomputer by microcomputer interface circuit, and realizes the setting and the working method De Zhuan Change of frequency by host computer; Phase-locked crystal oscillator source produces the high steady clock source signals of hyperfrequency, as the clock signal in this frequency synthesis source.
Described Direct Digital Frequency Synthesizers is made up of the data register that connects successively with the signal of telecommunication, phase accumulator and sinusoidal waveform question blank, wherein: data register produces the frequency control word of parallel or serial, by inquiry sinusoidal waveform question blank, obtain corresponding frequency control data, this frequency control data is by the parallel phase accumulator that inputs to of data register.
Described phase accumulator, its figure place is chosen flexibly according to the desired resolution of Direct Digital Frequency Synthesizers.
Parallel or the serial of the frequency control word of controller output input to data register, the parallel phase accumulator that inputs to of the frequency control data of data register storage by inquiry sinusoidal waveform question blank, obtains corresponding ladder sine wave shape.
Described high-speed DAC translation circuit is made up of the register that connects successively with the signal of telecommunication and position diverter switch, R-2R resistor network and buffer amplifier.
Described tracking filter and gain control circuit are mainly cut Change tracking filter amplifier and gain control circuit, output wave band electrical analogue switch, broadband buffer amplifier and amplitude by the input wave band electrical analogue switch, the subrane that are connected successively with the signal of telecommunication and are picked up slowdown monitoring circuit and form.
Described tracking filter and gain control circuit, it adopts subrane Qie Change circuit that the frequency range Qie Change of high-speed DAC Bian Change circuit output is become four wave bands, every wave band is earlier through band filter filtering, amplify through following the tracks of selective frequency amplifier circuit again, spuious and harmonic wave composition in the sinusoidal ladder frequency signal is eliminated, utilized gain control circuit that the interior output amplitude of frequency range of output is stablized then.
Described phase-locked crystal oscillator source is made up of variable frequency divider, external loop filter and the ultraharmonics crystal oscillator of the phase discriminator that connects successively with the signal of telecommunication, CPLD design.
The 10MHz temperature compensating crystal oscillator is adopted in described phase-locked crystal oscillator source, by phased lock loop locking ultraharmonics crystal oscillator.
Described 10MHz temperature compensating crystal oscillator can be accepted the Synchronization Control of the high steady 10MHz signal of outer input, makes oneself the output of locking ultraharmonics crystal oscillator reach very high frequency stability.
Above-mentioned DDS short-wave transmitter provided by the invention is used the frequency synthesis source, and it uses in the shortwave transmitting set of the short frequency pumping signal that works in 1.5MHz～30MHz.
The present invention compared with prior art has following main advantage:
1. adopt the Direct Digital frequency synthesizer circuit of CPLD design, taken into account frequency switch speed that the Direct Digital Frequency Synthesizers special integrated chip had reach soon the complex programmable device flexibly, control dual characteristics easily.
2. based on the high-speed DAC circuit of CPLD, saved special-purpose DAC integrated chip, memory cell is selected flexibly, and low in energy consumption, response speed is fast, and greatly reduces the complexity of cost and circuit.
3. designed tracking filter selective frequency amplifier circuit accomplishes that really each Frequency point all is in best resonance condition, eliminates the spuious and harmonic wave composition in the sinusoidal ladder frequency signal significantly, has improved the spectral purity of output frequency signal greatly.
4. designed gain controlling amplifying circuit has improved the amplitude-frequency characteristic of output signal greatly, has reduced the uneven degree in the reference frequency output.
5. the 10MHz temperature compensating crystal oscillator is selected in phase-locked crystal oscillator source for use, by phased lock loop locking ultraharmonics crystal oscillator.But the high steady 10MHz clock signal of outer simultaneously input is Synchronization Control 10MHz temperature compensating crystal oscillator also, can make oneself the output of locking ultraharmonics crystal oscillator reach very high frequency stability.
6. The controller and microcomputer interface circuit are easy to realize the setting of frequency and the conversion of working method, and function upgrading is convenient.
7. work in short-wave transmitter 1.5MHz～30MHz frequency range Inner, output has to hang down makes an uproar mutually, reached-the 90dBc/Hz(@10kHz skew), improved more than the 20dB than the same frequency range DDS frequency synthesizer that does not adopt the narrow-band tracking selective frequency filter circuit, be highly suitable for as short-wave band carrier of transmitter source.
8. adopt the ultraharmonics crystal oscillator of high-performance compensation crystal oscillator locking, when frequency is 140MHz, survey noise level to reach-the 120dBc/Hz(@lkHz skew), it is supplied with the DDS chip as the reference frequency.
In a word, working stability of the present invention is reliable and low in energy consumption, and the resolution height has realized that the victory of output frequency becomes and switches at a high speed, has particularly significantly reduced the spuious and harmonic component of output.
Description of drawings
Fig. 1 is a structured flowchart of the present invention.
Fig. 2 is the circuit structure diagram of high-speed DAC conversion of the present invention.
Fig. 3 is the fundamental diagram of mat woven of fine bamboo strips triband of the present invention.
Fig. 4 is the characteristic comparison diagram of narrow band tracking filter of the present invention and broadband band-pass filter.
Fig. 5 is a concrete structure block diagram of the present invention.
Embodiment
The invention will be further described below in conjunction with embodiment and accompanying drawing.
The DDS short-wave transmitter of employing provided by the invention CPLD design is used the frequency synthesis source, its structure as shown in Figure 5: comprise direct digital synthesis circuit, high-speed DAC translation circuit, tracking filter and gain control circuit, phase-locked crystal oscillator source, controller.Wherein: empty frame (1) is that it is made up of the data register that connects successively with the signal of telecommunication, phase accumulator and sinusoidal waveform question blank by the Direct Digital Frequency Synthesizers (DDS) of complex programmable designs among Fig. 5.Empty frame (2) is the high-speed DAC translation circuit by the complex programmable designs, and with reference to figure 2, it is made up of the register that connects successively with the signal of telecommunication and position diverter switch, R-2R resistor network and buffer amplifier.Empty frame (3) is tracking filter and gain control circuit, with reference to figure 3, it is picked up survey etc. by the input wave band electrical analogue switch, subrane tracking filter amplifier and the gain controlling that connect successively with the signal of telecommunication, output wave band electrical analogue switch, broadband buffer amplifier and amplitude and forms.Empty frame (4) is phase-locked crystal oscillator source, and it is made up of variable frequency divider, external loop filter and the ultraharmonics crystal oscillator of the phase discriminator that connects successively with the signal of telecommunication, CPLD design.Empty frame (5) is a controller, comprises microprocessor and microcomputer, and the interface circuit of microprocessor comprises keyboard, demonstration, D/A1 and D/A2, A/D, serial port circuit etc.; Microcomputer can be realized operation to microprocessor by serial port circuit or USB.
But described direct digital synthesis circuit is designed by complexity coder spare CPLD.Referring to Fig. 1 and Fig. 5, it comprises parts such as data register, phase accumulator, sinusoidal waveform question blank.Wherein data register storing frequencies control data (frequency control word) has the serial input function, and serial input is come self-controller or microcomputer, and parallel data can realize fast frequency-hopped function from CPLD.The parallel phase accumulator that inputs to of the frequency control data of data register can be chosen according to the desired resolution of frequency synthesizer flexibly by the figure place of the phase accumulator of CPLD design.The high m parallel-by-bit of phase accumulator output sequence inputs to the sinusoidal waveform question blank by CPLD design, and sinusoidal waveform question blank De Cun storage capacity has been taken all factors into consideration DDS precision, error and taken factor such as resource, generally selects 256 or 512 memory cell for use.Wherein parallel input phase accumulator circuit how many positions that need walk abreast are by clock frequency and resolution decision.
The structure of described phase accumulator circuit is shown in add28 among Fig. 2.Because of the operating frequency of DDS depends on selected CPLD, if consider to select general CPLD,, CPLD is operated in below the 200MHz in order to guarantee the reliability of work from cost performance,
If,, be minimum resolution, then can calculate resolution and be: Hz.
The structure of described sinusoidal waveform memory circuitry is shown in Sin256 among Fig. 3, and obviously memory cell is big more, and sampled point resolution more at most is high more.But this conclusion is only effective when lower frequency, and when frequency was very high, most of sample values were rejected.So compromise selection 256 byte memory unit, every byte eight-digit binary number, totally eight bit address line eight bit data lines.The sinusoidal waveform memory is connected with the high eight-bit of parallel input phase accumulator is parallel, and other positions are rejected.
Above-mentioned CPLD can be the CPLD of the MAX II series of ALTERA company, also can be the CPLD of XILINX or other company.
Described high-speed DAC translation circuit as shown in Figures 2 and 3, it has provided the structure by one 8 high-speed DAC Bian Change circuit of CPLD design.DAC256 among the figure is the fast data buffer register and the high speed Wei Qie Change switch of CPLD design, and their operating frequencies and selected CPLD operating frequency are suitable, can satisfy the requirement of short-wave transmitter frequency synthesis source to the DAC change-over circuit fully.External high precision reference voltage source and low error R-2R resistor network are subjected to the control of Wei Qie Change switch, and its output is amplified back output through transporting the grate amplifier buffer at a high speed, become sinusoidal ladder frequency signal to export the frequency data Bian Change of sinusoidal waveform question blank.
Resistance value in the R-2R resistor network is more little, and then response speed is high more, but just high more to the requirement of reference voltage source.The access of R-2R resistor network is subjected to the control of high speed Wei Qie Change switch, and its output is amplified back output through transporting at a high speed the grate amplifier buffer, becomes sinusoidal ladder frequency signal to export the frequency data Bian Change of sinusoidal waveform question blank.Obviously remove sinusoidal fundamental frequency signal place in the output, also comprised many spuious and harmonic components, need by the filter circuit filtering.
Tracking filter of the present invention and gain control circuit are by input subrane diverter switch, wide waveband band filter, follow the tracks of frequency-selecting, form with gain controlling amplifying circuit etc.The tracking filter and the gain control circuit of mat woven of fine bamboo strips triband have been provided among Fig. 3, complete circuit is formed as shown in Figure 5: the frequency range of 1.5MHz～30MHz is cut Change become four wave bands, the wave band commutation circuit adopts high-speed analog switch, wherein the frequency range of the mat woven of fine bamboo strips one wave band is 1.5MHz～8MHz, because its frequency is lower, sampled point is more, so elliptic function filter can obtain desirable output waveform.The frequency range Fen Do of the mat woven of fine bamboo strips two～four wave bands is 8MHz～12MHz, and 12MHz～19MHz and 19MHz～30MHz, the topped coefficient of its frequency are less than 1.6, so adopt voltage-controlled tracking filter circuit easily.
Described gain control circuit is with reference to figure 3 and Fig. 5, and the DDS and high-speed DAC change Change circuit and the amplifying circuit etc. that are designed by CPLD all have certain amplitude-frequency characteristic, produce distortion.Gain control circuit is according to the amplitude-frequency characteristic of system, amplitude detection circuit (detection and ADC change-over circuit) by frequency control word and signal output part, DAC by controller provides gain-controlled voltage, effectively compensation amplitude-frequency characteristic error is stablized the interior output amplitude of frequency range of 1.5MHz～30MHz.
Described tracking filter and gain control circuit, its course of work is: earlier with two～four wave bands of high-speed DAC Bian Change circuit output respectively through broadband buffer amplifier filtering, amplify through separately tracking selective frequency amplifier circuit again.Follow the tracks of the DAC output that voltage-controlled tuning voltage is taken from controller, its output voltage size is determined by frequency control word, and the variable capacitance diode of output voltage control loop makes the tracking selective frequency amplifier circuit be in the optimal tuning state.After such processing, can effectively eliminate the spuious and harmonic wave composition in the sinusoidal ladder frequency signal.Gain control circuit provides gain-controlled voltage by frequency control word by another DAC according to the amplitude-frequency characteristic of system, effectively compensates the amplitude-frequency characteristic error, and the interior output amplitude of reference frequency output of 1.5MHz～30MHz is stablized.
Described tracking filter circuit is actually the frequency selective amplifier of a controllable gain, and the amplifying device of selecting for use is dual gate FET 3SK223, also can adopt similar model, and the very convenient mat woven of fine bamboo strips two grids that utilize carry out amplitude control.Described broadband buffer amplifier is selected AD603 for use, also can adopt similar model, the also very convenient gain controlling of carrying out.
Described phase-locked crystal oscillator source, can select the 10MHz temperature compensating crystal oscillator for use, referring to Fig. 5, by external phase discriminator, the variable frequency divider of CPLD design, the phase-locked loop locking ultraharmonics crystal oscillator that external loop filter and ultraharmonics crystal oscillator are formed, its locking ultraharmonics crystal oscillator method is: by by phase discriminator, variable frequency divider, the phased lock loop that loop filter and ultraharmonics crystal oscillator are formed, high steady 10MHz signal by temperature compensating crystal oscillator output, as reference source locking ultraharmonics crystal oscillator, can make 10MHz crystal oscillator and the complementation of ultraharmonics crystal oscillator characteristic.The 10MHz crystal oscillator is controlled by the high steady 10MHz synchronization of clock signals of outer input also can simultaneously, and oneself can reach very high frequency stability at the output of locking ultraharmonics crystal oscillator, as master clock signal of the present invention.
Described phase-locked loop can adopt phase-locked chip 74LVC4046, also can adopt above-mentioned CPLD design, but prescaler is finished ultraharmonics crystal oscillator and buffer circuit employing gate circuit 74LVC04 by programming device.
That described controller is mainly used to dispose is tuning by the frequency control word in the data register of CPLD design and working method thereof, wave band conversion and control, voltage-controlled narrow-band tracking, gain-controlled voltage and output amplitude testing circuit etc.By revising the frequency control word of the data register among the CPLD, system can obtain the synthetic output of 1.5MHz～30MHz frequency range Inner optional frequency.This controller is AT91RM9200 or other single-chip microcomputer of atmel corp, also can select the ARM single-chip microcomputer for use.
Described interface circuit referring to Fig. 5, mainly contains: keyboard input, liquid crystal display, wave band control, the voltage-controlled DAC of tracking filter, gain controlling DAC, output amplitude detection and serial port circuit etc.Wherein the keyboard input is provided with operating frequency and mode and provides demonstration with liquid crystal display; The voltage-controlled DAC of tracking filter provides corresponding voltage-controlled voltage according to frequency control word, makes the tracking filter circuit be in the optimal tuning state all the time; Gain controlling DAC and output amplitude are picked up slowdown monitoring circuit can by the output voltage of ride gain control DAC, make output high-frequency signal maintenance amplitude-Ding in whole reference frequency output simultaneously according to frequency control word and output amplitude size.
Described microcomputer, it connects controller (Fig. 1 and Fig. 5) by interface circuit, is realized the setting and the working method De Zhuan Change of frequency by the upper computer software interface.
The foregoing description provided by the invention, be based on Direct Digital frequency synthesis (DDS) technology of complex programmable device (CPLD), the Direct Digital frequency synthesizer circuit that it is designed, having taken into account Direct Digital Frequency Synthesizers has the frequency switch speed and reaches the flexible characteristics of complex programmable device soon, particularly adopt high-speed DAC circuit, saved special-purpose DAC integrated chip and synthesized the waveform that is stored in the memory based on CPLD from wound.Referring to Fig. 4, adopt subrane to follow the tracks of frequency-selecting filter filtering, can effectively eliminate the spuious and harmonic wave composition in the sinusoidal ladder frequency signal, make output waveform very perfect.In addition,,, can effectively compensate DDS amplitude-frequency characteristic error, make the output amplitude in its frequency range stable by output gain control voltage according to frequency control word and in conjunction with the fluctuation of output amplitude.
The above is preferred embodiment of the present invention only, is not that structure of the present invention is done any pro forma restriction.Every foundation technical spirit of the present invention is to any simple modification, equivalent variations that above embodiment did, all still belong in the scope of technical scheme of the present invention, technical scheme of the present invention also can be used for the DDS synthesized source of other purposes of local oscillator information source of short-wave receiver.
Claims (10)
1. a DDS short-wave transmitter is used the frequency synthesis source, the DDS short-wave transmitter that it is characterized in that a kind of CPLD of employing design is used the frequency synthesis source, this frequency synthesis source mainly is made up of direct digital synthesis circuit, high-speed DAC translation circuit, tracking filter and gain control circuit, controller and phase-locked crystal oscillator source, and wherein: the high-speed DAC translation circuit becomes the sinusoidal frequency signal with the frequency data Bian Change of direct digital synthesis circuit output; Spuious and harmonic component in tracking filter and the gain control circuit filtering high-speed DAC translation circuit, gain control circuit make the frequency synthesis source keep the output of amplitude stabilization in frequency range; Controller comprises microprocessor and microcomputer, realizes the setting of frequency and the operation of working method by microprocessor, and perhaps microprocessor connects microcomputer by microcomputer interface circuit, and realizes the setting and the working method De Zhuan Change of frequency by host computer; Phase-locked crystal oscillator source produces the high steady clock source signals of hyperfrequency, as the clock signal in this frequency synthesis source.
2. DDS short-wave transmitter according to claim 1 is used the frequency synthesis source, it is characterized in that described Direct Digital Frequency Synthesizers is made up of the data register that connects successively with the signal of telecommunication, phase accumulator and sinusoidal waveform question blank, wherein: data register produces the frequency control word of parallel or serial, by inquiry sinusoidal waveform question blank, obtain corresponding frequency control data, this frequency control data is by the parallel phase accumulator that inputs to of data register.
3. DDS short-wave transmitter according to claim 2 is used the frequency synthesis source, it is characterized in that described phase accumulator, and its figure place is chosen flexibly according to the desired resolution of Direct Digital Frequency Synthesizers.
4. DDS short-wave transmitter according to claim 1 is used the frequency synthesis source, it is characterized in that described high-speed DAC translation circuit is made up of the register that connects successively with the signal of telecommunication and a position diverter switch, R-2R resistor network and buffer amplifier.
5. DDS short-wave transmitter according to claim 1 is used the frequency synthesis source, it is characterized in that described tracking filter and gain control circuit are mainly switched tracking filter amplifier and gain control circuit, exported wave band electrical analogue switch, broadband buffer amplifier and amplitude and pick up slowdown monitoring circuit and form by the input wave band electrical analogue switch that is connected successively with the signal of telecommunication, subrane.
6. DDS short-wave transmitter according to claim 5 is used the frequency synthesis source, it is characterized in that described tracking filter and gain control circuit, it adopts the subrane commutation circuit that the frequency range of high-speed DAC translation circuit output is switched to four wave bands, every wave band is earlier through band filter filtering, amplify through following the tracks of selective frequency amplifier circuit again, spuious and harmonic wave composition in the sinusoidal ladder frequency signal is eliminated, utilized gain control circuit that the interior output amplitude of frequency range of output is stablized then.
7. DDS short-wave transmitter according to claim 1 is used the frequency synthesis source, it is characterized in that described phase-locked crystal oscillator source is made up of variable frequency divider, external loop filter and the ultraharmonics crystal oscillator of the phase discriminator that connects successively with the signal of telecommunication, CPLD design.
8. DDS short-wave transmitter according to claim 7 is used the frequency synthesis source, it is characterized in that described phase-locked crystal oscillator source employing 10MHz temperature compensating crystal oscillator, by phased lock loop locking ultraharmonics crystal oscillator.
9. DDS short-wave transmitter according to claim 8 is used the frequency synthesis source, the Synchronization Control that it is characterized in that the high steady 10MHz signal of the outer input of described 10MHz temperature compensating crystal oscillator acceptance makes the output of own locking ultraharmonics crystal oscillator reach very high frequency stability.
10. the described DDS short-wave transmitter of arbitrary claim is characterized in that described frequency synthesis source uses with the purposes in frequency synthesis source in the claim 1 to 9 in the shortwave transmitting set of the short frequency pumping signal that works in 1.5MHz～30MHz.
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| CN103346874A (en) * | 2013-06-20 | 2013-10-09 | 桂林电子科技大学 | Digital communication clock synchronization system based on DDS |
| CN103346874B (en) * | 2013-06-20 | 2017-04-19 | 桂林电子科技大学 | Digital communication clock synchronization system based on DDS |
| CN103944540A (en) * | 2014-05-08 | 2014-07-23 | 成都雷电微力科技有限公司 | Triangular wave signal generator |
| CN104142430A (en) * | 2014-07-07 | 2014-11-12 | 盐城工学院 | RLC measuring instrument and measuring method |
| CN105515575A (en) * | 2015-12-05 | 2016-04-20 | 青岛盛嘉信息科技有限公司 | Sinusoidal signal frequency generator |
| CN108599783A (en) * | 2018-05-24 | 2018-09-28 | 南京熊猫电子股份有限公司 | A kind of frequency distribution module that frequency is configurable |
| CN108712167A (en) * | 2018-05-24 | 2018-10-26 | 南京熊猫电子股份有限公司 | A kind of mark frequency distribution module with adaptive frequency-selecting characteristic |
| CN108712167B (en) * | 2018-05-24 | 2021-11-23 | 南京熊猫电子股份有限公司 | Standard frequency distribution module with self-adaptive frequency selection characteristic |
| CN110176929A (en) * | 2019-06-20 | 2019-08-27 | 常州国光数据通信有限公司 | A kind of binary channels local oscillator source module receiving system simultaneously for shortwave two-way |
| CN110988760A (en) * | 2019-12-06 | 2020-04-10 | 天津大学 | Digital signal detection system of Mx type cesium optical pump magnetometer |
| CN110988760B (en) * | 2019-12-06 | 2024-05-28 | 天津大学 | Digital signal detection system of Mx cesium light pump magnetometer |
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