CN2624292Y - ASIC for multimachine sharing of counter and signal generator - Google Patents
ASIC for multimachine sharing of counter and signal generator Download PDFInfo
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- CN2624292Y CN2624292Y CNU032270984U CN03227098U CN2624292Y CN 2624292 Y CN2624292 Y CN 2624292Y CN U032270984 U CNU032270984 U CN U032270984U CN 03227098 U CN03227098 U CN 03227098U CN 2624292 Y CN2624292 Y CN 2624292Y
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Abstract
An ASIC for multiple shared counters and signal generator is provided, which adopts a FPGA chip, and internally comprises a PC interface circuit (6), a SCM interface circuit (7), a display latch register (9), an equivalent precision pre-processor (12), a frequency divider (14), a keyboard receiver (15), a counter controller (16), a counter (17), a delay trigger (18), a latch register (19), an analog input signal processing circuit (20), a signal generator controller (21), a waveform parameter register (22), a digital filter (23), an address generator (25), a waveform data memory (26), a data converter (32), and a digital extender (33). The multiple shared counter and signal generator with the ASIC have small volume, easy operation, in parallel working, excellent interface, multiple functions, high performance, and high performance cost ratio.
Description
Technical field
The utility model relates to a kind of chip that is used for counter and signal generator, is meant a kind of Multi-computer Sharing counter of fpga chip and ASIC that signal generator is used of adopting especially.
Background technology
Multi-functional counter and signal generator are scientific research and development, education experiment, two kinds of the most the most frequently used electronic devices of plant maintenance, they mostly are discrete, intelligent product for present China, there is not its integrated ASIC product, there is not its virtual product yet, they can not make full use of the PC rich in natural resources, also just can not expand the function and the usability that makes things convenient for that improves instrument of instrument fully, so its price is higher, function few, it is more tired to use.
The utility model content
The ASIC that provides a kind of Multi-computer Sharing counter and signal generator to use is provided the purpose of this utility model, adopts that the instrument of this ASIC has that volume is little, easy to operate, concurrent working, interface grace, function is many, performance is high, cost performance is high characteristics.
For achieving the above object, the ASIC that this Multi-computer Sharing counter and signal generator are used adopts fpga chip, and its internal circuit comprises
The PC interface circuit is used to realize three bus driver, isolation and the decoding of PC and FPGA;
Frequency divider is used for external clock signal is treated to the required various types of signal of system;
Signal produces controller, is used to produce the square wave that satisfies user's frequency and dutycycle requirement;
The waveform parameter register is used to deposit the waveform parameter that the user imports;
Address generator is used for the address and produces;
Waveform data memory is used to store non-rectangle wave-wave graphic data;
Digital filter; Be used for the burr that erasure signal produces square wave that controller produces;
The numeral expander is used for the output of digital filter is expanded.
The ASIC that this Multi-computer Sharing counter and signal generator are used also comprises
The analog input signal treatment circuit is used for the simulating signal arrangement of different amplitudes is the Transistor-Transistor Logic level signal;
Counter-controller is used to count working method and measured signal, user command, clock are organically made up gives counter, time-delay trigger and latch;
Counter is used to finish the counting of measured signal;
Time-delay trigger is used to produce the reset signal of counter;
Latch is used for latching of rolling counters forward result;
Data converter is used for 32 bit data with latch and is converted to 8 bit data and reads for CPU, provides the data useful signal for the CPU inquiry simultaneously.
The ASIC that this Multi-computer Sharing counter and signal generator are used also comprises
Etc. the precision pretreater, be used for the output signal of analog input signal treatment circuit is carried out pre-service.
The ASIC that this Multi-computer Sharing counter and signal generator are used also comprises
The interface microcontroller circuit is used for external single-chip microcomputer and is connected with the bus of FPGA;
The display latch device couples with the interface microcontroller circuit, and the section coded signal of display part latchs when being used for Single Chip Microcomputer (SCM) system work;
The keyboard receiver couples with the interface microcontroller circuit, is used for the I/O mouth that single-chip microcomputer when work latch, cushion for scanning provides when keyboard is discerned.
Adopt Multi-computer Sharing counter and the signal generator of this ASIC to have following advantage:
1) has two kinds of Control work modes of PC and single-chip microcomputer.When PC Control work pattern, can utilize existing PC powerful computing ability and rich in natural resources, expand the function and the usability that makes things convenient for that improves instrument of instrument fully.
When 2) replacing PC work with single-chip microcomputer, the instrument volume is little, is easy to carry, and is fit to very much field work.
3) can realize frequency, cycle, dutycycle, the pulsewidth of outside measured signal, the full-automatic high-acruracy survey of counting, and output frequency, dutycycle satisfy customer requirements and adjustable square-wave signal and other waveform signal of stepping.
Below in conjunction with drawings and the specific embodiments structure of the present utility model is further described.
Description of drawings
Fig. 1 is a concrete application principle block diagram of the present utility model.
Fig. 2 is an electrical schematic diagram of the present utility model.
Embodiment
As shown in Figure 1, Fig. 1 is this ASIC combines the Multi-computer Sharing of forming with PC, single-chip microcomputer counter and a signal generator theory diagram.Be the theory diagram of ASIC in the frame of broken lines among the figure, this ASIC adopts fpga chip, its inside comprise PC interface circuit 6, interface microcontroller circuit 7, display latch device 9, etc. precision pretreater 12, frequency divider 14, keyboard receiver 15, counter-controller 16, counter 17, time-delay trigger 18, latch 19, analog input signal treatment circuit 20, signal produce controller 21, waveform parameter register 22, digital filter 23, address generator 25, waveform data memory 26, data converter 32, digital expander 33.Wherein signal generation controller 21, waveform parameter register 22, address generator 25, waveform data memory 26, digital filter 23, digital expander 33 are used to produce rectangle or other waveform signal of customer requirements; Analog input signal treatment circuit 20, etc. precision pretreater 12, counter-controller 16, counter 17, time-delay trigger 18, latch 19, data converter 32 be used to finish the measurement of outer signal; Interface circuit when PC interface circuit 6, interface microcontroller circuit 7, display latch device 9, keyboard receiver 15 provide PC and single-chip microcomputer and the work of this asic chip.In the external circuits of ASIC: crystal oscillating circuit 13 is used to produce counter, the required work clock of signal generator and System self-test clock; The user imports 1 and is PC keyboard or mouse, is used for inputting user command; PC 2 is the main control computer of user's virtual mode; EPC1 module 3 is the series arrangement chip, is used for the FPGA reprinting file that powers on; Keyboard 4 is a single-chip microcomputer inputting user command equipment; Single-chip microcomputer 5 is the main control computer of single-chip microcomputer mode, band EPROM in this single-chip microcomputer; Wire jumper selector switch 8 is used for the selection of PC and single-chip microcomputer; Display driver circuit 10 is used for the driving of display 11; Display 11 is the LED charactron; Frequency multiplier 24 is used for signal is produced the square wave frequency multiplication of controller 21 outputs; Digital to analog converter 27 is used for the non-rectangle wave datum is converted to simulating signal; Low-pass filter 28 is used to filter simulation high frequency burr; Selector switch 29 is an analog switch, is used for the selection of square wave and other waveform; Amplitude controller 30 is used for the amplitude control of output signal; Output circuit 31 is used for output waveform amplification, driving, reversal etc.
Adopt Multi-computer Sharing counter and the signal generator of this ASIC that two kinds of mode of operations are arranged: PC Control work mode and Single-chip Controlling working method.Mode of operation is selected by wire jumper selector switch 8.When selecting PC Control work mode, the user imports 1 command selection and gives PC 2, and PC 2 is by PC interface circuit 6 and FPGA contact; When selecting the Single-chip Controlling working method, single-chip microcomputer 5 is by interface microcontroller circuit 7 and FPGA contact, and the information of keyboard 4 is delivered to keyboard receiver 15, and keyboard receiver 15 provides interface circuit for single-chip microcomputer 5 keyboard scans.
Describe its concrete principle of work below in detail:
1) measuring-signal.Outside measured signal is delivered to the input end of measured signal treatment circuit 20, amplify through measured signal treatment circuit 20 and to send into FPGA after amplitude limits are shaped as the TTL signal, measuring techniques such as precision such as in all modules of FPGA counter, use to realize frequency, cycle, dutycycle, the pulsewidth of outside measured signal, the full-automatic high-acruracy survey of counting.System precision pretreater 12 such as delivers at the TTL signal of measured signal treatment circuit 20 when the equal precision measurement, 12 the measured signal of precision such as provide to counter-controller 16 again, when measuring, alternate manner then directly delivers to counter-controller 16, counter-controller 16 is under the test mode order control that clock that frequency divider 14 provides and PC 2 or single-chip microcomputer 5 send, export each function and count the required gate-control signal that presets, timing signal, the organic assembling of measured signal is given counter 17, counter 17 is 2 32 digit counters, counter-controller 16 feed signals simultaneously produces effective reset signal to counter 17 for time-delay trigger 18, so that count again after counter 17 zero clearings, and counter-controller 16 is delivered to latch 19 with output, latch 19 effectively latchs the count results of counter 17 before counter 17 zero clearings, latch 19 output 32 bit data and data useful signal are given data converter 32, data converter 32 can divide 32 bit data 4 times under the control of PC 2 or single-chip microcomputer 5, send for each 8, provide the data useful signal simultaneously for PC or single-chip microcomputer inquiry.When PC Control work pattern, count results send the PC display screen to show after being handled by PC; In the Single-chip Controlling working method, handle behind the single-chip microcomputer 5 count pick up results, will result displayed deliver to display latch device 9 with dividing the time-division position, display latch device 9 send the section information that latchs driver 10 driving back to light-emitting diode displays 11 to show.Keyboard receiver 15 is given in the order of keyboard 4, and single-chip microcomputer 5 comes keyboard scan information by interface microcontroller circuit 7 and keyboard receiver 15, obtains user command.
2) produce signal.The signal of user's input produces parameter after PC 2 or single-chip microcomputer 5 processing, deliver to 22 preservations of waveform parameter register through PC interface circuit 6 or interface microcontroller circuit 7, signal produces controller 21 under the clock control of frequency divider 14, can automatically produce square wave and the square-wave signal that satisfies user's frequency and dutycycle requirement by the data that read waveform parameter register 22, signal produces controller 21 output square waves after digital filter 23 digital filterings remove burr when square wave is exported, after 33 expansions of digital expander, give selector switch 29 again, if non-rectangle ripple output, signal produces controller 21 and transports to frequency multiplier 24, frequency multiplier 24 produces the signal of 40 overtones bands and gives address generator 25,25 of address generators are given waveform data memory 26 by 40 frequency multiplication rhythm with the address, 26 data of sending non-rectangle ripple one-period by frequency multiplier 24 output rhythm of waveform data memory, finish digital-to-analog conversion through digital to analog converter 27, finish analogue low pass filtering through low-pass filter 28 again and arrive selector switch 29, selector switch 29 is selected input under the control of PC 2 or single-chip microcomputer 5, amplitude controller 30 is with the output of selector switch 29 reference voltage as own digital to analog converter, the digital quantity input of PC 2 or single-chip microcomputer 5 span of control limit of control controllers 30, amplitude controller is realized the control of output amplitude like this, and output circuit 31 exports amplitude controller again through driving, reversal, voltage-regulation etc. are handled back output.
As shown in Figure 2, bus interface module ZIEKO finishes latching, decipher and driving of three bus signals that PC ISA slot comes, when I/O address this adapter work when being 280H～2F7H, other I/O equipment of this adapter and PC is kept apart, the conversion interface circuit of microcontroller bus is arranged in simultaneously.The selection of its interface circuit is controlled by wire jumper signal XT.
The peripheral crystal oscillator of FPGA adopts one ± 0.5ppm, 50M TCXO crystal oscillator, 2 100M, ± the OSC crystal oscillator of 25ppm is as the input CLKD[2..0 of frequency divider C1], the timing signal Q[1..0 when it is output as system counter works is provided] (CLKK[1..0]), preset reference signal source Q2 (CLKA) that signal strobe Q6 (CLKB2), reference frequency Q4 (CLKB0), self check derived reference signal Q5 (CLKB1) and signal produce etc.PJC is accuracy test pretreatment module such as frequency, the required signal INF[1..0 of counter-controller PK when it accuracy test such as is converted to input signal], if pulsewidth, dutycycle, count measurement TEST[1..0 then] be directly inputted to the INM[1..0 of PK].
PC receives keyboard or the next user command of mouse, single-chip microcomputer receives the then DA[7..0 by JPY of keypad information], DB[7..0] finish scanning, if counter measures then this order is delivered to PK through ZIEKO, the PK module is then sent each functional test required gate-control signal GATE, timing signal CLK, the organic assembling of measured signal to counter cnt 2 under the control of CPU.CNT2 finishes 2 32 synchronous counting, when GATE is high level hour counter counting, stop and latching this count value at the negative edge CNT2 of GATE counting, make the CHX request signal effectively in the timing break in service, allowing PC pass through data converter PJK inquiry reading simultaneously, or supply single-chip microcomputer 5 by PJK inquiry reading, PJK mainly finishes the figure place conversion of 8/32 data and the transmission of state of a control signal, and PC then returns and send screen display after finishing the more accurate numerical computing among the Delphi as if reading valid data.Single-chip microcomputer reads back behind the valid data through sending the DC[7..0 of JPY after the quick computing of high precision], DD[7..0] section that shows latchs, and send external drive to show again.Time-delay trigger YC mainly is made of d type flip flop and some combinational logic circuits, and it produces the reset signal of the negative pulse of one 1 μ S as CNT2 under the negative edge effect of GATE, prepares for CNT2 counts again next time.
If being signal, user command produces, user elder generation incoming wave graphic data then, CPU data computation according to this obtains waveform parameter, and is stored in the waveform parameter register JICUN of FPGA, and these parameters mainly are 13 bit data length DF and DR, 20 remainder Y1,20 bit frequency F1,13 dutycycle Z1.CNT14 is that 14 synchronous down counters of scale-of-two are realized the frequency division task, CNT20 realizes that signal frequency repeats the output task automatically, CMPY is that comparer is to realize the comparison of dutycycle, remainder, frequency, BUSMUK finishes the selection of the required divide ratio of CNT14, CNT14, CNT20, CMPY, BUSMUX etc. have formed the controller that signal produces, can more automatically realize remainder interpolation and duty cycle adjustment by selection, counting, from the Z output terminal output frequency of CMPY, the rectangular signal OUTA that the dutycycle stepping is adjustable to divide ratio.When square wave is exported, OUTA exports E2[7..0 behind digital filter YM, digital expander KUN] to the external analog switch, when the non-rectangle ripple is exported, E21 returns from DN after outside 40 frequency multiplier frequencys multiplication, behind address generator NYC, obtain address D K[5..0], waveform data memory JNT is then by DN rhythm, DK[5..0] the address send Wave data DW[7..0] to the external number weighted-voltage D/A converter, JPY exports DE[7..0] import DF[7..0 as the numeral of amplitude controller] control mouth as the position of CPU.This shows that two instruments can concurrent working.
Based on counter and the signal generator system of this ASIC, designing after its index of experimental verification is as follows:
(1) frequency period counting test:, finish 8 * 10 to cycle signals such as the sine wave of 50mV～50V, 1Hz～100MHz, square wave, triangular waves
-6The measurement of precision, the error during counting are ± 1, and the maximal value of counting is 10
8-1.
(2) dutycycle test: the signal high level is during greater than 2.2 μ S, measuring accuracy 10
-2
(3) pulse width test: pulsewidth less than 21 μ S measuring error less than 21nS; Pulsewidth is greater than 21 μ S measuring accuracy 10
-3Pulsewidth is greater than 700 μ S measuring accuracy 3 * 10
-5
(4) system can self-checking.
(5) signal generator: square wave, square wave frequency 1Hz～1MHz, stepping is 1Hz, frequency accuracy 10
-3, as f≤0.5MHz, dutycycle β=1%～99%, stepping is 1%, dutycycle precision 0.5%, cycle precision 1.1%; As 0.5MHz＜f≤1MHz, β=2%～98%, stepping is 2%, dutycycle precision 1%, cycle precision 2.1%.Sine wave freuqency 1Hz～1MHz, stepping is 1Hz, frequency accuracy 10
-3, cycle precision 2.1%.
Claims (4)
1, the ASIC that uses of a kind of Multi-computer Sharing counter and signal generator is characterized in that: comprise PC interface circuit 6, be used to realize three bus driver, isolation and the decoding of PC and FPGA; Frequency divider 14 is used for external clock signal is treated to the required various types of signal of system; Signal produces controller 21, is used to produce the square wave that satisfies user's frequency and dutycycle requirement; Waveform parameter register 22 is used to deposit the waveform parameter that the user imports.
Address generator 25 is used for the address and produces;
Waveform data memory 26 is used to store non-rectangle wave-wave graphic data;
Digital filter 23 is used for the burr that erasure signal produces square wave that controller produces; Numeral expander 33 is used for the output of digital filter is expanded.
2, the ASIC that uses of Multi-computer Sharing counter according to claim 1 and signal generator is characterized in that: also comprise
Analog input signal treatment circuit 20 is used for the simulating signal arrangement of different amplitudes is the Transistor-Transistor Logic level signal;
Counter-controller 16 is used to count working method and measured signal, user command, clock are organically made up gives counter 17, time-delay trigger 18 and latch 19;
Counter 17 is used to finish the counting of measured signal;
Time-delay trigger 18 is used to produce the reset signal of counter 17;
Latch 19 is used for latching of counter 17 count results;
Data converter 32 is used for 32 bit data with latch 19 and is converted to 8 bit data and reads for CPU, provides the data useful signal for the CPU inquiry simultaneously.
3, the ASIC that uses of Multi-computer Sharing counter according to claim 1 and signal generator is characterized in that: also comprise
Etc. precision pretreater 12, be used for the output signal of analog input signal treatment circuit 20 is carried out pre-service.
4, the ASIC that uses of Multi-computer Sharing counter according to claim 1 and 2 and signal generator is characterized in that: also comprise
Interface microcontroller circuit 7 is used for external single-chip microcomputer and is connected with the bus of FPGA;
Display latch device 9, the section coded signal of display part latchs when being used for Single Chip Microcomputer (SCM) system work;
Keyboard receiver 15 is used for the I/O mouth that single-chip microcomputer when work latch, cushion for scanning provides during to keyboard 4 identifications.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU032270984U CN2624292Y (en) | 2003-03-11 | 2003-03-11 | ASIC for multimachine sharing of counter and signal generator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU032270984U CN2624292Y (en) | 2003-03-11 | 2003-03-11 | ASIC for multimachine sharing of counter and signal generator |
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| CN2624292Y true CN2624292Y (en) | 2004-07-07 |
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| CNU032270984U Expired - Fee Related CN2624292Y (en) | 2003-03-11 | 2003-03-11 | ASIC for multimachine sharing of counter and signal generator |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100405239C (en) * | 2005-12-14 | 2008-07-23 | 苏州科技学院 | Portable electronic simulator of vehicle engine |
| CN105355123A (en) * | 2015-12-24 | 2016-02-24 | 华东师范大学 | Digital circuit teaching experiment system |
| CN105676832A (en) * | 2014-11-17 | 2016-06-15 | 联创汽车电子有限公司 | Signal generator for engine control development |
| CN106843080A (en) * | 2017-03-29 | 2017-06-13 | 杰创智能科技股份有限公司 | A kind of FPGA parallel arrays module and its computational methods |
-
2003
- 2003-03-11 CN CNU032270984U patent/CN2624292Y/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100405239C (en) * | 2005-12-14 | 2008-07-23 | 苏州科技学院 | Portable electronic simulator of vehicle engine |
| CN105676832A (en) * | 2014-11-17 | 2016-06-15 | 联创汽车电子有限公司 | Signal generator for engine control development |
| CN105355123A (en) * | 2015-12-24 | 2016-02-24 | 华东师范大学 | Digital circuit teaching experiment system |
| CN105355123B (en) * | 2015-12-24 | 2018-01-16 | 华东师范大学 | A kind of Teaching Digital Circuit experimental system |
| CN106843080A (en) * | 2017-03-29 | 2017-06-13 | 杰创智能科技股份有限公司 | A kind of FPGA parallel arrays module and its computational methods |
| CN106843080B (en) * | 2017-03-29 | 2019-05-14 | 杰创智能科技股份有限公司 | A kind of FPGA parallel array module and its calculation method |
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| CF01 | Termination of patent right due to non-payment of annual fee |