CN1272906C - Pulse distance voltage converter and converting method thereof - Google Patents
Pulse distance voltage converter and converting method thereof Download PDFInfo
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- CN1272906C CN1272906C CN 03143197 CN03143197A CN1272906C CN 1272906 C CN1272906 C CN 1272906C CN 03143197 CN03143197 CN 03143197 CN 03143197 A CN03143197 A CN 03143197A CN 1272906 C CN1272906 C CN 1272906C
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Abstract
The present invention discloses a pulse interval voltage converter and a conversion method thereof. The pulse interval voltage converter comprises a clock generator, a counter, a latch, a digital-analog converter, a delay unit, a frequency adjuster and a current limiting protection unit. The delay unit, the frequency adjuster and the current limiting protection unit are added to the present invention correspondingly to the prior art. The delay unit can program the preset delay time in order to delay the return-to-zero occasion of the counter, so the reference line of the output voltage is adjusted. The frequency adjuster can adjust the clock generate frequency of the clock generator, so the resolution of the output voltage is adjusted. The current limiting protection unit can prevent external signals from entering the delay unit when the delay unit works, so the noise interference is avoided.
Description
Technical field
The invention relates to a kind of pulse spacing electric pressure converter (Pulse Interval to VoltageConverter, PIVC) and conversion method, particularly about a kind of pulse spacing electric pressure converter and conversion method thereof of programmable.
Background technology
The pulse spacing electric pressure converter is industry and the biomedical device of using always of going up, and it can be with the form performance of each pulse spacing with voltage.Shown in Fig. 1 (a), T1 to T6 is respectively the spacing of each pulse 11, and the voltage after its conversion is directly proportional with the spacing length of each pulse 11, that is: spacing is bigger, and its output voltage is bigger.In addition, according to different design forms, the pulse spacing electric pressure converter can simply be divided into analog and digital two kinds.
With reference to Fig. 1 (b), the digital type pulse principle of electric pressure converter at interval is to utilize a counter (counter) 13 to begin counting after accepting a pulse (pulse) 11, and the New count of laying equal stress on that when accepting next pulse 11, makes zero.This counter 13 must be sent to the count value of gained one latch (latch) 14 before making zero, and a digital-analog convertor (Digital to AnalogConverter, DAC) 15 can be converted to the count value in this representative pulse spacing one voltage signal.
Yet there is following problem in above-mentioned design:
(1) resolution for output voltage is not high:
Show that with 8 output voltage is an example since a pulse spacing be divided into 256 levels at most, and its with the difference at next pulse interval usually in 10%.That is to say and have only 26 levels to be used for distinguishing the difference in adjacent two pulse spacings in 256 levels approximately that so its bit service efficiency is low, the related resolution that voltage is shown can't improve.In other words as if, the method that improves resolution has only and adopts more counter, latch and the digital-analog convertor of higher bit position, but this measure will increase considerably cost.
(2) be subject to disturb:
Occur between two normal burst as a noise, this noise also can be taken as a pulse, and this counter 13 can make zero in advance, and significantly reduces the count value of these latch 14 gained.With reference to Fig. 1 (c), if a noise 16 occurs between the two normal pulses 11, the count value that this counter 13 is sent to latch 14 will significantly reduce, however the output of the voltage of normal burst 11 will be the voltage of this noise 16 several times of exporting.
Because conventional method has above-mentioned resolution problem low and that be subject to disturb to exist, so improvement design has its necessity.
Summary of the invention
The pulse spacing electric pressure converter and the conversion method thereof that the purpose of this invention is to provide a programmable postpone to calculate this two interpulse clock number and adjust the voltage output resolution ratio in order to default, so that adjust according to different needs.In addition, pulse spacing electric pressure converter of the present invention and conversion method thereof can be ignored pulse signal in time of delay, to avoid the short period The noise.
Pulse spacing electric pressure converter of the present invention comprises a clock generator (clock generator), a counter, a latch, a digital-analog convertor and delay (delay) unit.This clock generator is used to produce clock (clock) signal, and this clock signal is provided to counter and delay cell.This counter is used to calculate clock signal and gets a count value at two interpulse clock numbers, and can receive the rz signal that this delay cell produces, and makes zero to reset.This latch is used to receive and pin the instantaneous count value of this counter.This digital-analog convertor is the analog signal that is used for the count value that latch pins is converted to a voltage.This delay cell is used for delay counter and calculates this two interpulse clock number, uses the datum line of adjusting its output voltage.
Pulse spacing voltage conversion method of the present invention comprises step (a) to (d).Step (a) is for postponing an input pulse signal.Step (b) is for calculating the time between this input pulse signal and the previous input pulse signal.Step (c) is for to be converted to a digital voltage value with this time.Step (d) is for to be converted to an analog voltage with this digital voltage value.
In addition, this pulse spacing electric pressure converter can comprise a frequency adjuster and a current-limiting protection (underflow protection) unit in addition.This frequency adjuster can be a frequency divider (frequencydivider) or a frequency multiplier (frequency multiplier), the resolution of this frequency adjuster adjustable output voltage.This current-limiting protection unit can stop entering of outer signals when this delay cell work, to avoid interference of noise.
Description of drawings
The present invention will be illustrated according to accompanying drawing, wherein:
Fig. 1 (a) is the functional schematic of known pulse spacing electric pressure converter;
Fig. 1 (b) is the conversion schematic diagram of known pulse spacing electric pressure converter;
Fig. 1 (c) display noise is to the influence of known pulse spacing electric pressure converter;
Fig. 2 (a) is the main circuit calcspar of pulse spacing electric pressure converter of the present invention;
Fig. 2 (b) is the conversion schematic diagram of pulse spacing electric pressure converter of the present invention;
Fig. 2 (c) shows the function improvement of pulse spacing electric pressure converter of the present invention to Fig. 2 (e);
Fig. 3 (a) is the circuit block diagram of an embodiment of pulse spacing electric pressure converter of the present invention;
Fig. 3 (b) is to the local circuit of the circuit block diagram of Fig. 3 (g) displayed map 3 (a).
Embodiment
The present invention will be that example is carried out simple explanation with the pulse spacing electric pressure converter 20 shown in Fig. 2 (a) at first, in order to show technical characterictic of the present invention and advantage thereof.This pulse spacing electric pressure converter 20 comprises a counter 21, a latch 22, a digital-analog convertor 23, a delay cell 24, a frequency adjuster 25, a current-limiting protection unit 26 and a clock generator 27.Pulse 28 will be transferred to the voltage output signal of simulation by this digital-analog convertor 23 after importing via a delay cell 24 at last.This pulse spacing electric pressure converter 20 has increased this delay cell 24, frequency adjuster 25 and current-limiting protection unit 26 with respect to known technology.These delay cell 24 programmables are preset time of delay, to postpone the opportunity that this counter 21 makes zero.If Y clock of default delay, and each clock 28 delay back is respectively T1 to T6 apart from the time that produces next clock 28, its execution result is shown in Fig. 2 (b).When the Y value is bigger, it is littler relatively to equal T1 to T6, can adjust the datum line of output voltage by this, but still keeps the correlation of the output voltage of each pulse, shown in Fig. 2 (c).The resolution of these frequency adjuster 25 adjustable output voltages.Suppose that this frequency adjuster 25 is a frequency multiplier, can increase the clock generating frequency of this clock generator 27, cooperate aforementioned delay cell 24, increase resolution for output voltage by this, its result is shown in the thick line of Fig. 2 (d).On the contrary, if will reduce resolution, then this frequency adjuster 25 can adopt a frequency divider.Entering of prevention outer signals that this current-limiting protection unit 26 can be when 24 work of this delay cell (for example Y clock period in) is to avoid interference of noise.In the section, even this counter 21 receives pulse, still do not make zero at this moment, it is shown in Fig. 2 (e).
Below will illustrate the local circuit of the pulse spacing electric pressure converter of a practical application.Fig. 3 (a) shows the circuit block diagram of pulse spacing electric pressure converter 30 of the present invention, and Fig. 3 (b) shows the wherein local circuit of each square to Fig. 3 (g).This pulse spacing electric pressure converter 30 comprises one and adjusts 31, one synchronous (synchronization) unit 32, (conditioning) unit, a delay cell 33, a counter 34, a latch 35, a digital-analog convertor 36, a clock generator 37, an overflow protection (overflow protection) unit 38, a current-limiting protection unit 39 and a frequency adjuster 40.After this adjustment unit 31 is accepted pulse signal, will produce a triggering signal Trig, this triggering signal Trig carries out the phase place adjustment via this lock unit 32, thereby produces a synchronous triggering signal STrig.One rz signal Zero is produced by the delayed unit 33 of this synchronous triggering signal STrig, in order to this counter 34 is made zero.
The function of this adjustment unit 31 is for admitting the pulse signal of input, and this pulse signal is adjusted into the triggering signal Trig that is up between the minimum voltage, with the transistor that cooperates subsequent treatment to transistor logic (Transistor-Transistor Logic, TTL) specification, and transmit it to this lock unit 32.
Fig. 3 (b) is the partial circuit diagram of this adjustment unit 31, it mainly is by three operational amplifier (Operational Amplifier, OP) constitute, thereby form buffering (buffer) part 311, anti-phase (inversion) part 312 and amplitude adjustment (amplitude adjustment) part 313, wherein this anti-phase part 312 can utilize a switching switch (A or B) to substitute.
The function of this lock unit 32 is for to carry out the phase place adjustment with this triggering signal Trig, makes the clock synchronization of itself and this clock generator 37, and then produces synchronous triggering signal STrig.The width of this synchronous triggering signal STrig equals the cycle of this clock, and its rising and drop point all with this clock synchronization.Except that this lock unit 32, this clock generator 37 is gone back transmit clock signal and is given this delay cell 33 and counter 34.By the design of this lock unit 32, can increase the correctness of this counter 34 and 35 pairs of these triggering signals of latch Trig counting.The detailed circuit of this lock unit 32 is shown in Fig. 3 (c) below, and it is to constitute main body by two 7474 triggers (flip flop), and is aided with suitable gate, inverter and passive component.
The detailed circuit of this current-limiting protection unit 39 is shown in Fig. 3 (c) top, and its latch that mainly is made of 7402 NOR gate (NOR door) suitable element of arranging in pairs or groups forms.Produce before back and this Zero signal produce as yet at triggering signal STrig, promptly in this delay cell in 33 default time of delays, this lock unit 32 is no longer accepted other triggering signal Trig, with the interference of avoiding the short period noise to trigger.In addition, can utilize a LED (light-emitting diode) to light after the triggering signal Trig input accepting, as the indication of signal input.
With reference to Fig. 3 (d), this delay cell 33 can postpone this triggering signal STrig after the specific time and send this Zero signal, to delay the time that this counter 34 makes zero.The clock number that postpones can accurately be set by four digital dials 5,6,7,8.Two 40102 integrated circuit type counters (belonging to complementary metal oxide semiconductors (CMOS) series) provide 16 resolution, and with one 7402 NOR gate with both signal integrations, with output Zero signal.The digital input end of each 40102 integrated circuit type counter two digital dials 5,6 or 7,8 of all arranging in pairs or groups constitute man-machine interfaces, so that the sequencing of parameter is set.The visual demand of the consumption of this 40102 integrated circuit type counter increases and decreases, or changes binary 40103 into metric 40102.
Fig. 3 (e) shows the circuit structure of this counter 34, latch 35 and digital-analog convertor 36.This counter 34 mainly is made of one 4040 elements, and its function makes zero for the replacement of periodically accepting the Zero signal, and calculates interpulse clock number, and it is presented on the digital output end.Transmitted the count value that continues to increase will be frozen in this latch 35 after next synchronous triggering signal STrig produces output by this counter 34, this count value occurs to the clock number of this synchronous triggering signal STrig between taking place by a last Zero signal just.This latch 35 mainly is made up of one 74374 element.
35 of this counter 34 and latchs are provided with an overflow protection unit 38 in addition, and it is to be formed by two 7,402 one 7402 NOR gate of trigger collocation and the passive components that constitute.If a last Zero signal arrives the time of this synchronous triggering signal STrig and surpasses the figure place of setting, promptly produce spill over, and do not adopt this data.
This digital-analog convertor 36 can be aided with an amplifier and suitable passive component constitutes by a digital-analog convertor DAC0800, to produce direct current output (DC output) and alternating current output (AC output) simultaneously.The function of this digital-analog convertor 36 is converted into analog signal for the digital signal with these latch 35 outputs, with the final output as pulse spacing electric pressure converter of the present invention.The advantage of simulation output also can cooperate existing sunykatuib analysis system and register system except being easy to perusal, the more important thing is easy and other analog signal is analyzed synchronously.
With reference to Fig. 3 (f), this clock generator 37 is in order to producing the required clock signal of circuit of the present invention, and can adjust its cycle via the user.This clock generator 37 can be made of 1 MHz (MHz) quartz crystal and two 7404 inverters.This frequency adjuster 40 is a frequency divider in the present embodiment, and it mainly is to be made of two 40102 integrated circuits, and integrates its signal by one 7402 NOR gate and one 7404 inverter.The design of this frequency divider can reduce the frequency of clock generating, uses the resolution that reduces this voltage output.The parameter that this frequency divider will reduce is that the quantity that it also can optionally increase and decrease 40102 integrated circuits maybe can be changed to binary 40103 with metric 40102 by 1,2,3,4 inputs of four digital dials.
Fig. 3 (g) shows the power supply design of this pulse spacing electric pressure converter 30.In the present embodiment, these pulse spacing electric pressure converter 30 required power supplys comprise+5V ,+9V and-9V, wherein+5V is that digital circuit is required ,+9V with-9V then is that analog line is required.Should+circuit of 5V is made of with suitable passive component a LM7805 ,+9V and-9V then is aided with suitable passive component general+5V power source conversion by a MAU207 and obtains.
When practical application, pulse spacing electric pressure converter of the present invention can be with electrocardiosignal (electrocardiogram, ECG) simulation that is converted to heart beat cycle (R-R interval) is exported, be input ecg signal and export heart beat cycle, so that carry out the analysis of HRV (heart ratevariability).
In addition, pulse spacing electric pressure converter of the present invention also can be applicable to pulse width modulation (Pulse Wide Modulation, the PWM) reorganization of signal reduction.Noise in circuit tolerable part short period of the present invention and the macrocyclic pwm signal, and can get rid of the abnormal signal of all ultra-long periods and part super short period automatically for the input pwm signal, to reduce of the influence of unusual input signal for output stability.
Technology contents of the present invention and technical characterstic disclose as above, yet the personage who is familiar with this technology still may be based on teaching of the present invention and announcement and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by the present patent application claim.
Claims (12)
1. pulse spacing electric pressure converter, described pulse spacing electric pressure converter comprises: a counter, this counter is about to a counting value returns after receiving the input pulse signal; One latch, it is connected in this counter, in order to pin the count value of this counter before making zero; One digital-analog convertor, it is connected in this latch, is used for the count value of this latch is converted to an analog signal; With a clock generator, it is in order to clocking; It is characterized in that: described pulse spacing electric pressure converter comprises that also one is connected to the delay cell of described counter, in order to postpone described input pulse signal; One frequency adjuster, it is connected to described clock generator, is sent to this delay cell in order to the frequency of adjusting this clock generator signal and with this clock signal, thereby adjusts the resolution of this analog signal; With a current-limiting protection unit, it is connected in described delay cell, is used to make this delay cell no longer to receive other input pulse signal when postponing described pulse signal.
2. pulse spacing electric pressure converter according to claim 1 is characterized in that: described frequency adjuster is a frequency divider.
3. pulse spacing electric pressure converter according to claim 1 is characterized in that: it comprises a synchronous unit in addition, is used to make this an input pulse signal and a clock signal Synchronization.
4. pulse spacing electric pressure converter according to claim 3 is characterized in that: it comprises an overflow protection circuit in addition, abandons this count value when the count value of this counter surpasses a default value.
5. pulse spacing electric pressure converter according to claim 1 is characterized in that: it comprises an adjustment unit in addition, in order to this input pulse signal is adjusted into transistor to the transistor logic specification.
6. pulse spacing electric pressure converter according to claim 1 is characterized in that: described delay cell comprises two integrated circuit type counters and a NOR gate.
7. pulse spacing electric pressure converter according to claim 6 is characterized in that: described delay cell comprises four digital dials in addition, and two these digital dials of digital input end collocation of each integrated circuit type counter are to set.
8. pulse spacing electric pressure converter according to claim 2 is characterized in that: described frequency divider comprises two integrated circuit type counters, a NOR gate and an inverter.
9. pulse spacing electric pressure converter according to claim 8 is characterized in that: described frequency divider comprises four digital dials in addition to set.
10. pulse spacing voltage conversion method, it is characterized in that: described method comprises the following step:
(a) postpone an input pulse signal, and no longer accept other input pulse signals when postponing described pulse signal;
(b) calculate time between the input pulse signal after this input pulse signal and the previous delay;
(c) this time is converted to a digital voltage value;
(d) this digital voltage value is converted to an analog voltage;
(e) utilize the frequency of adjustment clock signal to adjust the resolution of described analog voltage.
11. pulse spacing voltage conversion method according to claim 10 is characterized in that: the Time Calculation in described step (b) is to the clock counting number between the input pulse signal after this input pulse signal and the previous delay.
12. pulse spacing voltage conversion method according to claim 10 is characterized in that: it comprises the step that reduces a clock signal frequency in addition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03143197 CN1272906C (en) | 2003-06-06 | 2003-06-06 | Pulse distance voltage converter and converting method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03143197 CN1272906C (en) | 2003-06-06 | 2003-06-06 | Pulse distance voltage converter and converting method thereof |
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| CN1553571A CN1553571A (en) | 2004-12-08 |
| CN1272906C true CN1272906C (en) | 2006-08-30 |
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| CN 03143197 Expired - Fee Related CN1272906C (en) | 2003-06-06 | 2003-06-06 | Pulse distance voltage converter and converting method thereof |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127529B (en) * | 2006-08-18 | 2010-05-12 | 智原科技股份有限公司 | Digital/analog converter and phase locking loop built-in self test circuit and its measurement method |
| GB2470591A (en) * | 2009-05-29 | 2010-12-01 | Powervation Ltd | Pulse width modulation synchronisation of switched mode power converters |
| CN102664608B (en) * | 2010-12-28 | 2015-03-11 | 博通集成电路（上海）有限公司 | Frequency multiplier and frequency multiplication method |
| CN102938635A (en) * | 2012-11-08 | 2013-02-20 | 华为技术有限公司 | Frequency multiplication circuit |
| CN104185267B (en) * | 2013-05-27 | 2019-03-08 | 联想(北京)有限公司 | Method and apparatus for determining the frequency of the reference clock of electronic equipment |
| CN106777437B (en) * | 2015-11-24 | 2020-05-19 | 龙芯中科技术有限公司 | Clock system construction method and device and clock system |
| CN117200762B (en) * | 2022-05-31 | 2024-02-27 | 湖南毂梁微电子有限公司 | Digital pulse measuring and converting circuit and method |
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