CN101394703B - Time clock recovery system and method - Google Patents
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- CN101394703B CN101394703B CN2008102245205A CN200810224520A CN101394703B CN 101394703 B CN101394703 B CN 101394703B CN 2008102245205 A CN2008102245205 A CN 2008102245205A CN 200810224520 A CN200810224520 A CN 200810224520A CN 101394703 B CN101394703 B CN 101394703B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The invention discloses a clock recovery system and a clock recovery method. The clock recovery system comprises a local clock module, and a clock signal extraction module. The local clock module is used for providing a clock signal for the clock signal extraction module. The clock signal extraction module comprises a counter (1), a counter (2), a divider (1), a divider (2) and a clock output unit. The clock recovery system recovers the clock signal in a cascade serial input data by extracting the clock signal of the cascade input data. The recovered clock signal has the advantages of high accuracy and low error rate.
Description
Technical field
The present invention relates to a kind of clock recovery system and method, in particular a kind of clock recovery system and method for controlling the single wire transmission scheme for cascade.
Background technology
Along with being widely used of LED, adopt LED emission three primary colors to be manufactured in a large number with the LED display unit that forms image according to pixel, and for the message panel in sports ground, side of buildings, railway station or billboard.
The LED display unit mainly comprises control circuit and some LED.At the LED control field, mainly exist 3 kinds of schemes for cascade control signal transmission in system such as monobus parallel transmission structure, multi-thread (as two lines, four lines) serial transmission structure and single-wire serial transmission structure.
Be illustrated in figure 1 single-wire serial transmission scheme schematic diagram, shown in figure, in system, between each light fixture, adopt single holding wire to be connected, the control signal of light fixture is sent by the controller of left end, and the light fixture 1 of transmission process successively is to light fixture n from left to right.This cascade system is integrated on a cascade transmission line by clock signal and data-signal, with respect to monobus parallel transmission structure and multi-thread serial transmission structure, under the prerequisite that has guaranteed system cascade performance, reduced the cost that system complexity and system realize.
In the middle of such system, the control device of every one-level light fixture need to carry out recovering clock signals to serial input signals, to obtain the sampled value of lamp point control signal, thereby carries out the control that lamp point shows; On the other hand, system also will be rebuild by the form identical with input signal the cascade serial data at output, thereby generates the directly link data, and therefore, control device also needs serial input signals is carried out the recovery of data reconstruction clock.
In the middle of existing technical scheme, a kind of method is to adopt fixing cascade serial data bit wide; get the frequency values of a certain frequency division value of local clock frequency as cascade signal; and in fixed position, use this clock signal to the cascade data value of being sampled, with the generation that realizes display control signal and the reconstruction of output signal; Another kind method is that the length of the Cycle Length of cascade serial signal and every 1 bit data low and high level is made to circumscription, and in relevant position, use the local clock signal to the cascade signal value of sampling, when the length of cycle of cascade data or high and low level surpasses above-mentioned scope, be considered as invalid signals.
Therefore existing clock recovery method proposes strict requirement to the cascade serial signal cycle in whole cascade chain, the antijamming capability that increased the difficulty that system is controlled, has reduced system; On the other hand, if strengthen the antijamming capability of system, must increase the Cycle Length of cascade signal, and this can reduce the cascade transmission rate, thereby reduce the display performance of system.
Therefore, there is defect in prior art, needs further improvement.
Summary of the invention
Technical problem to be solved by this invention is for the deficiencies in the prior art, to provide a kind of clock recovery system and method, especially clock recovery system and the method for LED control system single-wire serial transmission scheme
Technical scheme of the present invention is as follows:
A kind of clock recovery system wherein, comprising: local clock module, clock signal extraction module; Described local clock module is for providing the local clock signal to described clock signal extraction module; Described clock signal extraction module comprises:
The clock output unit, for when described ratio is default value, the corresponding output time at each default value, export each and pre-set clock signal, wherein, the output time that each adjacent default value is corresponding, at least two local clock cycles of space.
Described clock recovery system, wherein, described clock output unit arranges judgment sub-unit, for judging when described divider 2 is output as the first default value, the second default value, the 3rd default value, export respectively the high level of the first clock signal, second clock signal, the 3rd clock signal, the duration of each high level is a local clock cycle.
A kind of clock recovery method, wherein, the method includes the steps of:
A1, transmission local clock signal;
A2, the local clock number that default figure place input signal accumulative total is comprised are counted, and obtain the first count results;
A3, the local clock number that every input signal is comprised are counted, and obtain the second count results;
A4, calculate in described default figure place input signal, the local clock number that average every input signal comprises, obtain the 3rd count results;
A5, calculate the ratio of described the second count results and described the 3rd count results;
A6, when described ratio is default value, the corresponding output time at each default value, export each and pre-set clock signal, wherein, the output time that each adjacent default value is corresponding, at least two local clock cycles of space.
Described clock recovery method, wherein, in steps A 2, A3, every pulse signal that input signal is a complete cycle.
Described clock recovery method, wherein, in steps A 2, A3, described input signal is set to: the longer signal of the high level time of take is logical one, the shorter signal of high level time is logical zero, and wherein the high level time of logical one is than at least large two local clock cycles of the high level time of logical zero.
Described clock recovery method, wherein, in steps A 6, the output time that each adjacent default value is corresponding, two local clock cycles of space.
Described clock recovery method, wherein, in steps A 6, when described ratio is the first default value, the second default value, the 3rd default value, the corresponding output time at each default value, export respectively the first clock signal, second clock signal, the 3rd clock signal.
Described clock recovery method, wherein, when exporting respectively the first clock signal, second clock signal, the 3rd clock signal, carry out following steps: export respectively the high level of the first clock signal, second clock signal, the 3rd clock signal, the duration of each high level is a local clock cycle.
Described clock recovery method, wherein, described the first default value, described the second default value, described the 3rd default value are respectively 1/2nd, 1/4th, 3/4ths.
Described clock recovery method, wherein, described the first default value, described the second default value, described the 3rd default value are respectively 5/8ths, 3/8ths, one.
Adopt such scheme, by extracting the clock signal of cascade input data, directly in the cascade serial input data, recover clock signal, increased the flexibility that system realizes, improved the cascade performance.
The accompanying drawing explanation
Fig. 1 is the single wire transmission scheme schematic diagram of prior art;
The agreement method that Fig. 2 is every 1 signal of serial data in the present invention;
Fig. 3 is the structural representation of clock recovery system of the present invention;
Fig. 4 is the waveform sequential chart of a preferred embodiment of the present invention;
Fig. 5 is the waveform sequential chart of a preferred embodiment of the present invention;
Fig. 6 is the waveform sequential chart of a preferred embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
As shown in Figure 3, the invention provides a kind of clock recovery system, this system has comprised local clock module and clock signal extraction module, the local clock module provides the local clock signal for the clock signal extraction module, the clock signal extraction module has comprised counter 1, counter 2, divider 1, divider 2 and clock output unit, wherein, the local clock number of cycles that 1 pair of continuous n position cascade serial input signals sin accumulative total of counter comprises is counted, obtain the first count results time_last, and time_last is sent to divider 1, wherein the value of n is by systemic presupposition, divider 1 obtains the second count results time_last_ave by the value of time_last divided by n, and time_last_ave is sent to divider 2, the local clock number that counter 2 comprises each serial input signals sin is counted to get count results cnt, and cnt is sent to divider 2, divider 2 draws the two ratio clk_choose according to cnt and the time_last_ave of input, send to the clock output unit, the clock output unit is according to different clk_choose values, during the numerical value that is systemic presupposition at clk_choose, at the corresponding output time of this default value, export different clock signals.The value of clk_choose is crucial to realization of the present invention in the present invention, value for clk_choose need to satisfied primary condition be, three time intervals of clk_choose value in the scope of a signal period are at least the twice in local clock cycle, also within a signal period, choose three time points, at least 2 local clock cycles of interval in twos between each point, could extract discriminatively three different clock signals like this, for the cascade serial data of single wire transmission scheme, rebuild output.
Such as equaling two/for the moment in the value of clk_choose, in the moment of divider 2 outputs 1/2nd, the clock output unit is exported the first clock signal d_sync; Value at clk_choose equals four/for the moment, in the moment of divider 2 outputs 1/4th, and clock output unit output second clock signal d0_sync; Value at clk_choose equals at 3/4ths o'clock, and in the moment of divider 2 outputs 3/4ths, the clock output unit is exported the 3rd clock signal d1_sync, completes the process of clock recovery.
Certainly, the invention is not restricted to only recover three clock signals, in the situation that needs, utilize the invention thought of said system, can recover equally four, five even clock signals that need more.
The value of time_last and time_last_ave in said system, be adopt before in the input signal in multibit signal cycle, sum and the mean value thereof of contained local clock clk number; For example, adopt sum and the mean value thereof of the contained local clock clk of the input signal number of at least 2 signal periods, but not the contained local clock clk of the input signal of 1 signal period number before, such way can be avoided larger skew occurring because input signal sin sudden change causes clock signal d_sync, d0_sync, d1_sync extracting position, thereby mistake appears in the module that makes back utilize above-mentioned three clock signals to carry out data signal samples.
The invention provides a kind of clock recovery method, the method includes the steps of: the local clock module provides to the clock signal extraction module local clock signal that frequency is consistent; Counter 1 uses the local clock signal, system is preset to the local clock number that fixedly the cascade input signal accumulative total of figure place comprises and counted, and obtains the first count results time_last; The local clock number that counter 2 uses the local clock signal to comprise every input signal is counted, and obtains the second count results; Divider 1 calculates in described default fixedly figure place input signal according to the first count results, and the local clock number that average every input signal comprises, obtain the 3rd count results time_last_ave; Divider 2 calculates the ratio clk_choose of described the second count results and described the 3rd count results.
Then, when described ratio is the first default value, the clock output unit is exported the first clock signal; When described ratio is the second default value, clock output unit output second clock signal; When described ratio is the 3rd default value, clock output unit output the 3rd clock signal; Wherein, the output time of described the first default value, the second default value, the 3rd default value, at least two local clock cycles of interval in twos.The high level that like this, can guarantee each clock signal of extracting can not coincide together.
The sequential chart of a kind of embodiment of the method as shown in Figure 4, in this sequential chart, the high level time of logical one is 5 local clock cycles, the high level time of logical zero is 2 local clock cycles, the high level time of logical one is than large 3 local clock cycles of the high level time of logical zero, the statistics figure place of systemic presupposition is 16, being default is counted the local clock number that input signal added up to comprise of 16 before the 2nd input signal shown in Fig. 4, the first count results is 128 in this example, using 128 in divider 1, to obtain average bits per inch divided by 16 be 8 according to the local clock number time_last_ave comprised, the ratio of divider 2 output the second count results and the 3rd count results, the clock output unit is two/for the moment at divider 2 output ratio clk_choose, export the high level of the first clock signal d_sync signal, at clk_choose, be four/for the moment, the high level of output second clock signal d0_sync signal, at clk_choose, it is 3/4ths o'clock, export the high level of the 3rd clock signal d1_sync signal.
As shown in Figure 4,1/4th, 1/2nd, 3/4ths mutually between, interval two local clock cycles.
And above-mentioned 3 high level are all reduced to low level at 1 local clock after the signal period.When the clock output unit is other numerical value at divider 2 output ratio clk_choose, keep the low level of clock signal constant.Make in this way, directly from the cascade signal of input, extract clock signal, do not need to limit the pulsewidth scope of input signal, realized the requirement on flexibility of system.
As a kind of signal agreement method, on the basis of embodiment 2, as shown in Figure 2, the cascade input signal is used the pulse signal of a complete cycle as 1, in the middle of a data, has comprised high level and low level.Like this, be conducive to improve the accuracy that clock signal is extracted.
As a kind of signal agreement method, on the basis of embodiment 2, the cascade input signal can recently be distinguished by different duties logical zero and the logical one of every 1 signal, and the high level time of logical one is greater than at least two local clock cycles of high level time of logical zero.As shown in Figure 5, it is the waveform sequential chart of the preferred embodiment, in this embodiment, the high level time of logical one is 6 local clock cycles, the high level time of logical zero is 2.5 local clock cycles, the high level time of logical one is than large 3.5 local clock cycles of logical zero high level time, average every the local clock number time_last_ave comprised of input signal that illustrates before the 2nd input signal 16 is 8, the clock output unit is two/for the moment at clk_choose, export the high level of the first clock signal d_sync, at clk_choose, be four/for the moment, the high level of output second clock signal d0_sync, at clk_choose, it is 3/4ths o'clock, export the high level of the 3rd clock signal d1_sync, above-mentioned 3 high level are all reduced to low level at 1 local clock after the cycle.
Again as shown in Figure 6, the high level time of logical one is 9 local clock cycles, the high level time of logical zero is 5 local clock cycles, the high level time of logical one is than large 4 local clock cycles of the high level time of logical zero, before the 2nd input signal of diagram, 10 continuous clock numbers that signal added up to comprise are counted, count results is 150, average every the local clock number time_last_ave comprised of these 10 input signals is 15, the clock output unit is 7/15ths o'clock at clk_choose, export the high level of the first clock signal d_sync, at clk_choose, it is 3/15ths o'clock, the high level of output second clock signal d0_sync, at clk_choose, it is 10/15ths o'clock, export the high level of the 3rd clock signal d1_sync, above-mentioned 3 high level are all reduced to low level at 1 local clock after the cycle.Recover equally accurately three clock signals in the situation that every cascade signal high level differs 4 local clocks like this, reached the invention effect of expection.
In embodiment 2 to 4, the clock output unit, the method of clock signal can be: when three default values of divider 2 outputs, export respectively the high level of three clock signals, the high level time of this clock signal is fallen after the time equated with the local clock cycle, and the duration of each high level is a local clock cycle.Can avoid like this at three default value output time intervals hour, extract three clock signal high level close together and even coincide together, thereby affect follow-up data, rebuild and export.
On the basis of embodiment 5, preferably the first default value in divider 2 outputs is two/for the moment, exports the high level of the first clock signal; At the second default value, be four/for the moment, the high level of output second clock signal; Be 3/4ths o'clock at the 3rd default value, export the high level of the 3rd clock signal, above-mentioned each high level will be low level after a clock cycle.In this case, between the output time of three default values, in two local clock cycles of interval, can extract like clockwork three clock signals.
The the first clock signal d_sync signal obtained by technical solution of the present invention is for sampling and obtain the sampled value of this signal every 1 Bits Serial input signal sin; Second clock signal d0_sync signal descends constantly for the high level of determining logical zero when rebuilding output signal, and the 3rd clock signal d1_sync descends constantly for the high level of determining logical one when rebuilding output signal.
Should be understood that; for those of ordinary skills; can be improved according to the above description or be converted; such as those skilled in the art, under instruction of the present invention, also can select the first default value, the second default value and the 3rd default value to be respectively 5/8ths, 3/8ths, one; can also select 7/16ths, 3/16ths, 10/16ths etc. values; for such conversion, all should fall into claim protection range of the present invention.
Claims (9)
1. a clock recovery system, is characterized in that, comprising: local clock module, clock signal extraction module;
Described local clock module is for providing the local clock signal to described clock signal extraction module;
Described clock signal extraction module comprises:
Counter 1, counted for the local clock number that default figure place input signal accumulative total is comprised, and obtains the first count results, sends to divider 1;
Counter 2, counted for the local clock number that every input signal is comprised, and obtains the second count results, sends to divider 2;
Divider 1, for calculating described default figure place input signal, the local clock number that average every input signal comprises, obtain the 3rd count results, sends to divider 2;
Divider 2, for calculating the ratio of described the second count results and described the 3rd count results, export to the clock output unit;
The clock output unit, for when described ratio is default value, the corresponding output time at each default value, export each and pre-set clock signal, wherein, the output time that each adjacent default value is corresponding, at least two local clock cycles of space; Described default value is for to choose three time points within a signal period, at least 2 local clock cycles of interval in twos between each point.
2. clock recovery system according to claim 1, it is characterized in that, described clock output unit arranges judgment sub-unit, for judging when described divider 2 is output as the first default value, the second default value, the 3rd default value, export respectively the high level of the first clock signal, second clock signal, the 3rd clock signal, the duration of each high level is a local clock cycle.
3. a clock recovery method, is characterized in that, the method includes the steps of:
A1, transmission local clock signal;
A2, the local clock number that default figure place input signal accumulative total is comprised are counted, and obtain the first count results;
A3, the local clock number that every input signal is comprised are counted, and obtain the second count results;
A4, calculate in described default figure place input signal, the local clock number that average every input signal comprises, obtain the 3rd count results;
A5, calculate the ratio of described the second count results and described the 3rd count results;
A6, when described ratio is default value, the corresponding output time at each default value, export each and pre-set clock signal, wherein, the output time that each adjacent default value is corresponding, at least two local clock cycles of space; Described default value is for to choose three time points within a signal period, at least 2 local clock cycles of interval in twos between each point.
4. clock recovery method according to claim 3, is characterized in that, in steps A 2, A3, and every pulse signal that input signal is a complete cycle.
5. clock recovery method according to claim 3, it is characterized in that, in steps A 2, A3, described input signal is set to: the longer signal of the high level time of take is logical one, the shorter signal of high level time is logical zero, and wherein the high level time of logical one is than at least large two local clock cycles of the high level time of logical zero.
6. according to the arbitrary described clock recovery method of claim 3 to 5, it is characterized in that, in steps A 6, when described ratio is the first default value, the second default value, the 3rd default value, the corresponding output time at each default value, export respectively the first clock signal, second clock signal, the 3rd clock signal.
7. clock recovery method according to claim 6, it is characterized in that, when exporting respectively the first clock signal, second clock signal, the 3rd clock signal, carry out following steps: export respectively the high level of the first clock signal, second clock signal, the 3rd clock signal, the duration of each high level is a local clock cycle.
8. clock recovery method according to claim 6, is characterized in that, described the first default value, described the second default value, described the 3rd default value are respectively 1/2nd, 1/4th, 3/4ths.
9. clock recovery method according to claim 6, is characterized in that, described the first default value, described the second default value, described the 3rd default value are respectively 5/8ths, 3/8ths, 1/8th.
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| CN102540152A (en) * | 2011-11-25 | 2012-07-04 | 中国船舶重工集团公司第七二四研究所 | Method for improving capacity resistant to strong interference of radar transmitter for MAX 7219 |
| US11341904B2 (en) | 2019-08-13 | 2022-05-24 | Novatek Microelectronics Corp. | Light-emitting diode driving apparatus and light-emitting diode driver |
| US20210049952A1 (en) * | 2019-08-13 | 2021-02-18 | Novatek Microelectronics Corp. | Light-emitting diode driving apparatus |
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| WO1996021296A1 (en) * | 1994-12-29 | 1996-07-11 | Alcatel Standard Electrica S.A. | Data recovery circuit |
| CN1870491A (en) * | 2005-05-24 | 2006-11-29 | 深圳市木青科技实业有限公司 | Clock recovery technology using of far-end measuring near-end recovery simulation packet circuit |
| CN101005277A (en) * | 2005-10-06 | 2007-07-25 | 飞思卡尔半导体公司 | Digital clock frequency multiplier |
| CN101227617A (en) * | 2008-01-31 | 2008-07-23 | 北京卫星信息工程研究所 | System clock recovery apparatus |
| CN201323566Y (en) * | 2008-10-17 | 2009-10-07 | 北京巨数数字技术开发有限公司 | Clock recovering system |
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- 2008-10-17 CN CN2008102245205A patent/CN101394703B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996021296A1 (en) * | 1994-12-29 | 1996-07-11 | Alcatel Standard Electrica S.A. | Data recovery circuit |
| CN1870491A (en) * | 2005-05-24 | 2006-11-29 | 深圳市木青科技实业有限公司 | Clock recovery technology using of far-end measuring near-end recovery simulation packet circuit |
| CN101005277A (en) * | 2005-10-06 | 2007-07-25 | 飞思卡尔半导体公司 | Digital clock frequency multiplier |
| CN101227617A (en) * | 2008-01-31 | 2008-07-23 | 北京卫星信息工程研究所 | System clock recovery apparatus |
| CN201323566Y (en) * | 2008-10-17 | 2009-10-07 | 北京巨数数字技术开发有限公司 | Clock recovering system |
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