CN1870491A - Clock recovery technology using of far-end measuring near-end recovery simulation packet circuit - Google Patents

Clock recovery technology using of far-end measuring near-end recovery simulation packet circuit Download PDF

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CN1870491A
CN1870491A CN 200510071089 CN200510071089A CN1870491A CN 1870491 A CN1870491 A CN 1870491A CN 200510071089 CN200510071089 CN 200510071089 CN 200510071089 A CN200510071089 A CN 200510071089A CN 1870491 A CN1870491 A CN 1870491A
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clock
packet
circuit emulation
end
recovery
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CN 200510071089
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Chinese (zh)
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胡继超
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深圳市木青科技实业有限公司
胡继超
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Abstract

This invention discloses a clock resuming technology, which picks up clock information parameter of the E1 clock information with a difference resuming method by a far end primary circuit emulation device and utilizes the clock information parameter to resume the information from the emulator at the near end to reach accurate synchronization. After the device is turned on, a clock with the central frequency of a is initializes to a VCO, then a CLK samples a low frequency clock of the clock source to generate a counting value b, then the CLK samples the clock generated by the VCO to generate a counting value c to be checked with a difference mode to get a clock parameter (b-c) to be checked to get a clock of al=(b-c)+a to be stored in a data packet and sent to the receiving end by the IP network.

Description

分组电路仿真的远端测量近端恢复时钟技术 A distal measurement packet clock recovery circuit emulation technology proximal end

技术领域 FIELD

本发明涉及一种时钟恢复技术,尤其是一种分组电路仿真的远端测量近端恢复时钟技术。 The present invention relates to a clock recovery technique, particularly the distal end A packet measurement circuit emulation clock recovery techniques proximal end.

背景技术 Background technique

E1信号源自PCM编码时分复用技术,以2048kbps恒定速率传送信息,分组网络则采用统计复用技术,其传输和交换基于数据包。 E1 signals from PCM coding division multiplexing technology to transmit information 2048kbps constant rate, packet networks statistical multiplexing is used, which is based on packet transmission and switching. 时分复用技术具有带宽固定,传输时延小而稳定,信号定时透明度高,抖动、漂移小等特点,适合于话音、图像等对传输实时性和定时稳定性要求高的应用。 Time division multiplexing techniques have a fixed bandwidth, transmission delay small and stable, high transparency signal timing, jitter, drift, etc., suitable for voice, images and real-time transmission timing of applications requiring high stability. 基于数据包的统计反馈技术具有更高的复用效率,适合于对时延要求不严格、通常不需要准确恢复定时信息的数据传输场合,如一些基于包的传输、异步传输。 Feedback technique based on statistical data packet has a higher multiplexing efficiency, suitable for the delay is not critical, it is generally not required where accurate recovery of data transmission timing information, such as the number of packet-based transmission, asynchronous transmission.

在任何通过分组实现电路交换的技术中,最关键的问题之一就是时钟恢复。 In any circuit-switched technology through a packet, one of the most critical issues is the clock recovery. 时钟稳定性包括时钟抖动、漂移和频率保持特性。 Clock stability includes a clock jitter, frequency drift and retention characteristics. 抖动会引起E1终端设备产生误码,漂移会导致滑帧和其它类型的业务损伤,时钟频率的跳变则会导致帧失步和重新捕捉,表现为严重的误码。 Jitter can cause bit errors E1 terminal, drift can cause the slide frame and damage other types of traffic, the clock frequency hopping will result in recapturing and LOF, it showed severe errors. 例如,在两个客户端之间使用专用租借线路通过运营商分组网络上的仿真链路进行连接,则客户TDM业务的频率必须在分组网络的出口处精确地重新生成。 For example, the use of a dedicated leased line between two clients connected by links on the simulation operator packet network, the TDM service frequency customer must regenerate exactly at the outlet of the packet network. 长时间的频率不匹配将导致分组网络出口处形成等待队列,如果重新生成的时钟比原时钟慢,则缓冲器被填满,反之则会被清空。 Time frequency mismatch will result in a packet network egress queue is formed, if the re-generated clock slower than the original clock, then the buffer is full, otherwise it will be cleared. 这两种情况都会造成数据丢失和服务质量下降。 Both situations can cause data loss and reduced quality of service.

目前比较多的电路仿真设备厂家同步技术基于数据包统计负反馈技术计算分组到达速率推断时钟信息。 Currently more statistical negative feedback circuit emulation equipment manufacturers synchronization packet is calculated based on packet arrival rate estimation clock information. 如图1所示,计数器周期统计发送的数据速率和接收数据的速率,当发送数据速率大于接收数据速率,计数器通过控制压控振荡器(VCO)减小数据发送速率,反之增大数据发送速率。 1, the data rate of the received data and statistics counter cycle rate transmission, when the transmission data rate is greater than the received data rate, the data transmission rate by reducing the counter controlled oscillator (the VCO), and vice versa to increase the data transmission rate . 使发送出去的速率与接受的速率一致,来达到时钟同步。 So that a rate consistent with the acceptance sent out rate to achieve clock synchronization. 这种方案的劣势主要是网络上传输时数据包会丢失,数据包在通过网络传输的过程中被破坏,数据包由于网络拥塞(网络节点的队列已满)而被丢弃,数据包由于网络的故障而丢失;计数器是按周期统计的,分组网络数据包是突发性的,到达时间有快有慢这种同步方式时钟是不很精确的,会产生时钟振荡和收敛时间长的问题,误码,漂移不可避免。 The main disadvantage of this solution is the transmission of data packets will be lost on the network, the data packets during transmission through the network is destroyed, data packets due to network congestion (queue is full network node) is discarded, because the packet network fault lost; is counter statistics periodically, the packet network packet is bursty, the time of arrival of this fast or slow clock synchronization method is not very accurate, will produce long convergence time and the clock oscillation problems, bad code drift is inevitable.

发明内容 SUMMARY

本发明公开了一种能有效克服上述不足的时钟恢复技术,它有效的克服了网络延时随机性和丢包的影响。 The present invention discloses a method can effectively overcome the deficiencies of the above-described clock recovery technology, which effectively overcomes the influence of network delay and packet loss of randomness.

本发明是通过以下方法达到上述发明目的的:它在主电路仿真设备中对时钟源时钟(接收数据的时钟)进行采样,提取出时钟参数,封装在数据包内,在从电路仿真设备中依据这个时钟参数恢复出原始时钟,从而避免网络延时随机性和丢包的影响。 The present invention is to achieve the above object by the following method: It sampling clock source clock (clock for received data) in the main circuit emulation devices, the extracted clock parameters, encapsulated within a data packet, in accordance with the circuit emulation device the clock parameters to recover the original clock, thus avoiding the impact of network latency and packet loss of randomness.

上述方法中,主电路仿真设备端用差分恢复的方法对时钟源的时钟进行采样,提取出时钟参数。 In the above method, the simulation device side main circuit of the clock recovery method of differential clock source sampling clock parameters are extracted.

上述方法中,在设备上电后对压控振荡器(VCO)先初始化一个中心频率为a的时钟,在主电路仿真设备中本地高频时钟CLK来采样时钟源(即接收数据的时钟)低频时钟,产生一个计数值b,再本地高频时钟CLK采样压控振荡器产生的时钟,产生一个计数值c,用差分的方式来进行校验,得到的时钟参数即为(bc),校验后得到的时钟a1=(bc)+a,,将此时钟信号封装在数据包内,通过IP网络发送到接收端。 In the above method, the device is powered on to a voltage controlled oscillator (VCO) initialize a center frequency of a clock, in the main circuit emulation device to sample the local high frequency clock CLK frequency clock source (i.e., receive data clock) clock, generates a count value B, then the local clock frequency sampling clock CLK generated by the voltage controlled oscillator, generates a count value of c, and a differential approach to verify, obtained is the clock parameters (BC), check clock obtained after a1 = (bc) + a ,, this clock signal is encapsulated within a packet transmitted to the receiving side through IP network.

上述方法中,从电路仿真设备接收到上述的时钟测量值,根据这个时钟测量值,通过D/A转换来驱动压控振荡器(VCO),从而恢复出主设备端时钟源的时钟。 In the above method, circuit simulation apparatus is received from the clock to said measured values, the measured values ​​in accordance with this clock to drive a voltage controlled oscillator (VCO) by D / A conversion, thereby recovering the clock of the master clock source terminal.

上述方法中,主、从两个电路仿真设备组成的网络是双向通信的。 In the above-described method, the master, two circuit emulation devices from the network is composed of two-way communication.

附图说明 BRIEF DESCRIPTION

下面结合附图详述本发明的具体方法图1是现有的电路仿真设备采用的时钟恢复技术数据包统计负反馈技术原理图图2是本发明分组电路仿真的远端测量近端恢复时钟技术主从设备连接示意图图3是本发明分组电路仿真的远端测量近端恢复时钟技术主设备提取时钟参数原理图图4是本发明分组电路仿真的远端测量近端恢复时钟技术从设备恢复时钟原理图具体实施方式如图2所示,本实施例包含有E1信号源和E1受信端,主、从两个电路仿真设备,E1信号源和E1受信端在两端,E1信号源和E1受信端均连接一个电路仿真设备。 Detailed Description of the specific method of the present invention below with reference to FIG. 1 is a conventional clock recovery circuit emulation equipment using statistical techniques packets negative feedback FIG. 2 is a schematic diagram of a circuit according to the present invention, the distal end of the packet measuring a proximal simulation clock recovery technique from the master device connected to the distal end 3 is a schematic diagram of the inventive circuit emulation packet proximal measuring recovered clock parameters extracted clock master art schematic circuit of FIG. 4 of the present invention is a simulation of the distal end of the packet measuring a proximal recovered clock from the clock recovery device technology DETAILED DESCRIPTION schematic diagram shown in Figure 2, the present embodiment comprises a signal source E1 and E1 trusted end, the main, from two circuit emulation devices, the signal E1 and E1 trusted source of both ends, the signal sources E1 and E1 trusted in terminal devices are connected to a circuit simulation. 两个电路仿真设备通过IP网络连接,与E1信号源的相连的电路仿真设备是主电路仿真设备,与受信端相连的电路仿真设备是从电路仿真设备,在电路仿真设备中包含压控振荡器(VCO)。 Two circuit emulation devices are connected via an IP network, connected to the circuit emulation device is the primary signal source E1 circuit emulation devices, circuit simulation device connected with the reception terminal from the circuit simulation apparatus comprising a voltage controlled oscillator in the circuit emulation device (VCO).

其中,E1信号源发送E1码流到主电路仿真设备,主电路仿真设备对时钟源时钟用差分恢复的方法来采样,提取出时钟参数,把这个时钟参数封装在数据包内,数据包通过IP网络传送到另一端的从电路仿真设备,从电路仿真设备接收到数据包,根据这个时钟参数,恢复出时钟信息,将数据传送到这一端受信端设备。 Wherein, E1 E1 transmission source code of the main flow circuit emulation devices, the master device sampling circuit simulation method using the differential clock source clock recovery, clock parameter extraction, the clock parameters encapsulated within the packet, the IP packet from the network to the other end of the circuit simulation apparatus is received from the device to the circuit emulation data packet, in accordance with the clock parameters, the recovered clock information, transmits data to the terminal end of the trusted device. 在主电路仿真设备中对时钟源的时钟进行采样,提取出时钟参数,在从电路仿真设备中依据这个时钟参数恢复出时钟。 In the main circuit emulation device clock source sampling clock, the clock parameters are extracted, clock recovery parameters based on the clock from the circuit emulation device.

在如图3所示的主电路仿真设备中,在设备上电后对压控振荡器(VCO)先初始化一个中心频率为a的时钟,在主电路仿真设备中本地高频时钟CLK来采样时钟源(即接收数据的时钟)低频时钟,产生一个计数值b,再本地高频时钟CLK采样压控振荡器产生的时钟,产生一个计数值c,用差分的方式来进行校验,得到的时钟参数即为(bc),校验后得到时钟a1=(bc)+a,将此时钟参数封装在数据包内,通过IP网络发送到接收端。 In the main circuit simulation apparatus shown in FIG. 3, on the device after the power voltage controlled oscillator (VCO) initialize a center frequency of a clock, in the main circuit emulation device a local high frequency clock to the sampling clock CLK source (i.e., receive data clock) frequency clock, generates a count value B, then the local clock frequency sampling clock CLK generated by the voltage controlled oscillator, generates a count value of c, and a differential way to check a clock obtained parameter is the (BC), to give after checking clock a1 = (bc) + a, this clock parameters encapsulated within the packet transmitted to the receiving side through IP network.

把时钟信号加上标记封装在数据包内,由IP网络发送至接收端。 Clock signal marked encapsulated within a packet transmitted from the IP network to the receiving end.

在如图4所示的主从电路仿真设备中,接收端接收到上述的时钟测量值(时钟参数),根据这个时钟测量值(时钟参数),来驱动压控振荡器(VCO),从而恢复出主设备端时钟源的时钟。 In the primary circuit shown in Figure 4 from the emulation device, the receiving end receives the measured value of the above-described clock (clock parameters), according to the measured value of the clock (clock parameters), to drive a voltage controlled oscillator (the VCO), thereby restoring end of the master clock of the clock source.

本实施例对压控振荡器有较高的要求。 This embodiment has high requirements on the voltage controlled oscillator.

Claims (5)

  1. 1.一种分组电路仿真的远端测量近端恢复时钟技术,其特征是:在主电路仿真设备中对传送的E1的时钟信息进行采样,提取出时钟参数,并封装在数据包内,在从电路仿真设备中依据这个时钟参数恢复出精确的时钟信息,实现同步。 A distal end of the proximal end of the measurement circuit emulation packet clock recovery techniques, wherein: sampling the clock information is transmitted in a main E1 circuit emulation devices, the clock parameters are extracted and encapsulated within the packet, the recovery from the circuit emulation device according to this clock parameters precise clock information to achieve synchronization.
  2. 2.如权利要求1所述的分组电路仿真的远端测量近端恢复时钟技术,其特征是:主电路仿真设备端用差分恢复的方法来采样时钟信号,提取出时钟参数。 2. The distal end of the circuit emulation packet to claim 1, the proximal end of the recovered clock measurement techniques, characterized in that: the device side main circuit emulation method to recover the differential sampling clock signal, the extracted clock parameters.
  3. 3.如权利要求2所述的分组电路仿真的远端测量近端恢复时钟技术,其特征是:在主电路仿真设备中生成本地时钟CLK跟踪网络上传输的时钟,产生一个计数值b,再用此本地时钟CLK跟踪压控振荡器产生的时钟,产生一个计数值c,校验后得到时钟信号a1=(bc)+a,将此时钟信号标记并封装在数据包内,通过IP网络发送到接收端。 3. The distal end of the packet circuit according to claim 2 measurement simulation clock recovery techniques proximal end, wherein: generating a clock transmitted on the local network in the master clock CLK tracking circuit simulation apparatus, generates a count value B, then this local clock with the clock CLK VCO trace generated, generates a count value C, the clock signal after it is checked that a1 = (bc) + a, and this clock signal labeled encapsulated within the packet sent through the IP network to the receiving end.
  4. 4.如权利要求1所述的分组电路仿真的远端测量近端恢复时钟技术,其特征是:从电路仿真设备接收到上述的时钟测量值,根据这个时钟测量值,来驱动压控振荡器(VCO),从而精确地恢复出主设备端时钟源的时钟。 4. The circuit emulation packet distal end of the proximal end of a recovery clock claim measurement technology, characterized in that: receiving from the circuit emulation device to said clock measurement value, the measurement value according to this clock to drive the voltage controlled oscillator (VCO), so as to accurately recover the master clock end of the clock source.
  5. 5.如权利要求1所述的分组电路仿真的远端测量近端恢复时钟技术,其特征是:主、从两个电路仿真设备组成的网络是双向通信的。 5. The distal end of the circuit emulation packet to claim 1, the proximal end of the recovered clock measurement techniques, characterized in that: a main network composed of the two circuit emulation devices are two-way communication.
CN 200510071089 2005-05-24 2005-05-24 Clock recovery technology using of far-end measuring near-end recovery simulation packet circuit CN1870491A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101316160B (en) 2008-06-11 2010-12-15 南京磐能电力科技股份有限公司 Multi-node synchronization sampling and data transmission method
CN101034950B (en) 2007-04-20 2012-03-28 北京中星微电子有限公司 Clock synchronization method and device
CN103067114A (en) * 2012-12-20 2013-04-24 中兴通讯股份有限公司 Transmission system asynchronous mapping clock recovery method and transmission system asynchronous mapping clock recovery device
CN101394703B (en) 2008-10-17 2013-12-04 范红霞 Time clock recovery system and method
CN103905137A (en) * 2014-04-23 2014-07-02 南京磐能电力科技股份有限公司 Synchronous pulse jitter suppression method and system based on FPGA
CN104993820A (en) * 2015-07-07 2015-10-21 广东美的暖通设备有限公司 Calibration device and calibration method for frequency of oscillator

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101034950B (en) 2007-04-20 2012-03-28 北京中星微电子有限公司 Clock synchronization method and device
CN101316160B (en) 2008-06-11 2010-12-15 南京磐能电力科技股份有限公司 Multi-node synchronization sampling and data transmission method
CN101394703B (en) 2008-10-17 2013-12-04 范红霞 Time clock recovery system and method
CN103067114A (en) * 2012-12-20 2013-04-24 中兴通讯股份有限公司 Transmission system asynchronous mapping clock recovery method and transmission system asynchronous mapping clock recovery device
CN103067114B (en) * 2012-12-20 2017-12-05 中兴通讯股份有限公司 A transmission system for asynchronous mapping clock recovery method and apparatus
CN103905137A (en) * 2014-04-23 2014-07-02 南京磐能电力科技股份有限公司 Synchronous pulse jitter suppression method and system based on FPGA
CN103905137B (en) * 2014-04-23 2016-08-17 南京磐能电力科技股份有限公司 Jitter suppression method and system based on a synchronization pulse fpga
CN104993820A (en) * 2015-07-07 2015-10-21 广东美的暖通设备有限公司 Calibration device and calibration method for frequency of oscillator

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