CN102915705B - Timing sequence generating circuit for improving definition of light-emitting diode (LED) display screen with gray scale - Google Patents
Timing sequence generating circuit for improving definition of light-emitting diode (LED) display screen with gray scale Download PDFInfo
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Abstract
The invention discloses a timing sequence generating circuit for improving the definition of a light-emitting diode (LED) display screen with gray scale. The timing sequence generating circuit comprises a sub-field pulse signal processing circuit, a sampling pulse signal frequency dividing circuit, a luminance setting circuit, a 6BIT data beam concentrating circuit and one-from-multiple selecting circuit. The 6BIT data beam concentrating circuit converts high six-figure data in input data into a group of serially output pulses with high-low electrical levels concentrated together by means of a data weight-free encoding change method, the output end of the sampling pulse signal frequency dividing circuit outputs serial shift pulse with unique frequency, and width equivalence and beam concentration of the high six-figure data are achieved. In consideration of transmission frequency, rest low-position data are not required to be processed. Only the timing sequence generating circuit in a control system is changed, a drive mode of a display unit is not changed, the transmission characteristics of serial signals are not changed, the definition of the LED display screen is improved under the condition that the system cost is not increased, and the timing sequence generating circuit has great actual using significance and popularization value.
Description
Technical field
The present invention relates to LED display field, relate in particular to the timing generator circuit of a kind of raising with gray scale LED display sharpness.
Background technology
With the content that the LED display of gray scale is mainly used to Show Picture, video image etc. has gray shade scale, each LED pixel luminosity must be able to regulate, the fine degree of its adjusting is exactly the gray shade scale of display screen.Gray shade scale is higher, and the image of demonstration is just finer and smoother, and color is also abundanter.Quantizing if press every kind of 8BIT of red, green, blue 3 color image signal, is the image of 256 grades of gray scales; Every kind of 10BIT quantizes, and is the image of 1024 grades of gray scales; Every kind of 12BIT quantizes, and is the image of 4096 grades of gray scales, etc.
LED display with gray scale is made up of signal source, control system, screen body and power-supply system conventionally.The source that " signal source " is demonstration information, can be computing machine, video equipment, USB flash disk etc., by various ways outputs such as DVI, HMTV, network, USB." screen body " arranged in length and breadth by multiple luminescence units, forms a complete demonstration image.Luminescence unit is made up of red (Red), green (Green), blue (Blue) LED luminotron and driving circuit.Now the driving chip of conventional driving circuit has the chip of the built-in strings such as 74HC595, TB62726, ST2221C, MBI5028 shift register cell, output latch unit, drives the control inputs signal of chip to have data (R, G, B), shift pulse (CLK), latch pulse (STB) etc.This class drive chip because cheap, control the features such as simple, technology maturation, be the first-selection of most of LED display driving circuits, have most market.So analyze improvement, raising taking the driving chip of built-in string shift register cell, output latch unit as the control mode of the LED display of driving circuit, promote the development of LED display application market, there are very large economic implications and application prospect.
Comprise signal front-end processing and N subregion control with the LED display control system of gray scale, zoning controller number determine with screen body size, screen body compared with hour, signal front-end processing and subregion control can merge; Signal front-end processing mainly completes the reception, nonlinear transformation, sequential processing of the signal that " signal source " come, the work such as temporary, and by the mode of data stream, picture signal after treatment is sent to N zoning controller; Each zoning controller receiving data stream, the gray-scale value of the each pixel of luminescence unit in the control area that obtains controlling oneself, and all pixel gray-scale values are carried out to frame storage; Export data to screen body display unit by the mode of serial bit position output again, sequential pulsing is controlled in output simultaneously.
Now taking the Full color LED display screen of 10BIT, static latch mode as example, the principle of controlling the timing generator circuit that drives chip operation in the zoning controller of control system of the existing LED display with gray scale is described.
Fig. 1 is timing generator circuit block diagram in prior art, and Fig. 2 is timing generator circuit schematic diagram in prior art.R[9..0] represent 10BIT red image data input signal, R9 is most significant digit, R0 is lowest order; The processing mode of green image data and blue image data is identical with red image data, in circuit, no longer repeats.BITV represents BIT subfield input signal, after each BIT bit data is transmitted, produces a pulse; VS represents an input signal, and each all BIT bit data are transmitted after one time, produces a pulse; CP represents the clock input signal of synchronizeing with storer sense data; LV1, LV2, LCLK and L[3..0] for adjusting the input signal of whole screen brightness, realize by day, night etc. is when ambient brightness, controls the width of all driving chip OE, adjusts the function of whole screen brightness.
RD represents red image data output signal, CLK represents shift pulse output signal, STB represents latch pulse output signal, does data input, shift pulse input, latch pulse input respectively for the driving chip of the built-in string of driving circuit shift register cell, output latch unit.
In prior art, in timing generator circuit, sampling pulse (CP), through " frequency divider ", produces the time clock of different frequency; Subfield pulse (BITV), through " counter ", produces the gating signal for 2 " multiselect one gate " work, realizes in the time of the data of output different B IT position, exports different serial-shift pulses.
Fig. 3 is the output waveform schematic diagram of timing generator circuit in prior art, comprise the waveform that drives the output QN of the N position of chip in RD, CLK, STB, OE signal waveform and the luminescence unit of timing generator circuit output, the waveform of OE is that whole screen brightness is when maximum; Suppose the data R[9..0 of the pixel of controlling N position]=0101011111B.
From Fig. 2 and Fig. 3, see, in order to reduce the frequency of CLK signal transmission, the shift pulse output signal of low 4BIT data is rushed CP4 with the displacement of higher BIT position and substitute second, the difference of the gray level of low 4BIT bit data embodies by the width that presets OE, the data R0 of input, the reading rate of R1, R2, R3 also reduces, but it is constant to the character that drives chip to use to press BIT bit serial transmission data.
The beginning of, data RD signal gating R0, CLK gating CP4, realize the function of the minimum BIT of serial transmission position R0, according to the number of the big or small specified data serial transmission pulse of display unit, after being transmitted, latch pulse STB produces high impulse, allows each LED pixel show the bright dark of BIT position R0; Then transmission by turn, transmit successively the data of high with the BIT field of low, after being transmitted, latch pulse STB produces high impulse, allow each LED pixel show the bright dark of this low BIT position, certain every BIT position power and position difference, shift pulse CLK width difference, the interval of latch pulse STB is also same, and the dark time of LED pixel represent light is also different; When last BIT field, transmission data are " 0 ", and latch pulse STB produces high impulse, show the bright dark of BIT position R9, and ensure a dark minimum BIT field width degree in the time of next beginning, complete a circulation.In a circulation, all BIT of the each pixel bright time of position adds up to total brightness, reflects the gray level of pixel.
The waveform of the driver output QN of the N position of analysis-driven chip, we see that QN is a set of pulses, as long as the brightness number R[9..0 of pixel] not continuous " 1 ", its bright pulse separates.As: a certain BIT position is " 1 ", produces high impulse, and LED pixel is with regard to bright a period of time; Next BIT position is " 0 ", low a period of time, just dark a period of time of LED pixel; A BIT position, BIT position is " 1 " again, is output as " 1 ", producing high impulse, LED pixel is with regard to bright a period of time; Etc..
Find out thus, in prior art, each LED pixel is according to different pixels data, and by the combination of BIT position, the bright time of all BIT position LED pixel is added the total brightness of reflection; Pixel data difference, total brightness is also different, the gray level difference of reflection pixel.Because weights difference, the width of the highest BIT position R9 is 512 times of width of minimum BIT position R0, and the difference of pulse width is very large; The BIT digit pulse spaced far having in one group of bright pulse, some BIT digit pulses interval is near, and the interval of different pixels data is different.So in prior art, the method for LED pixel reflection gray level realizes by a set of pulses, each pulse width interval not identical, pulse of this set of pulses is also varied.
From the angle of optics, in one group of bright pulse, the width summation of pulse is identical, no matter how pulse distributes, brightness is all identical; Pixel data is little, and width summation is little, and pixel data is large, and width summation is large, and gray level is just high.But the image of LED display is watched for human eye, the overall quality such as gray level, sharpness of LED display, finally will make qualification by human eye, so the characteristic of LED display should adapt with the visual characteristic of human eye.
Image definition refers to the readability of the image that human eye macroscopic view sees, is the people that caused by the synthesis result of the objective performance of system and the equipment subjective sensations to final image.Experiment showed, in LED display, the apparent brightness feature of human eye, the impact of Broca-Sulzer effect is larger than Talbot-Plateau effect.After Broca-Sulzer effect is exactly the instantaneous flash receiving resemble shutter, the brightness that human eye is experienced is several times of intrinsic brilliance; But, repeatedly to accept after instantaneous flash, human eye can be experienced the mean flow rate in reciprocal time, is called " Talbot-Plateau effect ".Pulse width summation is identical, is concentrated into a wide pulse and is dispersed into several burst pulses, the corresponding difference of apparent brightness of human eye; Recurrent interval difference, also has impact to apparent brightness.Pixel reflects different gray levels by a set of pulses, the difference of its width summation of adjacent gray levels is identical, but human eye is inconsistent to the visual characteristic in different pulse widths, different recurrent interval, there is difference in apparent brightness, the adjacent gray levels apparent brightness difference making is large, what have is little, can not correctly reflect the luminance level feature of source images, and image definition declines.
Summary of the invention
The object of this invention is to provide the timing generator circuit of a kind of raising with gray scale LED display sharpness, can, in the situation that not increasing system cost, improve the sharpness of LED display.
The present invention adopts following technical proposals: the timing generator circuit of a kind of raising with gray scale LED display sharpness, include subfield pulse signal treatment circuit, sampling pulse signal frequency dividing circuit and brightness circuit is set, described timing generator circuit also includes pulse boundling treatment circuit, high six bit data in input data are input to pulse boundling treatment circuit, and the signal output part of pulse boundling treatment circuit is input to alternative gate;
Described subfield pulse signal treatment circuit includes shaping circuit, counter circuit, and its neutron field pulse signal is by shaping circuit output latch pulse signal, described subfield pulse signal is also input to counter as count pulse, field pulse input signal is input to counter as reset terminal, low three output signals of counter are input to the gating end of pulse boundling treatment circuit and the gating end of multiselect one gate, high four output signals of described counter are input to code translator, the most significant digit output signal of counter is as allowing end to be connected with code translator, eight output signals of code translator are as allowing end to be input to pulse boundling treatment circuit, the most significant digit output signal of described counter is also by being input to multiselect one gate as allowing to hold after phase inverter, be input to alternative gate as gating end, low data in input data outputs to multiselect one gate, and the output terminal of multiselect one gate is input to alternative gate, the output terminal output serial data signal of alternative gate, described sampling pulse signal frequency dividing circuit comprises frequency divider, and sampling pulse signal is input to frequency divider, and described subfield pulse signal is input to the reset terminal of frequency divider, the output terminal output serial pulse signal of frequency divider.
Described pulse boundling treatment circuit is 6BIT data boundling module, described 6BIT data boundling module comprise eight data encoding function modules and 8 and door, the input signal of each data encoding functional module has identical high six bit data, gating signal, also have different permission signal and preset level signal separately, 8 are the signal output part of pulse boundling treatment circuit with the signal output part of door.
Described data encoding functional module comprises that 3-8 haves no right re-encoder, comparer, triple gate, multiselect one gate, described 3-8 haves no right the signal input part of re-encoder and is connected with low three bit data in high six bit data, and 3-8 haves no right the signal output part of re-encoder and is input to the first triple gate; High 3 bit data and preset level in high six bit data are input in comparer, the permission signal end that is less than, equals, is greater than signal output part and output to respectively the first triple gate, the second triple gate, the 3rd triple gate of comparer, the second triple gate input is provided with high level signal end, the 3rd triple gate input is provided with low level signal end, the signal output part of the first triple gate, the second triple gate, the 3rd triple gate is all input in multiselect one gate, and multiselect one gate has also been inputted gating signal end and allowed signal end; The output terminal of multiselect one gate is the signal output part of data encoding functional module.
The present invention proposes a kind of, boundlingization wide by pulse processes to improve and in the zoning controller with gray scale LED display sharpness, controls the timing generator circuit that drives chip operation, change and in the zoning controller of control system, controlled the timing generator circuit that drives chip operation, to driving the set of pulses of driving LED pixel for chip in luminescence unit, can realize in the first-class broadening of figure image height 6 bit data, boundling processing, show as the wide pulse that cluster concentrates in together, recurrent interval is identical, reaches the linear object of apparent brightness and gray level; Low BIT bit data is taken into account need to not processing of reduction system transmission frequency.Thereby reach the object of the sharpness that improves LED display.
Because only having changed, the present invention in the zoning controller of control system, controls the timing generator circuit that drives chip operation, in the type of drive that does not change display unit, do not change the characteristic of serial signal transmission, do not increase in the situation of system cost, the sharpness that improves LED display, has larger actual use meaning and promotional value.
Brief description of the drawings
Fig. 1 is timing generator circuit block diagram in prior art;
Fig. 2 is the circuit theory diagrams of timing generator circuit in prior art;
Fig. 3 is the output waveform schematic diagram of timing generator circuit in prior art;
Fig. 4 is timing generator circuit block diagram of the present invention;
Fig. 5 is timing generator circuit schematic diagram of the present invention;
Fig. 6 is the circuit block diagram of 6BIT data boundling module in the present invention;
Fig. 7 is the circuit theory diagrams of 6BIT data boundling module in the present invention;
Fig. 8 is the circuit block diagram of data encoding functional module in the present invention;
Fig. 9 is the circuit theory diagrams of data encoding functional module in the present invention;
Figure 10 is the output waveform schematic diagram of timing generator circuit of the present invention.
Embodiment
The present invention proposes to control and drive chip operation timing generator circuit in the zoning controller of a kind of raising with gray scale LED display sharpness, in the present embodiment taking 10BIT(1024 level gray scale), the Full color LED display screen of static latch mode describes as example, 10BIT is divided into high six bit data and low six bit data.As shown in Figure 4, Figure 5, include subfield pulse signal treatment circuit, sampling pulse signal frequency dividing circuit, brightness circuit, pulse boundling treatment circuit and alternative gating circuit are set, high six bit data in input data are input to pulse boundling treatment circuit (6BIT data boundling module), and low four figures is according to being input to multiselect one gating circuit; The signal output part of 6BIT data boundling module and multiselect one gating circuit is input to alternative gate.
The present invention has changed in the zoning controller of control system and has controlled the timing generator circuit that drives chip operation, can realize the set of pulses of driving LED pixel for the driving chip to luminescence unit in the first-class broadening of high 6 bit data, the boundling processing of image.The broadenings such as pulse refer in a set of pulses and use the equal pulse of width, and reflect different image gray levels signals by different pulse numbers, gray level is high, and pulse number is many, and gray level is low, and pulse number is few.Boundlingization processingization refers to all bright pulses in a set of pulses concentrated in together, and the low level time period concentrates in together, and the interval of realizing pulse is identical.According to such thinking, all LED pixel grayscale show as the wide pulse group that cluster concentrates in together, recurrent interval is identical, data-signal increases a gray level, pulse group just increases a pulse, any 2 gray levels all follow such principle, in the time of the variation of different grey-scale, pulse width can not change, interval can not change, realize between any 2 gray levels apparent brightness poor identical, for example: poor and poor identical from the apparent brightness of 200 grades of brightness to 201 grade brightness from the apparent brightness of 100 grades of brightness to 101 grade brightness, reach the relation of apparent brightness and grey scale linear.So just solved existing with gray scale the control system of LED display in, LED pixel reflects gray level by a set of pulses, and each pulse width of this set of pulses interval not identical, pulse is also varied, can not reflect truly the luminance level feature of source images, the shortcoming that image definition declines.
Described subfield pulse signal treatment circuit includes shaping circuit, counter circuit, and its neutron field pulse signal BITV is by shaping circuit output latch pulse signal STB, described subfield pulse signal BITV is also input to counter as count pulse, field pulse input signal VS is input to counter as reset terminal, form the synchronous counter of 8 forward countings, low three output signals of counter are input to the gating end of 6BIT data boundling module and the gating end of multiselect one gate, high four output signals of described counter are input to code translator, the most significant digit output signal of counter is as allowing end to be connected with code translator, eight output signals of code translator are as allowing end to be input to 6BIT data boundling module, the most significant digit output signal of described counter is also by being input to multiselect one gate as allowing to hold after phase inverter, be input to alternative gate as gating end.
Described sampling pulse signal frequency dividing circuit comprises frequency divider, sampling pulse signal CP is input to frequency divider, described subfield pulse signal is input to the reset terminal of frequency divider, the output terminal output serial pulse signal of frequency divider, pulse is wide to be realized by a kind of frequency by sampling pulse signal frequency dividing circuit.
High six bit data view data R[9..4], low four bit image data R[3..0] composition R[9..0], represent 10BIT red image data input signal, R9 is most significant digit, R0 is lowest order; The processing mode of green image data and blue image data is identical, and narration is below also taking red image data as example, and green image data and blue image data no longer repeat.The gating signal that produces at subfield pulse signal treatment circuit, allow under the control of signal the high six bit data R[9..4 of viewdata signal] be input to 6BIT data boundling module, i.e. functional module 6BIT-CL in Fig. 5; The low 4 bit data R[3..0 of viewdata signal] input multiselect one gating circuit; The output of 6BIT data boundling module and multiselect one gating circuit is re-used as two tunnel inputs and is connected to alternative gate, and the data pulse RD of the output serial that alternative gate produces is for driving chip.
In described sampling pulse signal frequency dividing circuit, sampling pulse signal CP is input to frequency divider as time clock; Described subfield pulse signal BITV is input to frequency divider as reset terminal, and realization is synchronizeed with BITV's; The output terminal of frequency divider produces serial pulse signal CLK, and serial pulse signal CLK only has a kind of frequency division value, and frequency is invariable.In circuit, in a BIT subfield, the pulse number of serial pulse signal CLK is determined by the area size of display unit, ensure in a BIT subfield, a data of all pixels of display unit to be transmitted, determine that like this BIT subfield signal BITV is also one group of pulse signal that interval is identical.Like this, the serial pulse signal CLK frequency of driving chip that inputs to luminescence unit is identical, and latch pulse signal STB is also wide, drives the driver output pulse width of chip identical, has realized the function of the broadening processing such as picture signal.
As shown in Figure 6, Figure 7,6BIT data boundling module comprise eight 3BIT data encoding functional modules (M1-M8) and 8 and door, the input signal of each 3BIT data encoding functional module has identical high six bit data, gating signal, also have different separately permission signal and preset level signal, the output terminal of each data encoding functional module be input to 8 with door, 8 are the signal output part of 6BIT data boundling module with the signal output part of door.As shown in Figure 8, Figure 9, described data encoding functional module comprises that 3-8 haves no right re-encoder, comparer, triple gate, multiselect one gate, described 3-8 haves no right the signal input part of re-encoder and is connected with low three bit data in high six bit data, and 3-8 haves no right the signal output part of re-encoder and is input to the first triple gate; High 3 bit data and preset level in high six bit data are input in comparer, the permission signal end that is less than, equals, is greater than signal output part and output to respectively the first triple gate, the second triple gate, the 3rd triple gate of comparer, the input of the second triple gate is set to high level, the input of the 3rd triple gate is set to low level, the signal output part of the first triple gate, the second triple gate, the 3rd triple gate is input in multiselect one gate after being connected, and multiselect one gate has also been inputted gating signal and allowed signal; Multiselect one gate is by three gating signals and the permission signal controlling inputted, and the output terminal of multiselect one gate is the signal output part of 3BIT data encoding functional module.
The function of 3BIT data encoding functional module inside is by as shown in truth table one.In table, D2, D1, D0 are low three bit data of 6 bit data; What G-0, G, G-1 were comparer is less than, equals, is greater than three output terminals; Q7-Q0 is the output valve after the signal output part of three triple gates is directly connected.
Truth table one
Seen by truth table one, work as D[2..0]=011B=03H, when high 3 bit data in high six bit data and preset level input equate, Q[7..0]=1110000B, illustrate that now binary input numerical value is 03H, 8 bit data of output have 3 for high level, and high level is all concentrated in together.This Implement of Function Module 3BIT have the data-switching of weight to become 8 without weight and the concentrated data of high level, after data output signal, add again multiselect one gate to become serial output, and under the circuit such as comparer and triple gate is auxiliary, for data expansion provides preparation.
And 6BIT data boundling module is to have the data-switching of weight to become 64 without weight and the concentrated data of high level 6BIT, 64 gating circuits are also added, by data step-by-step gating.In a circulation, allow signal first to make data encoding functional module M1 work, high 3 bit data in high six bit data and the comparison of preset level signal, the preset level signal of data encoding functional module M1 is " 111 ", if high 3 bit data in high six bit data are less than " 111 ", 8 " 0 " of data encoding functional module M1 serial output, the functional module that is not allowed to signal permission work is all exported " 1 ", eight allow the serial output signal of module M1 as the signal output part signal output of 6BIT data boundling module with door, and later analysis situation is identical; Then, allow signal to make data encoding functional module M2 work, the preset level signal of data encoding functional module M2 is " 110 ", if high 3 bit data in high six bit data are less than " 110 ", and 8 " 0 " of data encoding functional module M2 serial output; Moreover, allow signal to make data encoding functional module M3 work, the preset level signal of data encoding functional module M3 is " 101 ", if high 3 bit data in high six bit data equal " 101 ", data encoding functional module M3 converts low 3 bit data in high six bit data to 8 without weight and the concentrated data parallel series output of high level, when output, low level, in a front high position rear, makes " 0 " of changing rear data be connected with " 0 " of module M2 output; Moreover, allow signal to make data encoding functional module M4 work, the preset level signal of data encoding functional module M4 is " 100 ", high 3 bit data in high six bit data are greater than " 100 ", 8 " 1 " of data encoding functional module M4 serial output, because " 1 " of module M3 output in the back, be connected with " 1 " of module M4 serial output; 8 " 1 " of the equal serial output of functional module below.Like this, 6BIT data boundling module converts 6 view data that have a weight to serial output 64 without weight burst, form all " 0 " above, all " 1 " in the back, the number of " 1 " equals the data sequence of 6 bit values, realized the function of image data set fasciculation.
As shown in Fig. 4, Fig. 5, Figure 10; view data output signal RD provides the serial data of driving circuit; pixel data R[9..0] high 6BIT position R[9..4] through 6BIT data boundling modules (functional module: 6BIT-CL) produce 64 groups of data, represent the brightness of high 6BIT position; Low 4BIT position R[3..0] constant by existing control system circuit, do not process direct gating.Processing is like this that the frequency of chip serial transmission is the highest can not exceed 30MHz because drive, and the display unit pixel number that sub-controller will be controlled can not be too little, otherwise there is no actual use meaning.In the present embodiment, the frequency transmission that serial pulse signal CLK still uses with in prior art, low-limit frequency CP4 is identical, the difference of the gray level of low 4BIT bit data embodies by the width that presets OE, CLK frequency is: fclk=120Hz*(64+1+4) * 2048=16.9MHz, frequency is lower than the high-transmission frequency limitation that drives chip, in formula: 120Hz is refreshing frequency, " 64+1+4 " is a number of times that middle data load, " 2048 " are the area size of the luminescence unit of one group of driver output control of hypothesis, the regional change of luminescence unit, CLK frequency also changes thereupon, the region of luminescence unit is with the scan mode of LED display, drive chip, the factors such as working environment have relation.
So this patent is considered the needs of practical application, allow to do the processing that some indexs reduce, high six of view data is done the broadenings such as pulse, boundling processing, shows as the wide pulse that cluster concentrates in together, recurrent interval is identical, reaches the linear object of apparent brightness and gray level, low BIT bit data is taken into account need to not processing of reduction system transmission frequency, even like this, low BIT bit data is in pulsewidth, diversity ratio prior art on recurrent interval also has certain improvement, still can reach good image processing effect and stronger practical application meaning, better solved existing with gray scale the control system of LED display in, LED pixel reflects gray level by a set of pulses, and each pulse width of this set of pulses is not identical, the interval of pulse is also varied, can not reflect truly the luminance level feature of source images, the shortcoming that image definition declines.
In concrete project, for not being 10BIT quantification, the picture signal of 1024 grades of gray scales, still do the broadenings such as pulse, boundling processing by high six bit data, remain low BIT position by prior art processing, circuit also adjusts accordingly, but principle is identical, in the scope all requiring at this patent.Because the timing generator circuit of patent of the present invention generally realizes in programming logic gate array FPGA at the scene, the selection meeting difference of FPGA internal module, in patent of the present invention, circuit block diagram and circuit theory diagrams are for processing mode is described, some difference of processing mode possibility of logical circuit, but basic composition form is identical.
Claims (3)
1. the raising timing generator circuit with gray scale LED display sharpness, include subfield pulse signal treatment circuit, sampling pulse signal frequency dividing circuit and brightness circuit is set, it is characterized in that: described timing generator circuit also includes pulse boundling treatment circuit, high six bit data in input data are input to pulse boundling treatment circuit, and the signal output part of pulse boundling treatment circuit is input to alternative gate;
Described subfield pulse signal treatment circuit includes shaping circuit, counter circuit, and its neutron field pulse signal is by shaping circuit output latch pulse signal, described subfield pulse signal is also input to counter as count pulse, field pulse input signal is input to counter as reset terminal, low three output signals of counter are input to the gating end of pulse boundling treatment circuit and the gating end of multiselect one gate, high four output signals of described counter are input to code translator, the most significant digit output signal of counter is as allowing end to be connected with code translator, eight output signals of code translator are as allowing end to be input to pulse boundling treatment circuit, the most significant digit output signal of described counter is also by being input to multiselect one gate as allowing to hold after phase inverter, be input to alternative gate as gating end, remaining data in input data outputs to multiselect one gate, and the output terminal of multiselect one gate is input to alternative gate, the output terminal output serial data signal of alternative gate, described sampling pulse signal frequency dividing circuit comprises frequency divider, and sampling pulse signal is input to frequency divider, and described subfield pulse signal is input to the reset terminal of frequency divider, the output terminal output serial pulse signal of frequency divider.
2. the timing generator circuit of raising according to claim 1 with gray scale LED display sharpness, it is characterized in that: described pulse boundling treatment circuit is 6BIT data boundling module, described 6BIT data boundling module comprise eight data encoding function modules and 8 and door, the input signal of each data encoding functional module has identical high six bit data, gating signal, also have different permission signal and preset level signal separately, 8 are the signal output part of pulse boundling treatment circuit with the signal output part of door.
3. the timing generator circuit of raising according to claim 2 with gray scale LED display sharpness, it is characterized in that: described data encoding functional module comprises that 3-8 haves no right re-encoder, comparer, triple gate, multiselect one gate, described 3-8 haves no right the signal input part of re-encoder and is connected with low three bit data in high six bit data, and 3-8 haves no right the signal output part of re-encoder and is input to the first triple gate; Senior Three bit data and preset level in high six bit data are input in comparer, the permission signal end that is less than, equals, is greater than signal output part and output to respectively the first triple gate, the second triple gate, the 3rd triple gate of comparer, the second triple gate input is provided with high level signal end, the 3rd triple gate input is provided with low level signal end, the signal output part of the first triple gate, the second triple gate, the 3rd triple gate is all input in multiselect one gate, and multiselect one gate has also been inputted gating signal end and allowed signal end; The output terminal of multiselect one gate is the signal output part of data encoding functional module.
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| CN105390091B (en) * | 2015-11-04 | 2017-12-08 | 深圳市绿源半导体技术有限公司 | LED shows enable signal control system, LED display system and display drive method |
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