CN101930349B - Led scanning control chip - Google Patents

Led scanning control chip Download PDF

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Publication number
CN101930349B
CN101930349B CN2010102539579A CN201010253957A CN101930349B CN 101930349 B CN101930349 B CN 101930349B CN 2010102539579 A CN2010102539579 A CN 2010102539579A CN 201010253957 A CN201010253957 A CN 201010253957A CN 101930349 B CN101930349 B CN 101930349B
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input end
output terminal
connects
shift register
sixteen bit
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CN101930349A (en
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林洺锋
王伟
赵平林
张春旺
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Shenzhen Zhouming Technology Co Ltd
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Shenzhen Zhouming Technology Co Ltd
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Abstract

The invention discloses an LED scanning control chip, comprising the following modules of an output amperage adjuster, a constant current source, a counter, a synchronous controller, a sixteen-bit displacement buffer, a state buffer, a comparator, and a buffer memory, and the like. The invention has the advantages that a novel FPGA (Field Programmable Gate Array)-based scanning control chip forms an LED large screen display system together with a peripheral circuit, a display panel and a computer by arranging a synchronous controller, a counter, a displacement buffer, a buffer memory and a comparator: the grey display of 256 levels of the LED display screen is realized; and clear and stable pictures are displayed on the premise of simplifying system hardware structures.

Description

The LED scanning control chip
Technical field
The present invention relates to LED display and semi-conductor chip field, relate in particular to a kind of LED scanning control chip.
Background technology
LED (light emitting diode) display screen is made up of light emitting diode matrix.Light emitting diode (LED) is a kind of current control device; Have advantages such as brightness height, volume is little, monochromaticity good, response speed is fast, driving is simple, the life-span is long; Therefore the information release tasks of the real-time of the competent various occasions of ability, diversity, dynamic has obtained widespread use.Wherein, The LED giant-screen is to be combined by led array; Realize the clear broadcast of signals such as literal, image, picture, video, TV through certain control method; All adopted the form of standard cell block on its structure; Promptly adopt 8*16,16*16,16*32,24*24 or 32*32 display pixel fluorescent tube to constitute a unit module, each module forms independently electron scanning function, control function, memory function, and constitutes an independent subsystem with this; And then connect and compose complete some matrix LED giant-screen with each standard source and communication driver part, add certain computer controlled member made, just constituted the whole LED display system after having multimedia card or the DVI card and the power supply memory communication driver part of digitizing component output.
See also Fig. 1; Core wherein is the LED scanning control chip, wants to check on it and how to control, and must know its gray scale scanning principle: for high grade grey level LED large screen display; The layered approach of gray scale is the Video Controller key for design; Because the luminosity of LED and the fluorescent lifetime in the scan period are approximated to direct ratio, so the realization of gray shade scale promptly adopts modulation duty cycle to realize normally by the fluorescent lifetime of control LED and the ratio of scan period.Supposing that the display gray scale number of degrees is N, is t because gray level is 1 pixel in the correspondence time of lighting of screen body, thereby gray level is that data presentation time of i is it after the gray scale linear modulation, and the data presentation time that gray level is the highest is (N-1) * td.Common consideration is in td, to accomplish once the reading of storer data line, and to be the cycle simultaneously with td be driven into the screen body with the data line of reading carries out gray scale and show.Since have N number of greyscale levels, so be frame-scan period: T=n*t*m,
Screen body display efficiency: p=(N-1) * t*m/T=(N-1)/N, setting video data input rate is Vi, it is Vo that storer is read speed, owing to must accomplish once reading of data line in the storage unit in the time at t; So Vo/Vi>=h/ (t*n) is arranged, establish λ and be storer and read the ratio with input rate, i.e. λ=Vo/Vi; λ>=h/ (t*n)=h*N*m/ (T*n), for guaranteeing the steady display of image, the scanning frame frequency must be enough high; If F>=Fo, T≤To then, (To=1/Fo).Fo is the acceptable scanning frame frequency of human eye (Fo >=60), λ >=h*N*m/ (To*n); T=To/ (N*m).For 256 grades of gray scale full screen scannings; It is conflicting that high number of greyscale levels, high scanning frame frequency and low storer are read speed, obtain high number of greyscale levels, just must improve the read-out speed of storer; Perhaps reduce vertical sweep frequency; When number of greyscale levels is higher, be difficult to reach the three with present integrated circuit realization level and take into account, one of solution is to adopt parallel organization in a large number; But one times of cost of the every minimizing of sweep frequency just increases by one times nearly, and the complexity of circuit also can increase to some extent; Another kind method is the compromise of proper longer screen body display efficiency in the hope of frame frequency and speed, adopts λ=1, t=h/16, and promptly storer is read speed and is equaled the data input rate, and demonstration basic time unit is 1/16 of a line period.Gray scale scanning is realized through the method that gradation data step-by-step timesharing is shown; Be computer screen image when exporting (each 8bit of red, green, blue) with every pixel 24bit, the not coordination of the bit byte through giving every kind of color distributes the different demonstration time to reach the purpose that gray scale shows, like the corresponding 1/16 row demonstration time of lowest order (the 8th); The 7th 1/8 row demonstration time of correspondence; ..., second 4 row demonstration time of correspondence, corresponding 8 row demonstration times of most significant digit.Screen volume data update time is unit with the line period, and lowest order corresponding update time is 1 line time, wherein shows 1/16 line time, in all the other 15/16 line times, produces blanking signal by control circuit and carries out blanking, and all the other positions roughly the same.
Summary of the invention
The technical matters that the present invention mainly solves provides a kind of LED scanning control chip of importing based on eight bit parallels of FPGA; 256 grades of gray scales that can realize LED display show, under the prerequisite of simplified system hardware configuration, obtain steady and audible picture display effect.
For solving the problems of the technologies described above; The technical scheme that the present invention adopts is: a kind of LED scanning control chip is provided, comprises output current regulator, constant current source, counter, isochronous controller, sixteen bit bit shift register, status register, comparer and buffering storer; Said output current regulator has first input end, second input end and output terminal; Said counter has first input end, second input end and output terminal; Said isochronous controller has input end, first output terminal, second output terminal and the 3rd output terminal; Said sixteen bit bit shift register has first input end, second input end, the 3rd input end, four-input terminal, first output terminal, second output terminal and the 3rd output terminal; Said memory buffer has input end and output terminal, and said comparer has first input end, second input end and output terminal; Said status register has first input end, second input end, first output terminal and second input end; The first input end of said output current regulator connects the outer meeting resistance that is used to set output current; Second input end of said output current regulator connects first output terminal of said status register, and the output terminal of said output current regulator connects the control end of constant current source; The first input end of said counter connects the GTG clock signal, and second input end of said counter connects the output terminal of isochronous controller, and the output terminal of said counter connects the first input end of said comparer; The input end of said isochronous controller connects the data strobe signal; First output terminal of said isochronous controller connects second input end of said counter; Second output terminal of said isochronous controller connects the first input end of said status register, and the 3rd output terminal of said isochronous controller connects said sixteen bit bit shift register the 3rd input end; The first input end of said sixteen bit bit shift register connects data clock signal; The second input end input serial data of said sixteen bit bit shift register; The 3rd input end of said sixteen bit bit shift register connects the 3rd output terminal of isochronous controller; Second output terminal of the four-input terminal connection status buffer of said sixteen bit bit shift register; Second input end of the first output terminal connection status buffer of said sixteen bit bit shift register, second output terminal of said sixteen bit bit shift register connects the input end of memory buffer, the 3rd output terminal output serial data of said sixteen bit bit shift register; The input end of said memory buffer connects second output terminal of sixteen bit bit shift register, and the output terminal of said memory buffer connects second input end of said comparer; The output terminal of the first input end linkage counter of said comparer, second input end of said comparer connects the output terminal of memory buffer, and the output terminal of said comparer connects constant current source; The quantity of the quantity of said memory buffer, the quantity of said comparer and said constant current source is identical.
Wherein, Said LED scanning control chip also comprises sixteen bit LED misdata processing module; Said sixteen bit bit shift register has the 5th input end; The input end of said sixteen bit LED misdata processing module connects constant current source, and the output terminal of said sixteen bit LED misdata processing module connects the 5th input end of sixteen bit bit shift register.
Wherein, the quantity of the quantity of the quantity of said memory buffer, said comparer and said constant current source is 16.
Wherein, said counter is 12 or 16 digit counters.
The invention has the beneficial effects as follows: a large amount of its complicated circuit of employing parallel organization and the higher defective of cost that are different from prior art; Perhaps sacrifice chip performance and try to achieve the defective of effect; The present invention adopts a kind of novel scanning control chip based on FPGA (field programmable gate array); Through isochronous controller, counter, bit shift register, memory buffer and comparer are set; Make the LED large screen display system that this chip and peripheral circuit, display panel and computing machine constitute, realize that 256 grades of gray scales of LED display show, under the prerequisite of simplified system hardware configuration, obtain steady and audible picture display effect.
Description of drawings
Fig. 1 is the LED display system architectures block scheme of background technology;
Fig. 2 is the functional block diagram of the LED scanning control chip of the embodiment of the invention;
Fig. 3 is the control circuit figure of the LED scanning control chip of the embodiment of the invention.
Embodiment
By specifying technology contents of the present invention, structural attitude, realized purpose and effect, give explanation below in conjunction with embodiment and conjunction with figs. are detailed.
See also Fig. 2, LED scanning control chip of the present invention comprises output current regulator, constant current source, counter, isochronous controller, sixteen bit bit shift register, sixteen bit LED misdata processing module, status register, comparer and buffering storer;
Said output current regulator has first input end, second input end and output terminal; The first input end of said output current regulator connects the outer meeting resistance that is used to set output current; Second input end of said output current regulator connects first output terminal of said status register, and the output terminal of said output current regulator connects the control end of constant current source;
Said counter has first input end, second input end and output terminal; The first input end of said counter connects the GTG clock signal; Second input end of said counter connects the output terminal of isochronous controller, and the output terminal of said counter connects the first input end of said comparer;
Said isochronous controller has input end, first output terminal, second output terminal and the 3rd output terminal; The input end of said isochronous controller connects the data strobe signal; First output terminal of said isochronous controller connects second input end of said counter; Second output terminal of said isochronous controller connects the first input end of said status register, and the 3rd output terminal of said isochronous controller connects said sixteen bit bit shift register;
Said sixteen bit bit shift register has first input end, second input end, the 3rd input end, four-input terminal, the 5th input end, first output terminal, second output terminal and the 3rd output terminal; The first input end of said sixteen bit bit shift register connects data clock signal; The second input end input serial data of said sixteen bit bit shift register; The 3rd input end of said sixteen bit bit shift register connects the 3rd output terminal of isochronous controller; Second output terminal of the four-input terminal connection status buffer of said sixteen bit bit shift register; The 5th input end of said sixteen bit bit shift register connects the output terminal of sixteen bit LED misdata processing module; Second input end of the first output terminal connection status buffer of said sixteen bit bit shift register, second output terminal of said sixteen bit bit shift register connects the input end of memory buffer, the 3rd output terminal output serial data of said sixteen bit bit shift register;
The input end of said memory buffer connects second output terminal of sixteen bit bit shift register, and the output terminal of said memory buffer connects second input end of said comparer;
Said comparer has first input end, second input end and output terminal; The output terminal of the first input end linkage counter of said comparer; Second input end of said comparer connects the output terminal of memory buffer, and the output terminal of said comparer connects constant current source;
The input end of said sixteen bit LED misdata processing module connects constant current source, and the output terminal of said sixteen bit LED misdata processing module connects the 5th input end of sixteen bit bit shift register.
The quantity of said memory buffer is identical with the quantity of the quantity of said comparer and said constant current source, can or be 16 multiple for 16.
Said counter is 12 or 16 digit counters.
The embodiment of the invention is to realize like this from vain to 256 grades of black gray-scale Control; This control chip has 16 bit serial input ports with clock synchronization; Include 16 bit shift buffers and 16 bit data latchs, can be shifted and latch 16 bit serial data.When circuit was started working, 16 bit serial data were squeezed under the effect of shift clock pulse in the offset buffer module of chip, and 16 shift registers are contained in its inside, were shifted after 16 times, and data will output to next chip from the SDO of this chip; 16 16 bit data of gained of will being shifted simultaneously are input in the GTG mapped buffer storer, and provide the capable gating signal of of the same name row and its output opened as long as the output control signal is low this moment; Each row can begin to export constant current; Simultaneously 12 digit counters begin the gray level clock is counted, and when the gray-scale value of being stored in count value and this row comparer equated, i.e. end was exported in the constant current of these row; Thereby realize that corresponding LED shows the control of time, i.e. dutycycle control.If adopt 10 these indicative control unit cascade driving LED display screens, then parallel always displacement just can be accomplished the transmission of first line data for 160 times.
Utilization VerilogHDL writes code and with the Modelsim simulation software this circuit code is compiled emulation; Can see under the control of control ends such as control end enable, rsel, bc ena, latch; Can realize control according to different demands to different gray scales and brightness; In the gray-scale Control unit, data shift transport to output terminal after having passed through 16 pulses is exported, and has realized the adjustable of 8 row or 16 row outputs; In brightness control unit, can realize the adjustable of output data equally through the value of adjusting enable, bc ena, latch, thereby realize the function of brilliance control accurately; Equal demonstration time of this row of the same name according to whole transmission times of each several part row of the same name, can obtain the value in line period and row cycle, be i.e. the line number of line period=frame period/scan mode, row cycle=line period/(every row count * part number).For example frame frequency is 120Hz, and then the frame period is 1/120s=8.33ms, is 1,/16 80 row to be divided into 5 16 row according to scan mode, and every row 160 is listed as, and line period is 520.6 μ s like this, and the row cycle is 650.75ns, and the row frequency is 1.54*106Hz.
The definition of each pin of chip of the embodiment of the invention is following:
GND: the earth terminal of steering logic and drive current.
SDI: the serial data input end that inputs to bit shift register.
DCLK: the input end of data clock signal, the data displacement occurs in the clock rising edge, when LE starts, but input control order.
LE: data are dodged the control input end, cooperate DCLK can assign control command.
OUT0~OUT15: constant current output terminal.
GCLK: GTG clock signal input terminal, GTG show it is by the function that relatively reach Wave-wide regulation controlled electric of GTG clock with the input data.
SDO: the serial data output terminal, the SDI that can be connected to next driver holds.
R-EXT: the input end that connects outer meeting resistance; This outer meeting resistance can be set the output current of all output channels.
The VDD:3.3V/5V power source supply end.
See also Fig. 3, the circuit control end of the embodiment of the invention defines as follows:
Din: data input pin.
Rsel: row selects signal end.
Mode: pattern control end.
Latch: latch signal end.
Clk: clock signal terminal.
Clkh: high level output.
Clkl: low level output.
Enable: enable control end.
Be different from a large amount of its complicated circuit of employing parallel organization and the higher defective of cost of prior art; Perhaps sacrifice chip performance and try to achieve the defective of effect; The present invention adopts a kind of novel scanning control chip based on FPGA; Through isochronous controller, counter, bit shift register, memory buffer and comparer are set; Make that the LED large screen display system that this chip and peripheral circuit, display panel and computing machine constitute, 256 grades of gray scales of realization LED display show, under the prerequisite of simplified system hardware configuration, obtain steady and audible picture and show.
The above is merely embodiments of the invention; Be not so limit claim of the present invention; Every equivalent structure or equivalent flow process conversion that utilizes instructions of the present invention and accompanying drawing content to be done; Or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.

Claims (4)

1. a LED scanning control chip is characterized in that: comprise output current regulator, constant current source, counter, isochronous controller, sixteen bit bit shift register, status register, comparer and buffering storer;
Said output current regulator has first input end, second input end and output terminal; Said counter has first input end, second input end and output terminal; Said isochronous controller has input end, first output terminal, second output terminal and the 3rd output terminal; Said sixteen bit bit shift register has first input end, second input end, the 3rd input end, four-input terminal, first output terminal, second output terminal and the 3rd output terminal; Said memory buffer has input end and output terminal; Said comparer has first input end, second input end and output terminal, and said status register has first input end, second input end, first output terminal and second input end;
The first input end of said output current regulator connects the outer meeting resistance that is used to set output current; Second input end of said output current regulator connects first output terminal of said status register, and the output terminal of said output current regulator connects the control end of constant current source;
The first input end of said counter connects the GTG clock signal, and second input end of said counter connects the output terminal of isochronous controller, and the output terminal of said counter connects the first input end of said comparer;
The input end of said isochronous controller connects the data strobe signal; First output terminal of said isochronous controller connects second input end of said counter; Second output terminal of said isochronous controller connects the first input end of said status register, and the 3rd output terminal of said isochronous controller connects said sixteen bit bit shift register the 3rd input end;
The first input end of said sixteen bit bit shift register connects data clock signal; The second input end input serial data of said sixteen bit bit shift register; The 3rd input end of said sixteen bit bit shift register connects the 3rd output terminal of isochronous controller; Second output terminal of the four-input terminal connection status buffer of said sixteen bit bit shift register; Second input end of the first output terminal connection status buffer of said sixteen bit bit shift register, second output terminal of said sixteen bit bit shift register connects the input end of memory buffer, the 3rd output terminal output serial data of said sixteen bit bit shift register;
The input end of said memory buffer connects second output terminal of sixteen bit bit shift register; The output terminal of the first input end linkage counter of said comparer; Second input end of said comparer connects the output terminal of memory buffer, and the output terminal of said comparer connects constant current source;
The quantity of the quantity of said memory buffer, the quantity of said comparer and said constant current source is identical.
2. LED scanning control chip according to claim 1; It is characterized in that: also comprise sixteen bit LED misdata processing module; Said sixteen bit bit shift register has the 5th input end; The input end of said sixteen bit LED misdata processing module connects constant current source, and the output terminal of said sixteen bit LED misdata processing module connects the 5th input end of sixteen bit bit shift register.
3. LED scanning control chip according to claim 1 and 2 is characterized in that: the quantity of the quantity of said memory buffer, the quantity of said comparer and said constant current source is 16.
4. LED scanning control chip according to claim 1 and 2 is characterized in that: said counter is 12 or 16 digit counters.
CN2010102539579A 2010-08-16 2010-08-16 Led scanning control chip Expired - Fee Related CN101930349B (en)

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FR3048219B1 (en) * 2016-02-26 2020-12-25 Valeo Vision VEHICLE LIGHTING DEVICE WITH DRIVING ASSISTANCE INFORMATION PRESENTATION
CN110277052B (en) * 2019-06-13 2020-08-04 华中科技大学 Full-color L ED driving chip with multi-row scanning high refresh rate and driving method
WO2022021123A1 (en) * 2020-07-29 2022-02-03 西安钛铂锶电子科技有限公司 Display drive circuit and method, led display panel, and display apparatus
CN113763875A (en) * 2021-09-28 2021-12-07 福建捷联电子有限公司 Driving method and circuit for dual-mode modulation RGB LED
CN113936591B (en) * 2021-11-01 2023-06-09 四川启睿克科技有限公司 Display device driving circuit and driving method thereof

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Publication number Priority date Publication date Assignee Title
CN2302555Y (en) * 1997-07-08 1998-12-30 马卓钊 Scanning device with image storing and greyscale decoding outputting
CN1204919A (en) * 1997-07-08 1999-01-13 马卓钊 Scanning device with image storage and grey level decoding output
CN101345021A (en) * 2008-08-26 2009-01-14 福州大学 Image gray scale modulation method and driving circuit of field-enhanced emission display used for big screen
CN201788499U (en) * 2010-08-16 2011-04-06 深圳市洲明科技股份有限公司 Led scanning control chip device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2302555Y (en) * 1997-07-08 1998-12-30 马卓钊 Scanning device with image storing and greyscale decoding outputting
CN1204919A (en) * 1997-07-08 1999-01-13 马卓钊 Scanning device with image storage and grey level decoding output
CN101345021A (en) * 2008-08-26 2009-01-14 福州大学 Image gray scale modulation method and driving circuit of field-enhanced emission display used for big screen
CN201788499U (en) * 2010-08-16 2011-04-06 深圳市洲明科技股份有限公司 Led scanning control chip device

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