CN110277052B - Full-color L ED driving chip with multi-row scanning high refresh rate and driving method - Google Patents
Full-color L ED driving chip with multi-row scanning high refresh rate and driving method Download PDFInfo
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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Abstract
The invention discloses a multi-row scanning high-refresh-rate full-color L ED driving chip and a driving method, belonging to the field of full-color L ED driving chip design, wherein the driving method comprises a synchronous controller, a shift register, a state register, an SRAM buffer, a gray scale clock generation module, a driving module, a pre-charging circuit and an analog output module, the gray scale clock generation module is used for carrying out frequency multiplication/frequency division processing on a data clock signal DC L K according to instruction information to generate a gray scale clock signal GC L K for controlling gray scale, the driving module is used for counting the gray scale clock signal GC L K to obtain gray scale counting corresponding to each row of pixel data, and generating output waveforms of PWM signals corresponding to each row of pixel data by using continuous N rows of pixel data and corresponding gray scale counting in each scanning process to realize multi-row scanning, and the analog output module is used for receiving the PWM signals and generating and driving L ED lamp beads by matching with the pre-charging circuit.
Description
Technical Field
The invention belongs to the field of design of full-color L ED (electronic device) driving chips, and particularly relates to a full-color L ED driving chip with a multi-row scanning high refresh rate and a driving method.
Background
L ED (light Emitting Diode) is born in the 60's of the last century, and through development of over fifty years, L ED has lower and lower power consumption and higher effective brightness, and has the characteristics of long service life, high-speed response, low cost, environmental protection and the like, and is increasingly widely applied in the fields of traditional illumination display, aerospace, consumer products and the like.
In the display process of one frame time, under the condition of meeting the high gray scale display, even if the mode of scattering display and gating enabling by high and low weight bits is adopted for processing, the visual refresh rate does not exceed hundreds of hertz.
In order to ensure that L ED has good row gray scale, SPWM divides sub-periods, the number of gray clocks (GC L K) in a single sub-period cannot be too small, and because of the wiring frequency limitation of a L ED screen PCB, the total number of GC L K in one frame time is limited, in the traditional L ED driving chip, a gray clock signal is provided by an off-chip signal through a pin, so that under the condition of meeting high gray scale display, the visual refresh rate and the row scanning capability are restricted mutually, and high visual refresh rate and multi-row scanning cannot be realized simultaneously in practical application.
Disclosure of Invention
In view of the defects and the improvement requirement of the prior art, the invention provides a full-color L ED driving chip with multi-row scanning high refresh rate and a driving method thereof, aiming at improving the refresh rate and supporting more scanning rows.
To achieve the above object, according to a first aspect of the present invention, there is provided a multi-line scan full-color L ED driver chip with high refresh rate, comprising a synchronous controller, a shift register, a status register, an SRAM buffer, a gray scale clock generation module, a driving module, a pre-charge circuit, and an analog output module;
a synchronization controller having a first input for receiving a latch signal L E, a latch signal L E for indicating the type of input data, a first output for transmitting a latch signal L E to the shift register and the status register;
the shift register is used for identifying instruction data and pixel data from the serial input data SDI according to a latch signal L E and transmitting the instruction data and the pixel data to the state register and the SRAM buffer respectively;
the gray clock generation module is used for carrying out frequency multiplication/division processing on the data clock signal DC L K according to instruction information so as to generate a gray clock signal GC L K, and the gray clock signal is used for controlling gray levels;
the driving module is used for counting a gray clock signal GC L K to obtain a gray count corresponding to each row of pixel data, and generating an output waveform of a PWM signal corresponding to each row of pixel data by using the continuous N rows of pixel data and the corresponding gray count in each scanning process, so that multi-row scanning is realized;
the synchronous controller is further used for generating a line changing/frame changing signal, the line changing/frame changing signal is used for indicating to display a next line or a next frame of pixels, the input end of the pre-charging circuit is connected to the second output end of the synchronous controller, the first input end of the analog output module is connected to the output end of the driving module, the second input end of the analog output module is connected with the pre-charging circuit, and the pre-charging circuit is used for pre-charging a PWM signal used for driving a pixel line to be displayed under the indication of the line changing/frame changing signal, so that a multi-channel driving current is generated, and constant current driving of L ED lamp beads is achieved.
Compared with the traditional L ED driving chip in which a gray clock signal is provided from the outside of the chip through a pin, the gray clock signal GC L K in the full-color L ED driving chip with the multi-row scanning high refresh rate can reach higher frequency, and meanwhile, the frequency of the full-color L ED driving chip automatically tracks DC L K, so that the anti-interference capability is greatly improved, and the refresh rate and the number of scanning lines which can be supported are effectively improved.
Further, the gray clock generating module includes: the phase-locked loop comprises a phase-locked loop, a frequency multiplication unit, a first frequency division unit and a second frequency division unit;
the first input end of the frequency doubling unit is used as the second input end of the gray scale clock generation module, the second input end of the frequency doubling unit is connected to the output end of the phase-locked loop, and the frequency doubling unit is used for doubling the frequency of the data clock signal DC L K according to the coefficient P to obtain a frequency doubling signal and outputting the frequency doubling signal through the phase-locked loop;
the input end of the first frequency-dividing unit is connected to the output end of the phase-locked loop, and the first frequency-dividing unit is used for dividing the phase-locked loop according to a coefficient M1Dividing the frequency of the frequency-multiplied signal to obtain a frequency-divided signal;
the input end of the second frequency dividing unit is connected to the output end of the first frequency dividing unit, and the second frequency dividing unit is used for dividing the frequency according to a coefficient M2Frequency-dividing the frequency-divided signal so as to be satisfied
The gray scale clock signal GC L K;
wherein P is a dynamically configurable frequency multiplication coefficient, M1And M2For dynamically configurable division factor, fDCLKAnd fGCLKThe frequencies of the data clock signal DC L K and the gray clock signal GC L K, respectively.
The invention is a gray scale clock generation module composed of a phase-locked loop and three frequency division/frequency multiplication units, which passes through digital clockThe clock signal DC L K is divided/multiplied to generate a gray scale clock signal GC L K, wherein the multiplication factor P and the division factor M1And M2All the gray clock signals can be dynamically configured, so that the generated gray clock signal GC L K can reach higher frequency, better luminance efficiency can be ensured, the display time is matched with the frame interval time, and meanwhile, the frequency division operation is completed in two times, and the storage requirement of a register for storing the frequency division coefficient is reduced.
Further, R, G, B three-primary-color data are integrated in the pixel data, and R, G, B three-primary-color data are synchronously processed in the process of processing the pixel data.
The invention can reduce the required occupied PCB area, improve the number of output channels and provide possibility for realizing smaller lamp bead spacing for L ED display screen by integrating R, G, B three primary colors in one driving chip.
Further, a second input terminal of the synchronous controller is configured to receive a line feed signal ROW, where the line feed signal ROW has different high-level widths, and the synchronous controller is configured to generate a corresponding line feed/frame feed signal according to the high-level width of the line feed signal ROW.
The invention introduces a line-changing signal ROW through a pin, and generates a line-changing/frame-changing signal according to the line-changing signal ROW to indicate the start of scanning the next frame or the next line, even if the field synchronizing signal Vsync arrives, the display can be continued, thereby the frame-changing is unrelated to the field synchronizing signal Vsync, so that the longer waiting time can be avoided when the frame is changed, a frame interval removing technology is realized, and the refresh rate is improved.
The invention further provides a multi-row full-color L ED driving chip with high refresh rate, which further comprises an error state detection module, a refresh rate detection module and a refresh rate control module, wherein the input end of the error state detection module is connected with each output channel of the analog output module and is used for detecting the open circuit/short circuit state of L ED lamp beads and replacing the pixel data of dead pixels with 0 to eliminate the dead pixel cross phenomenon;
the error state detection module detects L open circuit/short circuit state of the ED lamp bead, and replaces the pixel data of the dead point with 0, thereby avoiding PWM output generated at the dead point and eliminating the dead point cross phenomenon.
Further, the driving module includes: the device comprises a counter, a butterfly scattering unit and a comparison unit;
the input end of the counter is used as the first input end of the driving module, and the counter is used for counting the gray clock signal GC L K to obtain the gray count corresponding to each row of pixel data;
the input end of the butterfly scattering unit is connected to the output end of the counter, and the butterfly scattering unit is used for dividing the gray count into K gray blocks according to a data block mode and rearranging the gray blocks in a butterfly scattering mode to obtain a block number sequence; each gray scale block corresponds to a gray scale clock count value, and the sum of the gray scale clock count values corresponding to all the gray scale blocks is equal to the gray scale count;
the first input end of the comparison unit is used as the second input end of the driving module, the second input end of the comparison unit is connected to the output end of the butterfly scattering unit, the comparison unit is used for dividing pixel data into K pixel blocks according to a block mode, and sequentially taking the gray blocks and the pixel blocks which are correspondingly numbered according to a block number sequence for comparison, so that an output waveform of a PWM signal is generated; each pixel block corresponds to a gray value, and the sum of the gray values corresponding to all the pixel blocks is equal to the pixel data;
and K is the number of the blocks corresponding to the block mode.
The method comprises the steps of generating a PWM signal, wherein the number of GC L K cycles needing to be started for a pixel block when the pixel block is displayed is represented by a pixel value corresponding to the pixel block, the pixel block is brighter when the pixel block is displayed, directly counting a gray clock signal GC L K when the PWM signal is generated in a traditional L ED driving chip, comparing the gray clock signal GC L K with pixel data to generate an output waveform of the PWM signal, and when the pixel data are displayed according to the method, the front half part of each line of pixel data are obviously brighter than the rear half part of each line of pixel data when the pixel data are displayed, so that a bright line bright spot phenomenon occurs.
According to a second aspect of the present invention, there is provided a driving method for a multi-row scan high refresh rate full-color L ED driver chip, the method including:
(1) counting the gray clock signal GC L K to obtain the gray count corresponding to each row of pixel data;
(2) dividing any line of pixel data to be displayed in the current scanning process into K pixel blocks according to a data block mode;
each pixel block corresponds to a gray value, and the sum of the gray values corresponding to all the pixel blocks is equal to the pixel data;
(3) dividing the gray scale count corresponding to the row of pixel data into K gray scale blocks according to a data block mode, and rearranging the K gray scale blocks in a butterfly scattering mode to obtain a block number sequence;
each gray scale block corresponds to a gray scale clock count value, and the sum of the gray scale clock count values corresponding to all the gray scale blocks is equal to the gray scale count;
(4) sequentially taking the gray-scale blocks with the corresponding numbers and the pixel blocks according to the block number sequence for comparison, thereby generating an output waveform of the PWM signal corresponding to the row of pixel data;
(5) for the continuous N rows of pixel data, steps (2) to (4) are respectively executed to obtain output waveforms of PWM signals corresponding to the pixel data of each row;
(6) displaying the pixel data of N continuous lines according to the data blocking result and the generated PWM signal, sequentially displaying the pixel blocks with the same number in the pixel data of the 1 st to N lines, and starting to display the pixel block with the next number in the block number sequence after the pixel block with one number in all the pixel data of N lines is completely displayed;
and K is the number of the blocks corresponding to the block mode.
According to the full-color L ED driving method provided by the invention, the gray scale blocks are scattered in a butterfly shape, and the pixel blocks are displayed according to the reordered numbering sequence, so that the brighter pixel blocks and the darker pixel blocks are displayed in a crossed manner, the gray scale of image display is more uniform, the problem of bright lines and bright spots is avoided, and the image quality is improved.
Further, the pixel value corresponding to the pixel block and the gray scale value corresponding to the gray scale block are not less than L;
wherein L is an integer power of 2.
When the PWM signal corresponding to each pixel block is started, level climbing time exists, and the level climbing time restricts the improvement of the refresh rate; according to the invention, by increasing the minimum length of the data blocks (namely the pixel values corresponding to the pixel blocks or the gray scale count values corresponding to the gray scale blocks), the number of the actually displayed pixel blocks can be effectively reduced, so that the total level climbing time is reduced, and a higher refresh rate can be realized.
Further, when each row of pixel data is displayed, the corresponding PWM signal is turned on at the end of the entire PWM driving phase.
L ED screen has a line-changing time when it is refreshed, the line-changing time includes the line shadow-eliminating discharge time of the previous line and the charging time of the new line, the PWM signal needs a pre-charging time before it is started, in the traditional L ED driving method, the PWM signal is started at the beginning of the whole PWM driving stage, the pre-charging can be completed only by the line-changing time, the line-changing time is not fixed, therefore, the pre-charging process can not be completed normally because of the short line-changing time, the invention can utilize the line-changing time and the first half time of the PWM driving stage to pre-charge by starting the PWM signal at the end of the whole PWM driving stage, thereby ensuring that there is enough pre-charging time to complete the pre-charging process and improving the response speed of the driving current.
Generally, by the above technical solution conceived by the present invention, the following beneficial effects can be obtained:
(1) according to the multi-row full-color L ED driving chip with high refresh rate, the frequency division/frequency multiplication is carried out in the chip according to the data clock signal DC L K to generate the gray clock signal GC L K, the obtained gray clock signal GC L K can reach higher frequency, the frequency automatically tracks DC L K, the anti-interference capacity is greatly improved, and the refresh rate and the number of scanning lines which can be supported are effectively improved.
(2) The multi-row full-color L ED driving chip with high refresh rate provided by the invention integrates R, G, B three primary colors in one driving chip, so that the area of a PCB (printed circuit board) required to be occupied can be reduced, the number of output channels is increased, and the possibility of realizing smaller lamp bead spacing for a L ED display screen is provided.
(3) The full-color L ED driving chip with multi-line scanning and high refresh rate introduces the line-change signal ROW through the pin, and generates the line-change/frame-change signal according to the line-change signal ROW to indicate the start of scanning the next frame or the next line, even if the field synchronizing signal Vsync arrives, the display can be continued, thereby the frame-change is unrelated to the field synchronizing signal Vsync, thereby avoiding longer waiting time when the frame is changed, realizing a frame interval removal technology and improving the refresh rate.
(4) According to the multi-row high-refresh-rate full-color L ED driving chip and the driving method, the gray-scale blocks are scattered in a butterfly mode, and the pixel blocks are displayed according to the reordered numbering sequence, so that the brighter pixel blocks and the darker pixel blocks are displayed in a crossed mode, the gray scale of image display is more uniform, the problem of bright lines and bright spots is avoided, and the image quality is improved.
(5) The driving method provided by the invention can effectively reduce the number of actually displayed pixel blocks by increasing the minimum length of the data blocks (namely the pixel values corresponding to the pixel blocks or the gray scale count values corresponding to the gray scale blocks), thereby reducing the total level climbing time and realizing higher refresh rate.
(6) According to the driving method provided by the invention, the PWM signal is started at the tail of the whole PWM driving stage, and the line feed time and the first half time of the PWM driving stage can be utilized for pre-charging, so that the pre-charging process is ensured to be completed within a long enough pre-charging time, and the response speed of the driving current is improved.
Drawings
FIG. 1 is a schematic diagram of an internal architecture of a multi-scan full-color L ED driver chip with a high refresh rate according to an embodiment of the present invention;
fig. 2 is a PWM data flow diagram generated by synchronously processing integrated R, G, B three primary color data and 48bit pixel data according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a conventional PWM generation method;
FIG. 4 is a schematic diagram of data partitioning according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a pixel data display according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the level-climbing time in the conventional PWM signal turn-on process
FIG. 7 is a diagram of a conventional PWM signal turn-on and a schematic diagram of the PWM signal turn-on provided by the embodiment of the present invention; wherein, (a) is a conventional PWM signal turn-on diagram, and (b) is a PWM signal turn-on diagram provided by the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The full-color L ED driving chip with multi-row scanning high refresh rate, as shown in FIG. 1, comprises a synchronous controller, a shift register, a status register, an SRAM buffer, a gray scale clock generation module, a driving module, a pre-charging circuit and an analog output module;
a synchronization controller having a first input for receiving a latch signal L E, a latch signal L E for indicating the type of input data, a first output for transmitting a latch signal L E to the shift register and the status register;
the shift register is used for identifying instruction data and pixel data from the serial input data SDI according to a latch signal L E and transmitting the instruction data and the pixel data to the state register and the SRAM buffer respectively;
the gray clock generation module is used for carrying out frequency multiplication/division processing on the data clock signal DC L K according to instruction information so as to generate a gray clock signal GC L K, and the gray clock signal is used for controlling gray levels;
the driving module is used for counting a gray clock signal GC L K to obtain gray counts corresponding to pixel data of each row, and generating PWM signals corresponding to the pixel data of each row by using the pixel data of N rows continuously and the corresponding gray counts in each scanning process, so that multi-row scanning is realized;
the synchronous controller is further used for generating a line changing/frame changing signal, the line changing/frame changing signal is used for indicating to display a next line or a next frame of pixels, the input end of the pre-charging circuit is connected to the second output end of the synchronous controller, the first input end of the analog output module is connected to the output end of the driving module, the second input end of the analog output module is connected with the pre-charging circuit, and the pre-charging circuit is used for pre-charging a PWM signal used for driving a pixel line to be displayed under the indication of the line changing/frame changing signal, so that a multi-channel driving current is generated, and constant current driving of L ED lamp beads is achieved.
The multi-line full-color L ED driving chip with high refresh rate performs frequency division/frequency multiplication according to a data clock signal DC L K inside the chip to generate a gray clock signal GC L K, so that the gray clock signal GC L K can reach higher frequency, meanwhile, the frequency of the full-color L ED driving chip automatically tracks DC L K, the anti-interference capability is greatly improved, and the refresh rate and the number of scanning lines which can be supported are effectively improved.
Optionally, in order to set the output channel current, the multi-row-scan high-refresh-rate full-color L ED driver chip shown in FIG. 1 may further include a digital-analog converter and a power-transmission current regulator, an input end of the digital-analog converter is connected to the status register, a first input end of the output current regulator is used for receiving a signal R-EXT, a second input end of the output current regulator is connected to an output end of the digital-analog converter, an output end of the output current regulator is connected to each output channel, the signal R-EXT is connected to an input end of an external resistor and used for setting the output channel current, and the output current regulator acquires the content in the status register through the digital-analog converter and adjusts the drive current of the output channel according to the content in the status register and the signal R-EXT.
Optionally, in order to further improve the picture quality, the multi-row high-refresh-rate full-color L ED driver chip shown in fig. 1 may further include an error state detection module, an input end of which is connected to each output channel of the analog output module, for detecting an open/short circuit state of L ED lamp beads, and replacing pixel data of dead pixels with 0 to eliminate a dead pixel cross phenomenon;
the error state detection module detects L open circuit/short circuit state of the ED lamp bead, and replaces the pixel data of the dead point with 0, thereby avoiding PWM output generated at the dead point and eliminating the dead point cross phenomenon.
In an optional embodiment, as shown in fig. 1, the gray clock generation module specifically includes: the phase-locked loop comprises a phase-locked loop, a frequency multiplication unit, a first frequency division unit and a second frequency division unit;
the first input end of the frequency doubling unit is used as the second input end of the gray scale clock generation module, the second input end of the frequency doubling unit is connected to the output end of the phase-locked loop, and the frequency doubling unit is used for doubling the frequency of the data clock signal DC L K according to the coefficient P to obtain a frequency doubling signal and outputting the frequency doubling signal through the phase-locked loop;
the input end of the first frequency-dividing unit is connected to the output end of the phase-locked loop, and the first frequency-dividing unit is used for dividing the phase-locked loop according to a coefficient M1Dividing the frequency of the frequency-multiplied signal to obtain a frequency-divided signal;
the input end of the second frequency dividing unit is connected to the output end of the first frequency dividing unit, and the second frequency dividing unit is used for dividing the frequency according to a coefficient M2Frequency-dividing the frequency-divided signal so as to be satisfied
The gray scale clock signal GC L K;
wherein P is a dynamically configurable frequency multiplication coefficient, M1And M2For dynamically configurable division factor, fDCLKAnd fGCLKFrequencies of the data clock signal DC L K and the gray clock signal GC L K, respectively;
the invention relates to a gray scale clock generation module consisting of a phase-locked loop and three frequency division/frequency multiplication units, which generates a gray scale clock signal GC L K by frequency division/frequency multiplication of a digital clock signal DC L K, wherein a frequency multiplication coefficient P and a frequency division coefficient M1And M2All can be dynamically configured, thereby ensuring the generated gray clockThe signal GC L K can reach higher frequency, can ensure better brightness efficiency, ensures that the display time is matched with the frame interval time, and simultaneously, completes frequency division operation in two times, and also reduces the storage requirement of a register for storing the frequency division coefficient.
In an alternative embodiment, the multi-row full-color L ED driver chip with high refresh rate shown in fig. 1 integrates R, G, B three-primary-color data into pixel data, and synchronously processes R, G, B three-primary-color data in the process of processing the pixel data;
the traditional L ED driving chip is only responsible for driving the lamp beads with one primary color, each lamp bead needs three chips to be driven independently to realize the driving of the three primary colors, and occupies a larger PCB area, the invention can reduce the required occupied PCB area and improve the number of output channels by integrating R, G, B three primary colors in one driving chip, and provides possibility for realizing smaller lamp bead space for a L ED display screen, for example, 16-bit single-primary-color pixel data is taken as an example, as shown in figure 2, a 48K-bit SRAM buffer (the specific storage space size is determined by the loading area of the chip) can be embedded into the chip to carry out ping-pong buffer processing, the 48-bit gray data is divided into 16-bit R, G, B to be driven separately when PWM signals are generated, and the chip supports the maximum 48-channel output.
In an alternative embodiment, as shown in fig. 1, the second input terminal of the synchronous controller is configured to receive a line feed signal ROW, where the line feed signal ROW has different high-level widths, and the synchronous controller is configured to generate a corresponding line feed/frame feed signal according to the high-level width of the line feed signal ROW;
the high level width of the line feed signal ROW may be specifically set according to the practical application requirement to identify the line feed or frame feed operation, for example, the high level width of the line feed signal ROW may be set to be 4 DC L K widths or 8 DC L K widths, where if the high level width of the signal ROW is 8 DC L K widths, the beginning of the first group of the first line (i.e. frame feed) is indicated, and the other cases (i.e. line feed) are 4 DC L K widths, in practical application, when the ROW lasts for the high level of 8 DC L K cycles, the high level of the next 4 DC L K cycles indicates that the display of the first group of the first line is to be performed, and the setting manner described herein is merely an exemplary description and should not be interpreted as a sole limitation to the present invention;
the invention introduces a line-changing signal ROW through a pin, and generates a line-changing/frame-changing signal according to the line-changing signal ROW to indicate the start of scanning the next frame or the next line, even if the field synchronizing signal Vsync arrives, the display can be continued, thereby the frame-changing is unrelated to the field synchronizing signal Vsync, so that the longer waiting time can be avoided when the frame is changed, a frame interval removing technology is realized, and the refresh rate is improved.
In an alternative embodiment, as shown in fig. 1, the driving module includes: the device comprises a counter, a butterfly scattering unit and a comparison unit;
the input end of the counter is used as the first input end of the driving module, and the counter is used for counting the gray clock signal GC L K to obtain the gray count corresponding to each row of pixel data;
the input end of the butterfly scattering unit is connected to the output end of the counter, and the butterfly scattering unit is used for dividing the gray count into K gray blocks according to a data block mode and rearranging the gray blocks in a butterfly scattering mode to obtain a block number sequence; each gray scale block corresponds to a gray scale clock count value, and the sum of the gray scale clock count values corresponding to all the gray scale blocks is equal to the gray scale count;
the first input end of the comparison unit is used as the second input end of the driving module, the second input end of the comparison unit is connected to the output end of the butterfly scattering unit, the comparison unit is used for dividing pixel data into K pixel blocks according to a block mode, and sequentially taking the gray blocks and the pixel blocks which are correspondingly numbered according to a block number sequence for comparison, so that an output waveform of a PWM signal is generated; each pixel block corresponds to a gray value, and the sum of the gray values corresponding to all the pixel blocks is equal to the pixel data; the comparison unit consists of a plurality of comparators, and each comparator is used for comparing one pixel block with the gray block with the same number;
k is the number of the blocks corresponding to the block mode;
the method comprises the steps of dividing a pixel Data sequence into GC L K cycles which need to be started for the pixel blocks when the pixel blocks are displayed, wherein the larger the pixel value corresponding to the pixel blocks is, the brighter the pixel blocks when the pixel blocks are displayed, taking 16-bit pixel Data (namely gray Data) as an example, if the pixel Data is 32800 and a counter is 24 bits, in a traditional PWM signal generation method, the counter counts a gray clock signal GC L K and compares the gray clock signal GC with the pixel Data to generate a PWM signal, as shown in FIG. 3, when the pixel Data of each row is displayed in the mode, the front half part is obviously brighter than the rear half part, so that a bright line bright spot phenomenon occurs, in the invention, the pixel Data is divided into blocks, taking 64 (namely, K is 64) blocks as an example, the pixel Data is divided into 512 blocks, the difference of the pixel values corresponding to each pixel block does not exceed the minimum unit block length (1) when the pixel Data of each row is displayed, the pixel Data is divided into 64 (namely, the blocks are 64) blocks, the pixel blocks are divided into 512-32 pixel blocks, the gray block numbers of which need to be increased after the pixel blocks are divided into GC 32K 2 blocks, the gray clock signal is divided into 512 pixel Data, the gray blocks, the pixel Data is divided into 512-32 blocks, the pixel Data after the gray blocks, the gray blocks are divided into 512 pixel blocks, the gray blocks are divided into 512 pixel blocks, the gray blocks are divided into 512 pixel Data is divided into 512 pixel blocks, the gray blocks are divided into 512 pixel Data is divided into 512 pixel blocks, the gray blocks are divided into 512 pixel blocks, the gray blocks, the pixel.
The butterfly scattering is used for reordering the numbers of the blocks, and the specific mode is that the numbers of the blocks are represented as binary systems according to a block mode, and then the high and low bits of the binary systems are reversed, so that the ordered number sequence is obtained; for example, the data is divided into 64 blocks, i.e. the original block number is 0-63, then the normal block number is represented as 6 bits in binary, which are 000000, 000001, 000010 … …, and after the high and low bits are reversed, the numbering sequence is 000000(0), 100000(32), 010000(16), … … 111111 (63); for another example, the data is divided into 32 blocks, i.e. the original block number is 0-31, then the normal block number is represented as 5 bits in binary, which are 00000, 00001, 00010 … …, and after the high and low bits are reversed, the numbering sequence is 00000(0), 10000(16), 01000(8), … … 11111 (31).
Based on the full-color L ED driving chip with multi-row scanning high refresh rate shown in FIG. 1, the driving method provided by the invention comprises the following steps:
(1) counting the gray clock signal GC L K to obtain the gray count corresponding to each row of pixel data;
(2) dividing any line of pixel data to be displayed in the current scanning process into K pixel blocks according to a data block mode;
each pixel block corresponds to a gray value, and the sum of the gray values corresponding to all the pixel blocks is equal to the pixel data;
(3) dividing the gray scale count corresponding to the row of pixel data into K gray scale blocks according to a data block mode, and rearranging the K gray scale blocks in a butterfly scattering mode to obtain a block number sequence;
each gray scale block corresponds to a gray scale clock count value, and the sum of the gray scale clock count values corresponding to all the gray scale blocks is equal to the gray scale count;
(4) sequentially taking the gray-scale blocks with the corresponding numbers and the pixel blocks according to the block number sequence for comparison, thereby generating an output waveform of the PWM signal corresponding to the row of pixel data;
(5) for the continuous N rows of pixel data, steps (2) to (4) are respectively executed to obtain output waveforms of PWM signals corresponding to the pixel data of each row;
(6) displaying the pixel data of N continuous lines according to the data blocking result and the generated PWM signal, sequentially displaying the pixel blocks with the same number in the pixel data of the 1 st to N lines, and starting to display the pixel block with the next number in the block number sequence after the pixel block with one number in all the pixel data of N lines is completely displayed;
and K is the number of the blocks corresponding to the block mode.
According to the above driving method, taking the blocking result shown in fig. 4 as an example, after performing butterfly scattering, the display sequence of the consecutive N rows of data is shown in fig. 5, specifically:
firstly, displaying the No. 0 block of the first line, then displaying the No. 0 block of the second line, and displaying the No. 0 block of the third line, No. 0 block … … of the Nth line;
then displaying the first line No. 32 block, the second line No. 32 block … … No. 32 block of the Nth line;
then displaying the No. 16 block of the first line, the No. 16 block … … of the second line and the No. 16 block of the Nth line;
then the first line No. 48 block, the second line No. 48 block … … No. 48 block of line N are displayed;
……
until all blocks are displayed completely;
according to the driving method, butterfly scattering is carried out on each row of pixel data and the corresponding gray scale counts, and the pixel blocks are displayed according to the scattered sequence, so that brighter pixel blocks and darker pixel blocks can be displayed in a crossed manner, the gray scale of image display is more uniform, the problem of bright lines and bright spots is avoided, and the image quality is improved.
In an optional embodiment, in the driving method, a pixel value corresponding to the pixel block and a gray scale value corresponding to the gray scale block are not less than L;
wherein L is an integer power of 2;
when the PWM signal corresponding to each pixel block is turned on, there is a level-climbing time, as shown in fig. 6, such a level-climbing time restricts the improvement of the refresh rate; according to the invention, by increasing the minimum length of the data blocks (namely the pixel values corresponding to the pixel blocks or the gray scale count values corresponding to the gray scale blocks), the number of the actually displayed pixel blocks can be effectively reduced, so that the total level climbing time is reduced, and a higher refresh rate can be realized;
with pixel Data122170, 64 blocks, L22Taking 4 as an example, the difference between the pixel values corresponding to the pixel blocks does not exceed the minimum block unit length (here, 4), and the pixel value corresponding to the pixel block with the smaller number is not less than the pixel value corresponding to the pixel block with the larger number, after the division is completed according to the Data division mode, the block with the number of 0 to 37 is opened for 87 GC L K periods with the minimum length (namely 87 ×) among 64 blocks obtained by Data division of the pixel Data1, the block with the number of 38 is opened for L K periods of GC 734, the block with the number of 38 is opened for L K periods of GC L K periods with the minimum length (namely 38786 Data 5 4), the block with the number of 39 to 63 is opened for 86 GC L K periods with the minimum length (namely 38786 Data 5), and the total 87 × × +86 × (64-38) × +2 is opened for 22170K periods, and when the pixel Data appears2If the minimum length is not set in the case of 4, the pixel Data2Will be distributed to 4 different sub-blocks, each sub-block will start 1 GC L K cycle, generate PWM needs to consume four times level of climbing time, if set the minimum length to L ═ 4, then the pixel Data2Will be allocated to only 1 sub-block with 4 GC L K cycles on, resulting in a ramp-up time where the PWM only consumes one level.
In an optional embodiment, in the driving method, when displaying pixel data of each row, the corresponding PWM signal is turned on at the end of the entire PWM driving phase;
l ED screen has a line-change time when it is refreshed, the line-change time includes the line shadow discharge time of the previous line and the charge time of the new line, the PWM signal needs a pre-charge time before it is started, in the traditional L ED driving method, the PWM signal is started at the beginning of the whole PWM driving stage, as shown in (a) in FIG. 7, the pre-charge can only be completed by the line-change time, but the line-change time is not fixed, therefore the pre-charge process can not be completed normally because the line-change time is too short, the invention can utilize the line-change time and the first half time of the PWM driving stage to pre-charge by starting the PWM signal at the end of the whole PWM driving stage, as shown in (b) in FIG. 7, thereby ensuring that there is enough pre-charge time to complete the pre-charge process and increasing the response speed of the driving current.
Generally speaking, the multi-row high-refresh-rate full-color L ED driving chip and the driving method provided by the invention have the advantages that the gray clock GC L K and a multi-channel (such as 48 channels in fig. 1) driving technology are obtained and generated in the chip, so that L ED lamp beads have higher refresh rate and better gray scale, the adopted internal gray clock GC L K frequency division/frequency multiplication technology supports up to 64 rows of scanning, and when R, G, B three-channel pixel data are integrated to achieve the constant current driving output of a single chip 48 channel, a L ED display screen can realize smaller lamp bead spacing.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A full-color L ED driving chip with multi-row scanning high refresh rate is characterized by comprising a synchronous controller, a shift register, a state register, an SRAM buffer, a gray scale clock generation module, a driving module, a pre-charging circuit and an analog output module;
the synchronization controller, a first input of which is used for receiving a latch signal L E, the latch signal L E is used for indicating the type of input data, the synchronization controller is used for transmitting the latch signal L E to the shift register and the state register through a first output of the synchronization controller;
the shift register is used for identifying instruction data and pixel data from the serial input data SDI according to the latch signal L E and transmitting the instruction data and the pixel data to the state register and the SRAM buffer respectively;
the first input end of the gray clock generation module is used for receiving the data clock signal DC L K, the second input end of the gray clock generation module is connected with the state register, and the gray clock generation module is used for performing frequency multiplication/frequency division processing on the data clock signal DC L K according to instruction information to generate a gray clock signal GC L K, wherein the gray clock signal is used for controlling gray scales;
the first input end of the driving module is connected to the output end of the gray clock generation module, the second input end of the driving module is connected to the SRAM buffer, and the driving module is configured to count the gray clock signal GC L K to obtain a gray count corresponding to each row of pixel data, and generate an output waveform of a PWM signal corresponding to each row of pixel data by using N consecutive rows of pixel data and the corresponding gray count in each scanning process, thereby implementing multi-row scanning;
the synchronous controller is also used for generating a line changing/frame changing signal which is used for indicating to display a next line or a next frame pixel, the input end of the pre-charging circuit is connected to the second output end of the synchronous controller, the first input end of the analog output module is connected to the output end of the driving module, and the second input end of the analog output module is connected with the pre-charging circuit which is used for pre-charging a PWM signal of a pixel line to be displayed under the indication of the line changing/frame changing signal so as to generate a multi-channel driving current and realize the constant current driving of an L ED lamp bead;
the driving module includes: the device comprises a counter, a butterfly scattering unit and a comparison unit;
the input end of the counter is used as the first input end of the driving module, and the counter is used for counting the gray clock signal GC L K to obtain the gray count corresponding to each row of pixel data;
the input end of the butterfly scattering unit is connected to the output end of the counter, and the butterfly scattering unit is used for dividing the gray scale count into K gray scale blocks according to a data blocking mode and rearranging the K gray scale blocks in a butterfly scattering mode to obtain a block numbering sequence; each gray scale block corresponds to a gray scale clock count value, and the sum of the gray scale clock count values corresponding to all the gray scale blocks is equal to the gray scale count;
the first input end of the comparison unit is used as the second input end of the driving module, the second input end of the comparison unit is connected to the output end of the butterfly scattering unit, the comparison unit is used for dividing pixel data into K pixel blocks according to the block mode, and sequentially taking the gray blocks and the pixel blocks which are correspondingly numbered according to the block number sequence for comparison, so that the output waveform of the PWM signal is generated; each pixel block corresponds to a gray value, and the sum of the gray values corresponding to all the pixel blocks is equal to the pixel data;
and K is the number of the blocks corresponding to the block mode.
2. The multi-scan high refresh rate full-color L ED driver chip of claim 1, wherein the gray scale clock generation module comprises a phase locked loop, a frequency doubling unit, a first frequency dividing unit, and a second frequency dividing unit;
the first input end of the frequency doubling unit is used as the second input end of the gray scale clock generation module, the second input end of the frequency doubling unit is connected to the output end of the phase-locked loop, and the frequency doubling unit is used for doubling the frequency of the data clock signal DC L K according to a coefficient P to obtain a frequency doubling signal and outputting the frequency doubling signal through the phase-locked loop;
the input end of the first frequency division unit is connected to the output end of the phase-locked loop, and the first frequency division unit is used for dividing the phase-locked loop according to a coefficient M1Dividing the frequency of the frequency multiplication signal to obtain a frequency division signal;
the input end of the second frequency dividing unit is connected to the output end of the first frequency dividing unit, and the second frequency dividing unit is used for dividing the frequency according to a coefficient M2Frequency-dividing the frequency-divided signal to obtain a frequency-divided signal satisfying
The gray scale clock signal GC L K;
wherein P is a dynamically configurable frequency multiplication coefficient, M1And M2For dynamically configurable division factor, fDCLKAnd fGCLKThe frequencies of the data clock signal DC L K and the gray clock signal GC L K, respectively.
3. The multi-row scan high refresh rate full-color L ED driver chip of claim 1 or 2, wherein R, G, B three primary color data are integrated into the pixel data, and R, G, B three primary color data are processed synchronously during the processing of the pixel data.
4. The multi-ROW scan high refresh rate full-color L ED driver chip as claimed in claim 1 or 2, wherein the second input terminal of the synchronous controller is used for receiving a line feed signal ROW having different high-level widths, and the synchronous controller is used for generating corresponding line/frame signals according to the high-level widths of the line feed signal ROW.
5. The multi-row scan high-refresh-rate full-color L ED driver chip of claim 1 or 2, further comprising an error detection module having an input connected to each output channel of the analog output module for detecting L open/short circuit status of the ED lamp bead and replacing the pixel data of dead pixel with 0 to eliminate dead pixel cross.
6. A driving method of a multi-row scan high refresh rate full-color L ED driver chip according to any of claims 1-5, comprising:
(1) counting the gray clock signal GC L K to obtain a gray count corresponding to each row of pixel data;
(2) dividing any line of pixel data to be displayed in the current scanning process into K pixel blocks according to a data block mode;
each pixel block corresponds to a gray value, and the sum of the gray values corresponding to all the pixel blocks is equal to the pixel data;
(3) dividing the gray scale count corresponding to the row of pixel data into K gray scale blocks according to the data block mode, and rearranging the K gray scale blocks in a butterfly scattering mode to obtain a block number sequence;
each gray scale block corresponds to a gray scale clock count value, and the sum of the gray scale clock count values corresponding to all the gray scale blocks is equal to the gray scale count;
(4) sequentially taking the gray-scale blocks with the corresponding numbers and the pixel blocks according to the block number sequence for comparison, thereby generating an output waveform of the PWM signal corresponding to the row of pixel data;
(5) for the continuous N rows of pixel data, steps (2) to (4) are respectively executed to obtain output waveforms of PWM signals corresponding to the pixel data of each row;
(6) displaying the pixel data of the continuous N lines according to the data blocking result and the generated PWM signal, so that the pixel blocks with the same number in the pixel data of the 1 st to N lines are sequentially displayed, and starting to display the pixel block with the next number in the block number sequence after the pixel block with one number in all the pixel data of the N lines is completely displayed;
and K is the number of the blocks corresponding to the block mode.
7. The driving method according to claim 6, wherein a pixel value corresponding to the pixel block and a gray scale value corresponding to the gray scale block are not less than L;
wherein L is an integer power of 2.
8. A method according to claim 6 or 7, wherein for each row of pixel data to be displayed, the corresponding PWM signal is turned on at the end of the entire PWM driving phase.
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