CN210245028U

CN210245028U - Image data output circuit and display circuit

Info

Publication number: CN210245028U
Application number: CN201921748278.1U
Authority: CN
Inventors: Yonggui Xiao; 肖永贵; Yuan Hu; 胡渊
Original assignee: Shenzhen Fuman Electronic Group Co ltd
Current assignee: Fuman Microelectronics Group Co ltd
Priority date: 2019-10-17
Filing date: 2019-10-17
Publication date: 2020-04-03
Anticipated expiration: 2029-10-17

Abstract

In the image data output circuit provided by the present invention, the output terminal of the gray counter is connected to an input terminal of the first comparator, the high M bit of the external input data is input to another input terminal of the first comparator, and the output terminal of the first comparator is connected to an input terminal of the or gate; the output end of the subframe counter is connected to one input end of the second comparator, the low N bits of the external input data are input to the other input end of the second comparator, and the output end of the second comparator is connected to the other input end of the OR gate; the external input data is M + N bits; the output end of the gray counter is connected to the clock end of the row counter, and the output end of the row counter is connected to the clock end of the subframe counter; the output end of the OR gate is connected with the column driving end of the LED screen, the circuit does not need to increase the frequency of a display counting clock, the characteristics of the original LED screen device are fully guaranteed, the screen flashing phenomenon is avoided, image data of more than 10 bits are completely displayed, and the display effect of the LED screen is improved.

Description

Image data output circuit and display circuit

Technical Field

The utility model belongs to the technical field of the LED, concretely relates to image data output circuit and display circuit.

Background

The LED screen has the advantages of high gray scale, wide visual angle, low working voltage, low power consumption, long service life, individuation customized shape and the like. Therefore, the LED screen is widely used in the fields of commercial advertisement, information distribution, and the like. As the quality of the LED screen display screen is required to be higher by the user, the level of the display data is also higher, and the display is from the earlier monochromatic 6Bit (binary) (RGB 6 bits each) display to the current monochromatic 16Bit (binary) (RGB 16Bit each).

Currently, the display driving of the LED screen generally uses a PWM (pulse width modulation control) technology. When the 16-Bit color needs to be displayed and distinguished, 65535 display clocks are needed for adjustment control, as shown in fig. 1. Assuming that one LED driver chip controls a display array of 32 rows and 16 columns, the frame rate refresh must be above 60HZ in order to achieve a display without flicker, which results in a PWM display count clock of up to 125MHZ (65535 x 32 x 60HZ), which corresponds to only 8ns per color difference. Considering the parasitic capacitance caused by the peripheral wiring and the turn-on time of the switching device, the LED cannot be turned on within 8ns, so that the required display effect cannot be achieved. If the frequency of the display count clock is lowered, the refresh rate of the required frame frequency cannot be satisfied, and a splash screen phenomenon occurs. If a simple low-order discarding method is adopted, the data of 16Bit is only displayed with 8Bit or 9Bit higher, thus causing image distortion and failing to display the data with smaller gray scale.

SUMMERY OF THE UTILITY MODEL

Therefore, the utility model aims at providing an image data output circuit and display circuit, under the prerequisite of guaranteeing that the display image picture does not have the scintillation, will exceed the complete demonstration of 10Bit image data and come out, promote the display effect of image.

In a first aspect, an image data output circuit includes: the device comprises a gray counter, a row counter, a subframe counter, a first comparator, a second comparator and an OR gate;

the output end of the gray counter is connected to one input end of the first comparator, the high M bit of the external input data is input to the other input end of the first comparator, and the output end of the first comparator is connected to one input end of the OR gate;

the output end of the subframe counter is connected to one input end of the second comparator, the low N bits of the external input data are input to the other input end of the second comparator, and the output end of the second comparator is connected to the other input end of the OR gate; the external input data is M + N bits;

the output end of the gray counter is connected to the clock end of the row counter, and the output end of the row counter is connected to the clock end of the subframe counter;

and the output end of the OR gate is connected with the column driving end of the LED screen.

Preferably, the gray counter comprises a series of M D flip-flops; in the gray scale counter, the clock end of a first D trigger is connected with an external clock source, the real output end of the previous D trigger is connected with the clock end of the next D trigger, the supplementary output end of each D trigger is connected with the data input end of the D trigger, and the real output ends of all D triggers are connected with one input end of the first comparator.

Preferably, the line counter comprises K series of D flip-flops, and the number p of lines of the display array in the LED screen is 2^K(ii) a The real output end of the last D trigger of the gray counter is connected with the clock end of the first D trigger in the line counter, the real output end of the previous D trigger in the line counter is connected with the clock end of the next D trigger, and the supplementary output end of each D trigger in the line counter is connected with the data input end of the D trigger.

Preferably, the subframe counter comprises a series of N D flip-flops; the real output end of the last D trigger in the row counter is connected with the clock end of the first D trigger in the subframe counter, the real output end of the previous D trigger in the subframe counter is connected with the clock end of the next D trigger, the supplementary output end of each D trigger in the subframe counter is connected with the data input end of the D trigger, and the real output ends of all the D triggers in the subframe counter are connected with one input end of the second comparator.

Preferably, the reset terminals of the D flip-flops are commonly connected to an external clear terminal.

In a second aspect, an image data display circuit,

q image data output circuits according to the first aspect are included, and q is the number of columns of a display array in the LED screen; and the output ends of the OR gates in all the image data output circuits are connected with different column driving ends of the LED screen.

The utility model provides an image data output circuit and display circuit need not to heighten and shows count clock frequency, and abundant having kept original LED screen device characteristic has solved the splash screen phenomenon, and the complete image data that shows more than 10 bits has promoted LED screen display effect.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below. In the drawings, elements or portions are not necessarily drawn to scale.

Fig. 1 is a circuit diagram of a display driver of an LED screen provided in the background art.

Fig. 2 is a block diagram of an image data output circuit according to an embodiment of the present invention.

Fig. 3 is a timing diagram after splitting of external input data according to a first embodiment of the present invention.

Fig. 4 is a circuit diagram of an image data output circuit according to a first embodiment of the present invention.

Fig. 5 is a circuit diagram of an image data display circuit according to a second embodiment of the present invention.

Fig. 6 is a timing diagram illustrating the data bits of the sub-frame counter after being inverted according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby.

The first embodiment is as follows:

referring to fig. 2, an image data output circuit includes a gray counter, a row counter, a subframe counter, a first comparator, a second comparator, and an or gate;

Specifically, assuming that the number of bits of the external input data is 16 bits, the external input data of 16 bits is split into two sets of data with M upper bits and N lower bits, for example, 7 upper bits and 9 lower bits. As shown in FIG. 3, FIG. 3 divides an entire frame of data of 16 bits into 512 (2)⁹) Each sub-frame is divided into 32 rows, and each row displays the gray scale of 128 (2)⁷) One clock cycle. The gray counter of external input data of 7 bits high is compared with the gray counter of 7 bits, the first comparator is used for outputting PWM1, the sub-frame counter of external input data of 9 bits low is compared with the sub-frame counter of 9 bits, the second comparator is used for outputting PWM2, PWM2 is the supplementary display of PWM1, and the supplementary display only occupies one clock width in one sub-frame at most.

It can be seen from FIG. 3 that the external input data of row 1, high 7 bits and low 9 bits, are both not 0, so both PWM1 and PWM2 have outputs; the external input data for row 2 is 0 at 7 bits high and 0 at 9 bits low, so no output is from PWM1 and output is from PWM 2; the external input data on row 32 is not 0 for 7 bits high and 0 for 9 bits low, so PWM1 has an output and PWM2 has no output; finally, PWM1 is either identical to PWM2 or output from OUT.

According to the image data output circuit, external input data are split into two sections, the high-order part displays gray scale through a conventional PWM method, the low-order part is split to supplement the gray scale in a subframe, the display counting clock frequency is not required to be increased, the characteristics of the original LED screen device are fully maintained, the problem of screen flashing is solved, image data exceeding 10 bits are completely displayed, and the display effect of the LED screen is improved.

Referring to fig. 4, the gray counter includes M D flip-flops connected in series; in the gray scale counter, the clock end of a first D trigger is connected with an external clock source, the real output end of the previous D trigger is connected with the clock end of the next D trigger, the supplementary output end of each D trigger is connected with the data input end of the D trigger, and the real output ends of all D triggers are connected with one input end of the first comparator.

The line counter comprises K D triggers connected in series, and the number p of lines of a display array in the LED screen is 2^K(ii) a The real output end of the last D trigger of the gray counter is connected with the clock end of the first D trigger in the line counter, the real output end of the previous D trigger in the line counter is connected with the clock end of the next D trigger, and the supplementary output end of each D trigger in the line counter is connected with the data input end of the D trigger.

The subframe counter comprises N D triggers which are connected in series; the real output end of the last D trigger in the row counter is connected with the clock end of the first D trigger in the subframe counter, the real output end of the previous D trigger in the subframe counter is connected with the clock end of the next D trigger, the supplementary output end of each D trigger in the subframe counter is connected with the data input end of the D trigger, and the real output ends of all the D triggers in the subframe counter are connected with one input end of the second comparator.

And the reset ends of the D triggers are connected to the external zero clearing end together.

Specifically, as can be seen from fig. 4, assuming that the number of bits of the external input data is 16 bits, the external input data of 16 bits is split into two sets of data of 7 upper bits and 9 lower bits. Then 7D flip-flops are needed for the gray counter, 5D flip-flops are needed for the row counter, and 9D flip-flops are needed for the sub-frame counter. And the line counter is used for detecting whether all lines in the display array of the LED screen are scanned completely, and when all lines in the display array are scanned completely, the subframe counter is increased by 1 to show that the display of one subframe is complete.

Specifically, when the circuit inputs high data in externally input data to the first comparator, the gradation counter starts counting. The high M Bit of the externally input data is compared with the gray scale counter, and when the high data is larger than the gray scale counter, the PWM1 outputs 1.

For example, the external input data of 16 bits is divided into two groups of data of upper 7 bits and lower 9 bits, and each row displays the gray scale of 128 clock cycles. Assuming that the high data in the externally input data is 10, the high data is detected to be larger than the gray scale counter in the first 10 clock widths, the PWM1 outputs a high level of 10 clock widths, and after entering the 11 th clock width, the high data is detected to be smaller than the gray scale counter, and the PWM1 then outputs a low level of 117 clock widths. When the last clock is entered, supplementary display of 1 clock width is performed according to the low-bit data in the external input data.

And when all the lines in all the LED screens are scanned, adding 1 to the subframe counter. And when the lower data is greater than the reverse order of the subframe counter, if the output of the first comparator is 1 in the previous clock, the output of the second comparator is 1, and otherwise, the output of the second comparator is 0. And then the output values of the first comparator and the second comparator are output after the output values are output.

Suppose that: the external input data A is M + N bits, and the data A is expanded by a 2-system, namely:

A＝M_M+N-1*2^(M+N-1)+…+M_N+1*2^(N+1)+M_N*2^N+M_N-1*2^(N-1)+…+M₁*2¹+M₀*2⁰①；

the high order data of the external input data a is set as B,

B＝M_N+M-1*2^(N+M-1)+…+M_N+1*2^(N+1)+M_N*2^N②；

B＝(M_N+M-1*2^(M-1)+…+M_N+1*2¹+M_N*2⁰)*2^N③；

the lower bits of the external input data a are set to C,

C＝M_N-1*2^(N-1)+…+M₁*2¹+M₀*2⁰④；

A＝B+C ⑤；

in the

formulae

①, ②, ③, ④, M_n-1To M₀Is 0 or 1; external input data A divided into 2^NDisplaying the number of subframes, wherein high M Bit data B of the external input data A is output after each subframe is normally compared with a gray scale counter, the gray scale displayed by the high Bit data B is shown as a formula ②, low N Bit data C of the external input data A is compared with the subframe counter in each subframe, each subframe is supplemented with one gray scale display at most, and the gray scale display 2 at most is displayed after all the low N Bit data C are accumulated^N-1The gray levels are shown in formula ④, so that the gray level of the external input data A can be completely displayed as shown in formula ⑤.

The data bits of the sub-frame counter are reversed for display uniformity and better display effect. As shown in FIG. 6, when the externally inputted data A is gray scale 4, the sub-frame counter is sequentially compared, 4 display gray scales are displayed in the first 4 frames, and when the sub-frame counter is reversely compared, 4 display gray scales are uniformly distributed in 2^N-1And displaying in sub-frames, for example, the first clock display distributed in the corresponding line display positions in the 1 st sub-frame, the 128 th sub-frame, the 256 th sub-frame and the 384 th sub-frame in fig. 6.

Example two:

referring to fig. 5, an image data display circuit,

q image data output circuits are included, and q is the number of columns of a display array in the LED screen; and the output ends of the OR gates in all the image data output circuits are connected with different column driving ends of the LED screen.

Specifically, as can be seen from fig. 5, fig. 5 drives an LED panel with a display array of S rows and 16 columns. Then 16 of the above-described image data output circuits are required to drive 16 column-driving terminals in the LED panel. The display array of the LED screen can be set according to the requirements of users, and the image data display circuit can set the number of the image data output circuits according to the display array of the LED screen.

For the circuit provided by the embodiment of the present invention, for the sake of brief description, the corresponding contents in the foregoing embodiments can be referred to.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the scope of the embodiments of the present invention, and are intended to be covered by the claims and the specification.

Claims

1. An image data output circuit, comprising: the device comprises a gray counter, a row counter, a subframe counter, a first comparator, a second comparator and an OR gate;

2. The image data output circuit according to claim 1,

the gray counter comprises M D triggers which are connected in series; in the gray scale counter, the clock end of a first D trigger is connected with an external clock source, the real output end of the previous D trigger is connected with the clock end of the next D trigger, the supplementary output end of each D trigger is connected with the data input end of the D trigger, and the real output ends of all D triggers are connected with one input end of the first comparator.

3. The image data output circuit according to claim 2,

4. The image data output circuit according to claim 3,

5. The image data output circuit according to claim 4,

6. An image data display circuit characterized in that,

comprising q image data output circuits according to any of claims 1 to 5, q being the number of columns of the display array in the LED panel; and the output ends of the OR gates in all the image data output circuits are connected with different column driving ends of the LED screen.