CN110599951B - Image data output circuit, display circuit and method - Google Patents
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
Abstract
The invention provides an image data output circuit, wherein the output end of a gray counter is connected to one input end of a first comparator, the high M bit of external input data is input to the other input end of the first comparator, and the output end of the first comparator is connected to one input end of an OR gate; the output end of the subframe counter is connected to one input end of the second comparator, the low N bits of the external input data are input to the other input end of the second comparator, and the output end of the second comparator is connected to the other input end of the OR gate; the external input data is M+N bits; the output end of the gray counter is connected to the clock end of the line counter, and the output end of the line counter is connected to the clock end of the subframe counter; the output end of the OR gate is connected with the column driving end of the LED screen, the circuit does not need to heighten the display counting clock frequency, the characteristics of the original LED screen device are fully guaranteed, the screen flashing phenomenon is solved, the image data exceeding 10Bit are completely displayed, and the display effect of the LED screen is improved.
Description
Technical Field
The invention belongs to the technical field of LEDs, and particularly relates to an image data output circuit, a display circuit and a method.
Background
The LED screen has the advantages of high gray scale, wide visual angle, low working voltage, low power consumption, long service life, personalized customization of shape and the like. Therefore, the LED screen is widely used in the fields of commercial advertising, information release and the like. As the quality requirements of users on LED screen display pictures are higher and higher, the level of display data is higher and higher, from early monochrome 6Bit (binary) (RGB 6 bits each) display to current monochrome 16Bit (binary) (RGB 16 bits each) display.
Currently, PWM (pulse width modulation) technology is commonly used for LED screen display driving. When it is necessary to display a color of 16Bit, 65535 display clocks are required for adjustment control, as shown in fig. 1. Assuming that one LED driving chip controls the display array of 32 rows and 16 columns, in order to achieve no flicker of display, the frame rate refresh must be above 60HZ, so that the display count clock of PWM needs to be up to 125MHZ (65535×32×60 HZ), which is equivalent to only 8ns time for each color difference. Considering parasitic capacitance caused by peripheral wiring and the turn-on time of the switching device itself, the 8ns time cannot light the LED, so that the required display effect cannot be achieved. If the frequency of the display count clock is lowered, the refresh rate of the required frame rate cannot be satisfied, and thus a screen flicker phenomenon occurs. If the simple low-order discarding method is adopted, the 16Bit data is only displayed at the high 8Bit or 9Bit, thus causing the distortion of the image picture and the data with smaller gray scale can not be displayed.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the image data output circuit, the display circuit and the method, which can completely display the image data exceeding 10Bit on the premise of ensuring that the displayed image does not flicker, thereby improving the display effect of the image.
In a first aspect, an image data output circuit includes: a gray counter, a line counter, a subframe counter, a first comparator, a second comparator, and an or gate;
the output end of the gray counter is connected to one input end of the first comparator, the high M bits of the external input data are input to the other input end of the first comparator, and the output end of the first comparator is connected to one input end of the OR gate;
the output end of the subframe counter is connected to one input end of the second comparator, the low N bits of the external input data are input to the other input end of the second comparator, and the output end of the second comparator is connected to the other input end of the OR gate; the external input data is M+N bits;
the output end of the gray counter is connected to the clock end of the line counter, and the output end of the line counter is connected to the clock end of the subframe counter;
the output end of the OR gate is connected with the column driving end of the LED screen.
Preferably, the gray counter comprises M D flip-flops in series; in the gray counter, the clock end of the first D trigger is connected with an external clock source, the real output end of the former D trigger is connected with the clock end of the latter D trigger, the complementary output end of each D trigger is connected with the data input end of the latter D trigger, and the real output ends of all D triggers are connected with one input end of the first comparator.
Preferably, the row counter comprises K D flip-flops connected in series, and the row number p=2 of the display array in the LED screen K The method comprises the steps of carrying out a first treatment on the surface of the The real output end of the last D trigger of the gray counter is connected with the clock end of the first D trigger in the row counter, the real output end of the previous D trigger in the row counter is connected with the clock end of the next D trigger, and the complementary output end of each D trigger in the row counter is connected with the data input end of the next D trigger.
Preferably, the subframe counter comprises N D flip-flops connected in series; the real output end of the last D trigger of the row counter is connected with the clock end of the first D trigger in the subframe counter, the real output end of the previous D trigger in the subframe counter is connected with the clock end of the next D trigger, the complementary output end of each D trigger in the subframe counter is connected with the data input end of the same, and the real output ends of all the D triggers in the subframe counter are connected with one input end of the second comparator.
Preferably, the reset terminal of the D flip-flop is commonly connected to an external clear terminal.
In a second aspect, an image data display circuit,
the display device comprises q image data output circuits according to the first aspect, wherein q is the number of columns of a display array in the LED screen; the output ends of the OR gates in all the image data output circuits are connected with different column driving ends of the LED screen.
In a third aspect, an image data display method, which operates on the image data output circuit of the first aspect, includes the steps of:
splitting external input data into M-bit high-order data and N-bit low-order data;
the first comparator compares high-order data in the external input data with the gray counter, and outputs 1 when the high-order data is larger than the gray counter, otherwise outputs 0;
after all rows in the display array of the LED screen are scanned, adding 1 to the subframe counter;
the data bits of the subframe counter are subjected to reverse order;
the second comparator compares low-order data in the external input data with the inverted subframe counter, and outputs 1 when the low-order data is larger than the inverted subframe counter, otherwise outputs 0;
and after the output end of the first comparator and the output end of the second comparator are subjected to phase OR, the OR gate drives the column driving end of the LED screen.
Preferably, the column driving end of the LED screen is greater than 10.
According to the technical scheme, the image data output circuit, the display circuit and the method provided by the invention have the advantages that the display counting clock frequency does not need to be increased, the characteristics of the original LED screen device are fully maintained, the screen flash phenomenon is solved, the image data exceeding 10Bit is completely displayed, and the display effect of the LED screen is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Like elements or portions are generally identified by like reference numerals throughout the several figures. In the drawings, elements or portions thereof are not necessarily drawn to scale.
Fig. 1 is a circuit diagram of an LED screen display driver provided in the background art.
Fig. 2 is a block diagram of an image data output circuit according to an embodiment of the present invention.
Fig. 3 is a timing chart of an external input data splitting according to an embodiment of the invention.
Fig. 4 is a circuit diagram of an image data output circuit according to an embodiment of the invention.
Fig. 5 is a circuit diagram of an image data display circuit according to a second embodiment of the present invention.
Fig. 6 is a timing chart showing the reverse sequence of the data bits of the subframe counter according to the third embodiment of the present invention.
Detailed Description
Embodiments of the technical scheme of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and thus are merely examples, and are not intended to limit the scope of the present invention. It is noted that unless otherwise indicated, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Embodiment one:
referring to fig. 2, an image data output circuit includes a gray counter, a line counter, a sub-frame counter, a first comparator, a second comparator, and an or gate;
the output end of the gray counter is connected to one input end of the first comparator, the high M bits of the external input data are input to the other input end of the first comparator, and the output end of the first comparator is connected to one input end of the OR gate;
the output end of the subframe counter is connected to one input end of the second comparator, the low N bits of the external input data are input to the other input end of the second comparator, and the output end of the second comparator is connected to the other input end of the OR gate; the external input data is M+N bits;
the output end of the gray counter is connected to the clock end of the line counter, and the output end of the line counter is connected to the clock end of the subframe counter;
the output end of the OR gate is connected with the column driving end of the LED screen.
Specifically, assuming that the number of bits of the external input data is 16 bits, the external input data of 16 bits is split into two sets of data of upper M bits and lower N bits, for example, upper 7 bits and lower 9 bits. As shown in fig. 3, fig. 3 divides a whole frame of 16Bit data into 512 (2 9 ) Each sub-frame is divided into 32 lines, and each line displays 128 (2 7 ) For a clock cycle. Comparing gray level counters of 7Bit and 7Bit of external input data, outputting PWM1 by using a first comparator, comparing sub-frame counters of 9Bit and 9Bit of external input data, outputting PWM2 by using a second comparator, wherein PWM2 is complementary display of PWM1, and the complementary display occupies only one clock width at most in one sub-frame.
As can be seen from fig. 3, the external input data of row 1 is not 0 at high 7Bit and low 9Bit, so PWM1 and PWM2 have outputs; the external input data of the 2 nd row has a high 7Bit of 0 and a low 9Bit of not 0, so PWM1 has no output and PWM2 has an output; the external input data of the 32 nd row is high 7Bit and low 9Bit is 0, so PWM1 has output, PWM2 has no output; finally, PWM1 and PWM2 phases or outputs from OUT.
According to the image data output circuit, external input data are split into two sections, the high-order part displays gray scales through a conventional PWM method, the low-order part is split to supplement and display gray scales in a subframe, the display counting clock frequency is not required to be increased, the characteristics of an original LED screen device are fully maintained, the screen flashing phenomenon is solved, the image data exceeding 10Bit are completely displayed, and the display effect of an LED screen is improved.
Referring to fig. 4, the gray counter includes M D flip-flops connected in series; in the gray counter, the clock end of the first D trigger is connected with an external clock source, the real output end of the former D trigger is connected with the clock end of the latter D trigger, the complementary output end of each D trigger is connected with the data input end of the latter D trigger, and the real output ends of all D triggers are connected with one input end of the first comparator.
The row counter comprises K D flip-flops connected in series, and the row number p=2 of the display array in the LED screen K The method comprises the steps of carrying out a first treatment on the surface of the The real output end of the last D trigger of the gray counter is connected with the clock end of the first D trigger in the row counter, the real output end of the previous D trigger in the row counter is connected with the clock end of the next D trigger, and the complementary output end of each D trigger in the row counter is connected with the data input end of the next D trigger.
The subframe counter comprises N D triggers which are connected in series; the real output end of the last D trigger of the row counter is connected with the clock end of the first D trigger in the subframe counter, the real output end of the previous D trigger in the subframe counter is connected with the clock end of the next D trigger, the complementary output end of each D trigger in the subframe counter is connected with the data input end of the same, and the real output ends of all the D triggers in the subframe counter are connected with one input end of the second comparator.
The reset ends of the D triggers are commonly connected to an external zero clearing end.
Specifically, as can be seen from fig. 4, assuming that the number of bits of the external input data is 16 bits, the external input data of 16 bits is split into two sets of data of upper 7 bits and lower 9 bits. Then the gray counter requires 7D-flip-flops, the line counter requires 5D-flip-flops, and the sub-frame counter requires 9D-flip-flops. The line counter is used for detecting whether all lines in the display array of the LED screen are scanned, and when all lines in the display array are scanned, the subframe counter is increased by 1 to indicate that the display of one complete subframe is completed.
Embodiment two:
referring to fig. 5, an image data display circuit,
the LED display device comprises q image data output circuits, wherein q is the number of columns of a display array in an LED screen; the output ends of the OR gates in all the image data output circuits are connected with different column driving ends of the LED screen.
Specifically, as can be seen from fig. 5, fig. 5 shows an LED screen with an array of 16 columns and S rows. Then 16 of the above image data output circuits are required to drive 16 column driving terminals in the LED panel. The display array of the LED screen can be set according to the requirements of users, and the image data display circuit can set the number of the image data output circuits according to the display array of the LED screen.
For a brief description, reference may be made to the corresponding contents of the foregoing embodiments for the circuit provided in the embodiments of the present invention.
Embodiment III:
an image data display method, which is operated on the image data output circuit, includes the steps of:
splitting external input data into M-bit high-order data and N-bit low-order data;
the first comparator compares high-order data in the external input data with the gray counter, and outputs 1 when the high-order data is larger than the gray counter, otherwise outputs 0;
after all rows in the display array of the LED screen are scanned, adding 1 to the subframe counter;
the data bits of the subframe counter are subjected to reverse order;
the second comparator compares low-order data in the external input data with the inverted subframe counter, and outputs 1 when the low-order data is larger than the inverted subframe counter, otherwise outputs 0;
and after the output end of the first comparator and the output end of the second comparator are subjected to phase OR, the OR gate drives the column driving end of the LED screen.
Preferably, the column driving end of the LED screen is greater than 10.
Specifically, in the image data display method, when high-order data in the external input data is input to the first comparator, the gradation counter starts counting. The high M Bit of the external input data is compared with the gray counter, and when the high data is larger than the gray counter, PWM1 outputs 1.
For example, the external input data of 16Bit is split into two groups of data of upper 7 bits and lower 9 bits, and each row displays 128 clock cycles of gray scale. Assuming that the high-order data in the externally input data is 10, the high-order data is detected to be larger than the gray counter in the first 10 clock widths, PWM1 outputs a high level of 10 clock widths, and after the 11 th clock width is entered, the high-order data is detected to be smaller than the gray counter, PWM1 then outputs a low level of 117 clock widths. When the last clock is entered, 1 clock width supplementary display is performed according to low order data in the external input data.
After all rows in all LED screens are scanned, the subframe counter is increased by 1. In order to display uniformity, the data bits of the sub-frame counter are inverted, the low-order data of the externally input data is compared with the inverted sequence of the sub-frame counter, and when the low-order data is larger than the inverted sequence of the sub-frame counter, if the output of the first comparator is 1 in the previous clock, the second comparator outputs 1, otherwise, the second comparator outputs 0. And then outputting the output values of the first comparator and the second comparator.
Assume that: the external input data A is M+N bits, and the data A is expanded by using a 2 system, namely:
A＝M M+N-1 *2 (M+N-1) +…+M N+1 *2 (N+1) +M N *2 N +M N-1 *2 (N-1) +…+M 1 *2 1 +M 0 *2 0 ①；
the external input data a high-order data is set to B,
B＝M N+M-1 *2 (N+M-1) +…+M N+1 *2 (N+1) +M N *2 N ②；
B＝(M N+M-1 *2 (M-1) +…+M N+1 *2 1 +M N *2 0 )*2 N ③；
the external input data a low-order data is set to C,
C＝M N-1 *2 (N-1) +…+M 1 *2 1 +M 0 *2 0 ④；
A＝B+C ⑤；
in the formulas (1), (2), (3) and (4), M n-1 To M 0 0 or 1; the external input data a is divided into 2 N The display of the subframe number, the high M Bit data B of the external input data A is output after each subframe is normally compared with a gray counter, and the gray scale displayed by the high Bit data B is shown as a formula (2); the low N Bit data C of the external input data A is compared with a subframe counter in each subframe, each subframe is supplemented with at most one gray level display, and the total accumulated data is displayed for at most 2 N-1 Gray scales as shown in formula (4); the gray scale of the external input data a can be displayed entirely as shown in formula (5).
For uniformity of display and better display effect, the data bits of the subframe counter are in reverse order. As shown in fig. 6, when the external input data a is gray level 4, the sub-frame counters are sequentially compared, 4 display gray levels are displayed in the first 4 frames, and when the sub-frame counters are reversely compared, 4 display gray levels are uniformly distributed in 2 N-1 The display is performed in subframes, for example, in fig. 6, the first clock display is respectively distributed in the display positions of the corresponding rows in the 1 st subframe, the 128 th subframe, the 256 th subframe and the 384 th subframe.
For a brief description of the method provided by the embodiments of the present invention, reference may be made to the corresponding content in the foregoing embodiments where the description of the embodiments is not mentioned.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention, and are intended to be included within the scope of the appended claims and description.
Claims (8)
1. An image data output circuit, comprising: a gray counter, a line counter, a subframe counter, a first comparator, a second comparator, and an or gate;
the output end of the gray counter is connected to one input end of the first comparator, the high M bits of the external input data are input to the other input end of the first comparator, and the output end of the first comparator is connected to one input end of the OR gate;
the output end of the subframe counter is connected to one input end of the second comparator, the low N bits of the external input data are input to the other input end of the second comparator, and the output end of the second comparator is connected to the other input end of the OR gate; the external input data is M+N bits;
the output end of the gray counter is connected to the clock end of the line counter, and the output end of the line counter is connected to the clock end of the subframe counter;
the output end of the OR gate is connected with the column driving end of the LED screen;
the gray counter comprises M D flip-flops connected in series; the row counter comprises K D flip-flops connected in series, and the row number p=2 of the display array in the LED screen K The method comprises the steps of carrying out a first treatment on the surface of the The subframe counter comprises N D triggers which are connected in series; the external input data is divided into 2 N The display of the number of subframes, the low-N Bit data of the external input data is compared with a subframe counter in each subframe, and each subframe is supplemented with one gray scale display at most.
2. The image data output circuit according to claim 1, wherein,
in the gray counter, the clock end of a first D trigger is connected with an external clock source, the real output end of the former D trigger is connected with the clock end of a later D trigger, the complementary output end of each D trigger is connected with the data input end of the latter D trigger, and the real output ends of all D triggers are connected with one input end of the first comparator.
3. The image data output circuit according to claim 2, wherein,
the real output end of the last D trigger of the gray counter is connected with the clock end of the first D trigger in the row counter, the real output end of the previous D trigger in the row counter is connected with the clock end of the next D trigger, and the complementary output end of each D trigger in the row counter is connected with the data input end of the next D trigger.
4. The image data output circuit according to claim 3, wherein,
the real output end of the last D trigger of the row counter is connected with the clock end of the first D trigger in the subframe counter, the real output end of the previous D trigger in the subframe counter is connected with the clock end of the next D trigger, the complementary output end of each D trigger in the subframe counter is connected with the data input end of the same, and the real output ends of all the D triggers in the subframe counter are connected with one input end of the second comparator.
5. The image data output circuit according to claim 4, wherein,
the reset ends of the D triggers are commonly connected to an external zero clearing end.
6. An image data display circuit, characterized in that,
the image data output circuit according to any one of claims 1 to 5, wherein q is the number of columns of the display array in the LED screen; the output ends of the OR gates in all the image data output circuits are connected with different column driving ends of the LED screen.
7. An image data display method, characterized by being run on the image data output circuit of any one of claims 1 to 5, comprising the steps of:
splitting external input data into M-bit high-order data and N-bit low-order data;
the first comparator compares high-order data in the external input data with the gray counter, and outputs 1 when the high-order data is larger than the gray counter, otherwise outputs 0;
after all rows in the display array of the LED screen are scanned, adding 1 to the subframe counter;
the data bits of the subframe counter are subjected to reverse order;
the second comparator compares low-order data in the external input data with the inverted subframe counter, and outputs 1 when the low-order data is larger than the inverted subframe counter, otherwise outputs 0;
and after the output end of the first comparator and the output end of the second comparator are subjected to phase OR, the OR gate drives the column driving end of the LED screen.
8. The method for displaying image data according to claim 7, wherein,
the column driving end of the LED screen is larger than 10.
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