KR20160080768A - Display Device And Driving Method for the Same - Google Patents

Abstract

The present invention relates to a displaying device and an operating method thereof capable of flicker prevention and reduction of power consumption by lowering a refresh rate depending on the state of inputted images and gradation. The displaying device comprises: a display panel including multiple gate lines and data lines crossing each other to define a pixel; a timing controller with a refresh rate setting unit for setting the information about refresh rates of pixels based on the state of images or videos and the level of gradation after receiving image data of the pixels from the system; a gate driver for controlling the period of gate signals in each line by receiving the information about the refresh rate; and a data driver for providing image signals for the data lines by receiving the information about the refresh rate.

Description

[0001] The present invention relates to a display device and a method of driving the same,

The present invention relates to a display apparatus, and more particularly, to a display apparatus and a driving method thereof that simultaneously reduce a power consumption and a flicker by setting a refresh rate differently depending on whether the input image is stopped or not.

Recently, a display field that visually expresses electrical information signals has rapidly developed as the information age has come to a full-scale information age. In response to this, a variety of flat display devices having excellent performance such as thinning, light weight, And is rapidly replacing existing CRT (Cathode Ray Tube).

Specific examples of such a flat panel display include a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), an electroluminescent display Electro Luminescence Display Device (ELD), and the like. In general, a flat panel display panel, which realizes an image, is an essential component. The flat panel display panel has a pair of material layers having inherent light emission or optical anisotropy Of the transparent insulating substrate facing each other.

On the other hand, the above-mentioned flat panel display device is driven at a specific frequency such as 60 Hz for display. Recently, there has been a demand for reducing power consumption by varying the driving frequency for each frame depending on the type of image.

However, since the pulse period for each gate line is long when driven with a low frequency, a discharge time between frames inverted to different polarities is long, a charge leakage value is large in a pixel, and a residual DC value becomes large. There is a phenomenon that occurs. Since such a flicker is proportional to? Vp, there is a problem that the longer the discharge time, that is, the longer the cycle, the more noticeable the flicker phenomenon.

Thus, although the low-frequency driving has an advantage of reducing the power consumption, it is difficult to solve the flicker phenomenon, which is difficult to apply.

In this case, when the image displayed on the screen is partly moving and some part is still image, the method of controlling the frequency per frame needs to be consistently driven at a high frequency. In this case, There is a problem that the power consumption is large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device and a method of driving the same that simultaneously reduce a refresh rate and a flicker by setting a refresh rate differently depending on whether the input image is stopped or not, .

According to another aspect of the present invention, there is provided a display apparatus including a display panel including a plurality of gate lines and data lines crossing each other and defining pixels, A timing controller which has a refresh rate setting section for setting refresh rate information for each pixel row in relation to the stop / moving image presence / absence and gradation levels, a gate driver for receiving the refresh rate information and controlling the cycle of the gate signal for each line, And a data driver for supplying a video signal to the data lines.

The refresh rate setting unit may include a line memory for storing image data for each pixel row from the system, an idling discriminating unit for discriminating the still image and the moving image of the image data for each pixel row, And a first and a second gray discrimination unit for discriminating a gray level for each video and a moving image.

The above-described method of driving a display device includes a first step of storing image data for each pixel row from the system, a second step of segmenting the still image and the moving image of the image data for each pixel row, When the data is a still image, the gray level is discriminated, and a timing signal is output at a low refresh rate when the gradation level is higher than the first gradation level, at an intermediate refresh rate, and when the gradation level is lower than the first gradation level And a third step of, when the video data for each pixel row is a moving image, discriminating a gray level, and when the gradation level is higher than the second gradation level, at a high refresh rate and at a lower gradation level than the second gradation level, A step of outputting a timing signal at an intermediate refresh rate, and a step of outputting a timing signal to the video data of the pixel row obtained in the third and fourth steps By passing a signal to the gate driver and the data driver, and a fifth step of adjusting the gate line by the refresh rate.

The display apparatus and the driving method thereof according to the present invention having the above-described features are characterized in that the refresh rate driven by each gate line (per pixel row connected thereto) is set differently so that when the still image is partially present on the screen, The necessary parts are driven at the timing of the refresh rate, and the remaining part is driven at the timing of the low refresh rate, so that the power consumption in the timing controller and the data driver can be drastically reduced.

Further, in order to prevent flicker phenomenon from occurring at the time of expressing a high gradation level at a low refresh rate, a high gradation level of a low refresh rate can increase the refresh rate to be driven, thereby preventing the occurrence of flicker.

That is, it is possible to perform spatial division according to still image / moving image / partial moving image on one screen, thereby maximizing reduction of power consumption and preventing flickering.

1 is a block diagram showing a display apparatus according to the present invention;
2 is a block diagram showing the timing controller of FIG. 1 and its interface
3 is a block diagram illustrating an internal configuration of a data driver connected to the timing controller of FIG.
FIG. 4 is a block diagram showing an example of a refresh rate setting unit for each line in FIG.
5 is a flowchart showing a driving method of a display apparatus according to the present invention.
6 is a photograph showing the driving of the display device of the present invention
7 is a graph showing Vp-p changes at 20 Hz refresh driving and gray gradation at 60 Hz refresh driving

Hereinafter, a display apparatus and a driving method thereof according to the present invention will be described with reference to the accompanying drawings.

Hereinafter, the liquid crystal display device will be described as a typical example of the display device, but the present invention is not limited thereto, and other types of flat panel display devices such as an organic light emitting display device, a plasma display panel (PDP), a field emission display device (FED), an electrophoretic display device, and the like.

That is, according to the present invention, the refresh rate is set for each pixel line (horizontal line), and the refresh rate can be varied depending on whether the input image is a pixel-by-pixel image, The present invention can be applied to a structure having a plurality of gate lines and a plurality of data lines and having a driving driver therefor.

FIG. 1 is a block diagram showing a display apparatus of the present invention, and FIG. 2 is a block diagram showing an interface between the timing controller and the timing controller of FIG.

1, the display device of the present invention includes a display unit (DSP), a system 300, a timing controller 22, a data driver 24, and a gate driver 30.

The display unit DSP includes i * j (i, j is a natural number greater than 1) pixels PX, i data lines, and j gate lines GL1 to GLj in a kind of panel do. Here, first to j-th gate signals are applied to the first to j-th gate lines GL1 to GLj, respectively, and a data voltage is input to each of the first to i-th data lines DL1 to DLj .

The display unit DSP may be a liquid crystal panel, an organic light emitting display panel, or an electrophoretic display panel.

These pixels PX are arranged in a matrix on the display unit DSP. These pixels PX are divided into a red pixel R for displaying red, a green pixel G for displaying green, and a blue pixel B for displaying blue. At this time, the red pixels, the green pixels and the blue pixels R, G, B adjacent in the horizontal direction are unit pixels for displaying one unit image.

Here, when the display device of the present invention is a liquid crystal display device, the pixel may be composed of a thin film transistor, a pixel electrode, a common electrode, a liquid crystal, or the like.

I pixels (hereinafter, the nth horizontal line pixels) arranged along the nth horizontal line (n is any one of 1 to j) are individually connected to the first to i-th data lines DL1 to DLi And is connected through a TFT (Thin Film Transistor) (not shown). In addition, the n-th horizontal line pixels are connected in common to the n-th gate line through each TFT. Thus, the n-th horizontal line pixels are supplied with the n-th gate signal in common. That is, all the i pixels arranged on the same horizontal line are supplied with the same gate signal, but the pixels located on different horizontal lines are supplied with different gate signals. For example, while the red pixel R, the green pixel G and the blue pixel B located in the first horizontal line HL1 are all supplied with the first gate signal, The red pixel R, the green pixel G and the blue pixel B are supplied with a second gate signal having a different timing from them. That is, the rising points of the gate signals are different.

The above-described j gate signals have a gate-on time of the same time width, but have a low-level time width of the gate output enable signal GOE per gate line applied from the timing controller 22 , So that the refresh rate of each can be different. For example, the refresh rate is divided into a low frequency, an intermediate frequency, and a high frequency according to whether a video / still image of video data to be input per horizontal line pixel in the timing controller 22 and a gradation level are different. In this case, if the frame is a 60 Hz frame, the low frequency can be set to 1 Hz, the intermediate frequency to 20 to 30 Hz, and the high frequency to 60 Hz. In the case of a moving image, it is first set to an intermediate frequency or more, and is compared with a specific gradation level capable of flicker identification. If the gradation level is below a specific gradation level, the intermediate refresh rate is set to a high refresh rate. In the case of a still image, it is set to be equal to or lower than the intermediate frequency, and compared with a specific gradation level capable of identifying the flicker again. If the gradation level is higher than a specific gradation level, Setting. Here, the specific gradation levels for the still image and the moving image may be the same or may be different. In this case, the respective intermediate frequency values may be different.

Meanwhile, the system 300 outputs the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the clock signal DCLK, and the image data R / G / B through the interface circuit through the transmitter of the graphic controller . The vertical / horizontal synchronizing signal and the clock signal output from the system 300 are supplied to the timing controller 22. Image data (Image data) sequentially output from the system 300 is supplied to the timing controller 22.

2, the timing controller 22 includes an interface 210 to which video data and a timing signal are input from the system 300, and a stop / A refresh rate setting unit 220 for setting a refresh rate information for each line in accordance with a moving image and a gradation level and a refresh rate setting unit 220 for setting a refresh rate set by the clock signal from the interface 210 and the refresh rate setting unit 220 And a timing signal generator 230 for outputting the gate output enable signal GOE and the source output enable signal SOE according to the rate information. The input image for each pixel row from the interface 210 outputs the digital video signal R / G / B data and the polarity signal POL for each pixel row through the refresh rate setting unit 220 .

Although image data and timing signals are directly input from the system 300 to generate signals for timing and driving of the gate driver 30 and the data driver 24 through internal processing, It may be preferable to provide the interface 210 at the input terminal as shown in FIG. The interface 210 may be a low voltage differential signaling (LVDS) receiver, and may further include an LVDS transmitter at the output of the system 300. The interface 210 may be another type of internal interface instead of LVDS.

A horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, a data enable DE, a clock DCLK and image data Data are input from the system 300 through the interface 210. The vertical synchronizing signal (Vsync) represents the time required for displaying the screen of one frame. The horizontal synchronization signal Hsync indicates the time required to display one horizontal line of the screen, that is, one pixel line.

Therefore, the horizontal synchronizing signal includes pulses as many as the number of pixels included in one pixel row (horizontal line). The data enable signal DE indicates the period during which valid video data is located for each pixel row. The timing controller 22 rearranges the video data so that video data (Data) of a predetermined bit supplied from the interface can be supplied to the data driver 24. The timing controller 22 receives the horizontal synchronizing signal Hsync, the vertical synchronizing signal Vsync, the data enable DE and the clock signal DCLK from the interface to receive the data control signal DCS, A gate output enable signal GOE and a gate control signal GCS to the data driver 24 and the gate driver 30. [

In general, each gate output enable signal GOE is applied in the form of shifting a pulse signal having the same pulse width for each gate line in a scheme driven at the same refresh rate for each pixel row, It is possible to change the refresh rate depending on the type of the image and the gradation state of the image, and it is possible to change the cycle of the gate output enable signal GOE of each gate line . That is, for example, the gate lines are divided into blocks and divided into a low refresh rate, an intermediate refresh rate, or a high refresh rate, ) To each of the gate lines G1, G2, and G3. For example, a gate line to which a gate output enable signal is applied at a high refresh rate of the same rate as that of a frame at 60 Hz has a total refresh gate rate of 60 times at a high refresh rate of 60 Hz as compared with a gate output enable signal GOE However, the gate line to which the gate output enable signal GOE is applied at a low refresh rate of 1 Hz generates one gate output enable signal. Accordingly, the data of the pixel rows connected to the respective gate lines are applied 60 times and the number of times of 1 times, respectively, so that it is possible to perform spatial division by region. When the refresh rate is relatively low, The amount of data input to the driver 24 can be reduced and the amount of processing in the data driver 24 can be reduced to reduce power consumption. Here, the adjustment of the data application by the pixel row may be performed according to the change of the high level and the low level of the source output enable signal SOE in the timing controller 22. For example, when the source output enable signal SOE is at a high level, data is supplied to the data lines. When the source output enable signal SOE is at a low level, data supply to the data lines is prevented. The source output enable signal SOE for each pixel row corresponds to the generation of the corresponding gate output enable signal GOE and can be shifted for a predetermined time.

3 is a block diagram showing an internal configuration of a data driver connected to the timing controller of FIG.

In the drawing, the data driver 24 is provided with one corresponding to the pixel row, but may be provided on the display panel by being divided into a plurality of data drive ICs.

3, the data control signal DCS supplied to the data driver 24 includes a source sampling clock signal SSC, a source output enable signal SOE, a source start pulse signal SSP: Source Start Pulse, and Polarity reverse (POL) signal.

The data driver 24 includes a shift register SR, a first latch unit LT1, a second latch unit LT2, a multiplexer MUX and a digital-analog converter DAC and a buffer unit BFU. .

The shift register SR sequentially generates the sampling signal based on the source start pulse signal SSP and the source sampling signal SSC.

The source sampling clock signal SSC is used as a sampling clock for latching the image data in the data driver 24 and is set according to the highest refresh rate among the refresh rates applied to the pixel rows.

The first latch unit LT1 sequentially samples the image data of one horizontal line according to the sampling signal from the shift register SR and latches the sampled image data. The second latch unit LT2 simultaneously latches the image data sampled from the first latch unit LT1 in accordance with the rising edge of the source output enable signal SOE and performs a polling of the source output enable signal SOE And simultaneously outputs the sampling image data latched at the edge point. The cycle of the source output enable signal SOE may be different for each line. That is, for the pixel rows driven at a low refresh rate, the source output enable signal SOE can be applied at a cycle of several times or several tens times for pixel rows driven at different high refresh rates.

The multiplexer MUX simultaneously receives the sampling image data from the second latch unit LT2 and relocates the output position of the sampling image data according to the polarity inversion signal POL.

On the other hand, the source output enable signal SOE causes the image data latched by the source sampling clock signal SSC to be transmitted to the display unit. The source start pulse signal SSP is a signal indicating the start of latching or sampling of image data during one horizontal period. If a predetermined gate line is applied with a gate output enable signal GOE at a low refresh rate, The source output enable signal SOE can be applied only once to the high level level. The polarity reversal signal POL is a signal indicating the polarity of the data voltage (analog signal to the image data) to be supplied to the pixel for inversion driving of the display device, and for the pixel rows with different refresh rates, The polarity reversal signal POL can be applied at a different number of times. That is, the polarity reversal signal POL is inverted more than the pixel rows of the high refresh rate and the pixel rows of the low refresh rate.

The digital-analog converter (DAC) converts the sampling image data provided from the multiplexer (MUX) into data voltages which are analog signals. And includes a positive polarity digital analog converter and a negative polarity analog converter, and is converted into a positive or negative polarity data voltage by using the input polarity gradation voltages (GMA).

In addition, the buffer unit BFU buffers and outputs the positive data voltages and the negative data voltages provided from the digital-analog converter (DAC).

FIG. 4 is a block diagram showing one embodiment of a refresh rate setting unit for each line in FIG. 2, and FIG. 5 is a flowchart showing a driving method of the display device of the present invention.

4, the line-by-line refresh rate setting unit 220 includes a line memory 221 for storing video data for each pixel line from the system 300, And the first and second gray discriminators 224a and 224b for discriminating the gray levels of the still image and the moving image, respectively.

Here, the information about the first gradation level, which is a reference of the determination of the gray level of the still image, and the second gradation level, which is a reference of the determination of the gray level of the still image, (LUT). The first and second gradation levels can be set to a value at which the flicker is identified by observing the flicker phenomenon in advance according to the frequency and gradation level of the corresponding display panel model.

The driving method of the display apparatus of the present invention using the line-by-line refresh rate setting unit 220 is as follows.

That is, as in 5, first, image data for each pixel row is stored from the system (100S).

Then, the still image and the moving image of the image data for each pixel row are discriminated (110S).

If the image data for each pixel row is a still image, the gray level is discriminated (120S). At this time, when the gradation level is higher than the first gradation level, the timing signals GOE and SOE are output at an intermediate refresh rate (122S). If the gray level of the image data is lower than the first gray level, the timing signals GOE and SOE are output at a low refresh rate 125S.

If the video data for each pixel row is a moving image, the gray level is discriminated (130S).

At this time, when the gradation level is higher than the second gradation level, the timing signals GOE and SOE are output at a high refresh rate (132S). If the gray level of the image data is lower than the second gradation level, the timing signal is outputted at the intermediate refresh rate (135S).

Then, the timing signal (GOE, SOE) for the video / still image discrimination and the gray-level discrimination of the video data for each pixel row are transmitted to the gate driver 30 and the data driver 24, (Pixel rows).

Here, the high refresh rate is a maximum frequency of each moving picture frame of the display panel, and may be, for example, 60 Hz or a multiple thereof. The low refresh rate corresponds to the still image and the low gradation level in the display panel and may be, for example, 1 Hz.

As described above, the intermediate refresh rate may be set so that the low gradation level of the moving image and the high gradation level of the still image are set to be the same or different from each other. The intermediate refresh rate may be about 10 Hz to 50 Hz, and may be set differently between them, and may be the lowest gradation level at which the flicker is identified in the look-up table of the corresponding model.

A screen to which the driving method of the display apparatus of the present invention described above is applied will be described with reference to Fig.

6 is a photograph showing driving of the display device of the present invention.

As shown in Fig. 6, in one screen, a fixed background such as a sky or a rock without motion can be treated as a still image. However, the high gradation level brightly expressed as sky is large in the pixel charge leakage in the section in which the image signal is inverted during the low-frequency driving, and therefore the flicker phenomenon may occur, and therefore, the determination unit of the refresh rate setting unit , The refresh rate was increased from 20 to 30 Hz, which is a level at which flicker is not identified rather than a low refresh rate such as 1 Hz.

On the other hand, in a region close to a black background, such as a rock, a region at a lower end has a low gradation level to be represented, so that a change in DELTA V in a section where a video signal is inverted is small and a flicker phenomenon is not observed even when driven at a low frequency, .

In addition, in the region where the movement of the penguin appears, the high-speed driving is performed like the 60 Hz, and the expression of the movement is facilitated.

On the other hand, in the judgment of the refresh rate setting section, the refresh rate is set in accordance with the moving image when the video data of the pixel row is mixed with the moving image and the still image, and the high gray- , The refresh rate is set in accordance with the high gradation level. That is, when the moving picture of the penguin and the part of the building with the bright color background are present together at the center of the screen of Fig. 6, a refresh rate of 60 Hz is set to sufficiently express the moving picture.

7 is a graph showing changes in Vp-p according to the gray scale during the 20 Hz refresh rate driving and the 60 Hz refresh rate driving.

RGB (0, 0, 0) is represented by a low gradation level indicating black in the range of RGB (0, 0, 0) to RGB (255, 255, 255) , And RGB (255, 255, 255) corresponds to a high gradation indicating white.

As shown in Fig. 7, the change width of the inter-frame Vp-p (DELTA Vp) is not large at a refresh rate of relatively high frequency of 60 Hz, but when the refresh rate is 20 Hz and the low frequency, It is expected that the Vp-p change width is large and the inter-frame pixel charge leakage is large, which can be expected to easily identify the flicker phenomenon. Therefore, in the method of driving a display device of the present invention, the gradation level is not set to a low frequency for a still image, and when a high gradation level is required to be expressed, a level at which flicker is not identified The refresh rate is increased.

That is, in the display apparatus and the driving method of the present invention, the refresh rate driven by each gate line (per pixel row connected thereto) is set differently, and when the still image is partially present on the screen, It is possible to drive at the timing of the high refresh rate and drive the remaining portions at the timing of the low refresh rate, thereby remarkably reducing the power consumption in the timing controller and the data driver.

Further, in order to prevent flicker phenomenon from occurring at the time of expressing a high gradation level at a low refresh rate, a high gradation level of a low refresh rate can increase the refresh rate to be driven, thereby preventing the occurrence of flicker.

That is, it is possible to perform spatial division according to still image / moving image / partial moving image on one screen, thereby maximizing reduction of power consumption and preventing flickering.

In some cases, the timing is set to be lower than the intermediate frequency with respect to the still image in the timing diagram of Fig. 5, but when the flicker of the still image is severe at the high gradation level, the drive refresh rate may be further raised to the high refresh rate.

In the above example, the low refresh rate is set to 1 Hz and the high refresh rate is set to 60 Hz. However, the present invention is not limited to this, and the range can be adjusted. The application of the present invention is not limited to the characteristic of a specific frequency, but rather that the driving refresh rate may be different for each line (horizontal pixel row) and that the adjustment of the video / .

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

22: timing controller 24: data driver
30: gate driver 210: interface
220: Line-by-line refresh rate setting unit 230: Timing signal generator
221: line memory 222:
224a: first gray level discrimination section 224b: second gray level discrimination section
300: System 100: Display

Claims (9)

A display panel including a plurality of gate lines and data lines crossing each other and defining pixels;
A timing controller having a refresh rate setting unit for receiving the video data for each of the plurality of pixel rows from the system and setting the refresh rate information for each pixel row with respect to the video stop /
A gate driver receiving the refresh rate information and controlling a cycle of a gate signal for each line; And
And a data driver receiving the refresh rate information and supplying a video signal to the data lines. The method according to claim 1,
Wherein the refresh rate setting unit comprises:
A line memory for storing image data for each pixel row from the system;
An idling discrimination unit for discriminating a still image and a moving image of the image data for each pixel row; And
Wherein the image data for each pixel row includes first and second gray discriminators for discriminating gray levels of a still image and a moving image, respectively. 3. The method of claim 2,
Wherein the first and second gray discrimination sections output timing signals of different refresh rates for respective pixel rows. The method of claim 3,
Wherein the timing signal includes a gate output enable signal and a source output enable signal, and wherein the gate output enable signal and the source output enable signal are transmitted to a gate driver and a data driver, respectively. The method of claim 3,
Wherein the first gray discriminator outputs a timing signal at an intermediate refresh rate when the gray level of the still image is higher than the first gray level and a timing signal with a lower refresh rate when the gray level of the still image is lower than the first gray level. 6. The method of claim 5,
Wherein the second gray discriminator outputs a timing signal of an intermediate refresh rate when the gray level of the moving image is higher than a second gray level and at a higher refresh rate and lower than a second gray level. The method according to claim 6,
Wherein the refresh rate setting unit of the timing controller further includes a lookup table for information on the first gradation level and the second gradation level. A method of driving a display device including a plurality of gate lines and data lines crossing each other and defining pixels,
A first step of storing image data for each pixel row from the system;
A second step of separating the still image and the moving image of the image data for each pixel row;
When the image data for each pixel row is a still image, determines a gray level, and when the gradation level is higher than the first gradation level, at an intermediate refresh rate, when the gradation level is lower than the first gradation level, A third step of outputting a timing signal;
And when the image data for each pixel row is a moving image, the gray level is discriminated, and when the gradation level is higher than the second gradation level, at a high refresh rate and at a lower gradation level than the second gradation level, A fourth step of outputting a signal; And
And a fifth step of transferring a timing signal for the pixel data for each pixel row obtained in the third and fourth steps to the gate driver and the data driver to adjust the refresh rate for each gate line. A method of driving a device. 9. The method of claim 8,
Wherein the first gradation level is a gradation level at which a flicker of a still image is identified and the second gradation level is a gradation level at which flicker of a moving image is identified.

Images