KR102278743B1 - Liquid Crystal Display and Driving Method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device.
A liquid crystal display device according to the present invention outputs a data voltage to the data lines during a low logic period of a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect, and the source output enable signal, and the source output enable signal A data driver that short-circuits the adjacent data lines to perform charge share during a high logic period of . Transmits input image data to the data driving circuit, and defines an output timing of the data voltage and a timing of the charge share. A timing controller that generates a source output enable signal and a predetermined specific type of problem pattern are detected in the input image, and when the problem pattern is detected, the source output is enabled based on a change in gradation between the vertically adjacent data. and an afterimage improvement unit for varying the high logic section of the enable signal.

Description

Liquid Crystal Display and Driving Method thereof

The present invention relates to a liquid crystal display device and a driving method thereof.

A display device is applied to various information devices or office devices as a transmission medium of visual information. In the past, CRTs using cathode ray tubes were mainly used, but in recent years, flat panel display devices with significantly reduced weight and volume have been widely used. Flat panel displays include Liquid Crystal Display (LCD), Field Emission Display (FED), Plasma Display Panel (PDP), and Organic Light Emitting Diode Device (OLED). ), etc.

A liquid crystal display is a display device that displays luminance according to the degree of deflection of liquid crystals formed on a liquid crystal panel. The degree to which the liquid crystal is deflected in the liquid crystal display device is determined by the difference between the data voltage applied to the pixel and the common voltage.

The data voltage is sequentially supplied to the horizontal lines of the liquid crystal panel by the data driver. For example, as shown in FIG. 1 , the data line DLi of column i sequentially supplies the data voltage to the m-th horizontal line Hm and the (m+1)-th horizontal line H(m+1). At this time, a ripple is induced in the common voltage Vcom by a difference in data voltages sequentially provided between horizontal lines. For example, as shown in the figure, if a voltage of '127' is provided to the m-th horizontal line (Hm) and a voltage of '0' is provided to the (m+1)-th horizontal line [H(m+1)], A ripple is induced in the common voltage in a section in which the voltage output through the data line DLi is changed. These ripples cause a linear afterimage in the horizontal direction, thereby degrading the display quality of the liquid crystal display.

An object of the present invention is to provide a liquid crystal display device for improving ripple induced by a data voltage difference between horizontal lines.

A liquid crystal display device according to the present invention outputs a data voltage to the data lines during a low logic period of a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect, and the source output enable signal, and the source output enable signal A data driver that short-circuits the adjacent data lines to perform charge share during a high logic period of . Transmits input image data to the data driving circuit, and defines an output timing of the data voltage and a timing of the charge share. A timing controller that generates a source output enable signal and a predetermined specific type of problem pattern are detected in the input image, and when the problem pattern is detected, the source output is enabled based on a change in gradation between the vertically adjacent data. and an afterimage improvement unit for varying the high logic section of the enable signal.

The method of driving a liquid crystal display according to the present invention comprises a first step of storing data of an input image in a line memory for each horizontal line, and determining whether an input image is a problem pattern image based on the amount of data change in each memory area of the line memory and a third step of adjusting the width of the high logic section of the source output enable signal when the problem pattern image is input.

According to the present invention, the amount of change between the initial voltage and the data voltage can be minimized in the section where the data voltage is changed by adjusting the charge share section. Accordingly, it is possible to improve the induction of ripple in the common voltage in the section in which the data voltage is changed, and it is possible to prevent the generation of a linear afterimage due to the ripple.

1 is a schematic diagram illustrating a phenomenon in which a ripple is induced.
2 is a view showing a liquid crystal display device according to the present invention.
3 is a block diagram showing the configuration of an afterimage improvement unit according to the present invention.
4 is a diagram showing a data driving circuit according to the present invention.
5 is a view showing a charge share unit according to the present invention.
6 is a flowchart illustrating a method of driving a liquid crystal display according to the present invention.
7 and 8 are schematic diagrams for explaining a pattern analysis method of an input image.
9 to 12 are diagrams illustrating a relationship between a charge share time and a ripple according to a change in a reference gradation.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

2 is a view showing a liquid crystal display device according to the present invention.

Referring to FIG. 2 , the liquid crystal display according to the present invention includes an afterimage improvement unit 10 , a liquid crystal panel 20 , a timing controller 30 , a data driving circuit 50 , and a gate driving circuit 40 . .

The afterimage improving unit 10 improves a phenomenon in which a ripple is generated due to a coupling phenomenon with a common voltage line due to a change amount of the data voltage. To this end, the afterimage improvement unit 10 detects a problem pattern of a specific type preset in the input image, and when the problem pattern is detected, the high logic section width of the source output enable signal based on the grayscale change between vertically adjacent data. change the The afterimage improving unit 10 adjusts the width of the source output enable signal so as to minimize a difference between the voltage charged in the previous horizontal line and the voltage charged in the current horizontal line.

The afterimage improvement unit 10 adjusts the width of the high logic section of the source output enable signal SOE when receiving a problem pattern image in which the gradation between vertically adjacent pixels in the input image is greater than or equal to a threshold value, thereby reducing the charge share section. Adjust.

To this end, the afterimage improvement unit 10 includes a line memory 11 , a pattern analysis unit 13 , and a signal control unit 15 as shown in FIG. 3 .

The line memory 11 stores the data of the input image for each horizontal line.

The pattern analysis unit 13 determines whether the input image is the problem pattern image based on the data stored in the line memory 11 .

The pattern analysis unit 13 determines whether the data for each pixel sequentially stored in the line memory 11 belongs to the reference gray level, and determines whether the input image is a problem pattern based on the amount of change in the reference gray level between adjacent horizontal lines. judge In this case, the reference grayscale is a representative value selected from the grayscale range displayed by the liquid crystal panel 20 , and may include, for example, a low grayscale, a middle grayscale, and a high grayscale. The low gray level may be set to a gray level of '0' indicating black or a range value including '0'. The high gray level may be set as a range value including the maximum luminance for displaying white, for example, a '255' gray level or a '255' gray level. In addition, the middle grayscale may be set as an average value of the low grayscale and the high grayscale or a range value including the average value.

When data provided to an adjacent horizontal line changes from a specific reference grayscale to another reference grayscale, the pattern analyzer 13 regards a pixel receiving data of a different reference grayscale as a pattern pixel. In addition, the pattern analysis unit 13 determines the input image as a problem pattern image when the number of pattern pixels having the same reference gradation change is equal to or greater than a certain ratio compared to the number of pixels included in the entire horizontal line.

The signal control unit 15 varies the high logic width of the source output enable signal SOE when the pattern analysis unit 13 detects a problem pattern image from the input image. That is, the signal controller 15 may adjust the charge share period by adjusting the high logic width of the source output enable signal SOE.

The afterimage improvement unit 10 may be implemented by being included in the timing controller 30 or other components.

The liquid crystal panel 20 has a liquid crystal layer formed between two glass substrates. The liquid crystal panel 20 includes m×n liquid crystal cells Clc arranged in a matrix form by an intersecting structure of m data lines 34 and n gate lines 35 .

Data lines DL, gate lines GL, TFTs, and a storage capacitor Cst are formed on the lower glass substrate of the liquid crystal panel 20 . The liquid crystal cells are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2 . A black matrix, a color filter, and a common electrode 2 are formed on the upper glass substrate of the liquid crystal panel 20 . On the other hand, the common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. It is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving mode. A polarizing plate is attached to the upper glass substrate and the lower glass substrate of the liquid crystal panel 20 , and an alignment film for setting a pre-tilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal.

The timing controller 30 receives timing signals such as vertical/horizontal synchronization signals Vsync and Hsync, a data enable signal DE, and a clock signal CLK, and receives the data driving circuit 50 , and the gate driving circuit 40 . ) to generate control signals for controlling the operation timing. These control signals include a gate timing control signal and a data timing control signal. Also, the timing controller 30 supplies digital video data to the data driving circuit 50 .

The gate timing control signal GDC generated by the timing controller 30 includes a gate start pulse GSP, a gate shift clock signal GSC, and a gate output enable signal GOE. do.

The data timing control signal generated by the timing controller 30 includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signals (Source Output Enable, SOE), and the like. The source start pulse SSP indicates a start pixel in a line on which data is to be displayed. The source sampling clock SSC instructs a latch operation of data in the data driving circuit 50 based on a rising or falling edge. The polarity control signal POL controls the polarity of the analog video data voltage output from the data driving circuit 50 . The source output enable signal SOE controls the data voltage output of the data driving circuit 50 .

As shown in FIG. 4 , the data driving circuit 50 includes a shift register 51 , a data register 52 , a latch unit 53 , a conversion unit 54 , an output unit 55 , and a charge share unit 57 . includes

The shift register 51 shifts the source sampling clock SSC supplied from the timing controller 30 . The shift register 51 transfers the carry signal CAR to the shift register of the source drive IC of the next adjacent stage. The data register 52 temporarily stores the digital data signal DATA supplied from the timing controller 30 and supplies it to the latch unit 53 . The latch unit 53 samples a digital data signal DATA serially input according to a clock sequentially supplied from the shift register 51 , and simultaneously outputs the latched data. The conversion unit 54 converts the digital data signal DDATA supplied from the latch unit 53 in response to the polarity control signal POL and the horizontal output inversion signal HINV into a positive gamma voltage or a negative gamma voltage. It is converted to analog data voltage. The output unit 55 includes a buffer that minimizes signal attenuation of the data voltage output to the data lines DL1 to DLn. The charge share unit 57 supplies the charge share voltage or the common voltage Vcom to the data lines DL1 to DLn during the charge share period according to the source output enable signal SOE.

The backlight unit 60 is for irradiating light to the liquid crystal panel 10 and may be classified into an edge type or a direct type.

5 is a view showing the charge share unit 57 .

Referring to FIG. 5 , the charge share unit 57 is connected to correspond to the output unit 55 . The charge share unit 57 includes the first switch units SW1 to SW1n and the data lines DL1 positioned between the output lines OL1 to OLn and the data lines DL1 to DLn of the output unit 55 . and a second switch unit SW2 to SW2n positioned between the DLn and DLn. The charge share unit 57 is a charge share voltage or a charge share during the charge share period CSP by the first switch units SW1 to SW1n and the second switch units SW2 to SW2n in response to the source output enable signal SOE. A common voltage Vcom is supplied to the data lines DL1 to DLn. That is, when the source output enable signal SOE is in the high logic section, the charge share unit 57 turns on the second switch units SW2 to SW2n to average the voltages between adjacent channels. Since the width of the high logic section of the source output enable signal SOE varies according to the selection of the afterimage improving unit 10 , the charge share unit 57 averages the voltage level in the process of averaging the voltages between adjacent channels. is different

6 is a flowchart illustrating a method of driving a liquid crystal display according to the present invention. Referring to FIG. 6 , the driving method of the liquid crystal display of the present invention is as follows.

< Pattern analysis of input image: S601 >

The line memory 11 stores the data of the input image in units of horizontal lines.

The pattern analysis unit 13 determines a problem pattern based on the data of the horizontal lines stored in the line memory 11 . The pattern analysis unit 13 regards the adjacent vertical pixels as pattern pixels when they belong to different reference grayscales, and determines that the pattern pixels are problematic patterns when the pattern pixels have a certain ratio or more among all horizontal pixels.

In order to determine whether there is a problem pattern, the pattern analysis unit 13 checks whether the data of each pixel stored in the line memory 11 belongs to the reference grayscale. The line memory 11 includes first to n-th memory areas A1 to An corresponding to the number of pixels arranged in a horizontal line, and each memory area A1 to An is each of the pixels arranged in a horizontal line. Store the data provided in For example, it is a view showing an example of the input image shown in Fig. 7, and Fig. 8 (a) is a schematic diagram of the line memory 11 in which data provided to each pixel arranged on the m-th horizontal line Hm is stored. , FIG. 8B is a schematic diagram of the line memory 11 in which data provided to each pixel arranged on the (m+1)th horizontal line [H(m+1)] is stored.

The pattern analysis unit 13 checks whether the data respectively stored in the first to nth memory areas A1 to An belong to the reference grayscale. As shown in (a) of FIG. 8 , if the data stored in the ith memory area Ai is '127' grayscale, the pattern analysis unit 13 determines that the data of the pixel in the ith column of the mth horizontal line Hm is It is judged to belong to the 'middle gradation'.

Next, in the schematic diagram of FIG. 8 (b) in which the data of the (m+1)th horizontal line [H(m+1)] pixels are stored, it is assumed that the data stored in the ith memory area Ai is '255' grayscale. Then, the pattern analysis unit 13 determines that the data of the pixel in the i-th column of the (m+1)-th horizontal line [H(m+1)] belongs to the 'high grayscale'.

< Check the problem pattern: S603 >

In addition, the pattern analysis unit 13 regards pixels having the same reference gradation of data stored in each memory area A1 to An of the line memory 11 as pattern pixels. That is, the pattern analysis unit 13 regards the pixel in the i-th column of the (m+1)-th horizontal line [H(m+1)] as the pattern pixel.

The pattern analyzer 13 calculates the number of pattern pixels, and determines whether the pattern pixels are equal to or greater than a certain ratio among pixels arranged in all horizontal lines. In addition, the pattern analysis unit 13 determines a special pattern when the number of pattern pixels is greater than or equal to a certain number in comparison to the total number of pixels arranged in a horizontal line. For example, in the case where the number of pattern pixels in the (m+1)th horizontal line in FIG. 5 is 'k', the pattern analysis unit 13 performs the (m+1)th horizontal line when the following [Equation 1] is satisfied. A line is regarded as a pattern pixel.

[Equation 1]

(k/n)×100 ≥ threshold (%)

< High logic width control of source output enable signal : S605 >

The signal controller 15 adjusts the output time of data provided to the horizontal line, which is a special pattern.

To this end, the signal controller 15 adjusts the charge share time by adjusting the high logic section of the source output enable signal SOE. The charge share time may vary according to changes in the reference grayscales.

The setting criteria for the charge share time will be described in detail with reference to FIGS. 9 to 12 . 9 to 12 , the low gray level voltage level is a voltage level for displaying a '0' gray level, a middle gray level voltage level is a voltage level for displaying a '127' gray level, and a high gray level is a '255' gray level. It will be defined as the voltage level for 9 to 11 show a section in which the data voltage is changed from the m-th horizontal line (Hm) to the (m+1)-th horizontal line [H(m+1)], in which case the charge share is the (m+)-th horizontal line. 1) Adjust the initial output voltage provided to the horizontal line [H(m+1)]. That is, in the description of FIGS. 9 to 11 , the initial output voltage means the initial output voltage of the (m+1)th horizontal line [H(m+1)], and the data voltage is the (m+1)th horizontal line [ H(m+1)] means the data voltage provided to it.

FIG. 9 is a diagram illustrating a change in a voltage charged in a pixel according to a charge share time when changing from a middle grayscale to a low grayscale.

Referring to FIG. 9 , the initial voltage of the (m+1)th horizontal line [H(m+1)] varies according to the charge share time, and the (m+1)th horizontal line [H(m+1)] The data voltage of '0' is a gradation voltage.

Without the charge share operation, since the initial voltage of the (m+1)th horizontal line [H(m+1)] is the half-gray voltage level (127 grayscales), the difference between the initial voltage and the data voltage is equal to the first change amount (Δ V0). And when the charge share operation is performed for as short as the first period T1, the initial voltage of the (m+1)th horizontal line H(m+1) becomes the voltage level of 'V1', and the initial voltage and the data voltage The difference between them becomes the second variation ΔV1. Also, when the charge share operation is performed for a long time about the second period T2, the initial voltage of the (m+1)th horizontal line becomes a voltage level 'V2' close to the common voltage level Vcom, and the initial voltage and the data voltage It becomes the third change amount (ΔV2) of the liver.

That is, in FIG. 9 , as the charge share period increases, the difference between the initial voltage and the data voltage decreases. Since the magnitude of the ripple is proportional to the difference between the initial voltage and the data voltage, the ripple decreases as the charge share period increases when the data between the horizontal lines changes from the middle gray level to the low gray level. Accordingly, the signal controller 15 lengthens the charge share period in order to reduce ripple when the data between the horizontal lines is changed from the middle gray level to the low gray level.

10 is a diagram illustrating a change in a voltage charged in a pixel according to a charge share time when a high gray level is changed to a middle gray level.

Referring to FIG. 10 , the initial voltage of the (m+1)th horizontal line [H(m+1)] varies according to the charge share time, and the (m+1)th horizontal line [H(m+1)] The data voltage of '127' is the gradation voltage.

If there is no charge share operation, since the initial voltage of the (m+1)th horizontal line [H(m+1)] is a high grayscale voltage level (255 grayscales), the difference between the initial voltage and the data voltage is equal to the first change amount (Δ V0). And when the charge share operation is performed for as short as the first period T1, the initial voltage of the (m+1)th horizontal line H(m+1) becomes the voltage level of 'V1', and the initial voltage and the data voltage The difference between them becomes the second variation ΔV1. Also, when the charge share operation is performed for a long time about the second period T2, the initial voltage of the (m+1)th horizontal line becomes a voltage level 'V2' close to the common voltage level Vcom, and the initial voltage and the data voltage It becomes the third change amount (ΔV2) of the liver.

That is, as the charge share period in FIG. 10 increases, the initial voltage decreases from the high gray level voltage level (255 gray levels) to the 'V2' voltage level close to the common voltage level Vcom via the middle gray level voltage level (127 gray levels). . Accordingly, when the charge share operation is performed in FIG. 10 , the amount of change between the initial voltage and the data voltage is reduced until the time t1 when the initial voltage reaches the half-gray voltage level. And if the charge share operation is continuously performed, the amount of change between the initial voltage and the data voltage increases again.

Accordingly, the signal control unit 15 sets the time t' at which the initial voltage reaches the half-gray voltage level (127 gray levels) as the charge share period. At this time, since the time point t' at which the initial voltage reaches the half-gray voltage level (127 gray levels) may vary according to panel characteristics, it may be set based on an experimental value.

11 is a diagram illustrating a change in a voltage charged in a pixel according to a charge share time when a grayscale is changed from a middle grayscale to a high grayscale.

Referring to FIG. 11 , the initial voltage of the (m+1)th horizontal line [H(m+1)] varies according to the charge share time, and the (m+1)th horizontal line [H(m+1)] The data voltage (255 gradations) of is a high gradation voltage.

Without the charge share operation, since the initial voltage of the (m+1)th horizontal line [H(m+1)] is the half-gray voltage level (127 grayscales), the difference between the initial voltage and the data voltage is equal to the first change amount (Δ V0). And when the charge share operation is performed for as short as the first period T1, the initial voltage of the (m+1)th horizontal line H(m+1) becomes the voltage level of 'V1', and the initial voltage and the data voltage The difference between them becomes the second variation ΔV1. Also, when the charge share operation is performed for a long time about the second period T2, the initial voltage of the (m+1)th horizontal line becomes a voltage level 'V2' close to the common voltage level Vcom, and the initial voltage and the data voltage It becomes the third change amount (ΔV2) of the liver.

That is, in FIG. 11 , as the charge share period increases, the difference between the initial voltage and the data voltage increases. Since the magnitude of the ripple is proportional to the difference between the initial voltage and the data voltage, the ripple increases as the charge share period increases when the data between horizontal lines changes from the middle grayscale to the high grayscale. Accordingly, the signal controller 15 reduces the charge share period in order to reduce ripple when the data between the horizontal lines changes from the middle gray level to the low gray level.

Also, as in the case of changing from the middle gray level to the high gray level, even in the pattern changing from the low gray level to the middle gray level, the signal controller 15 reduces the charge share period in order to reduce the horizontal line ripple.

The simulation results for the ripple change according to the charge share time in the form of each problem pattern are summarized as shown in FIG. 12 .

In FIG. 12 , the graph of ① is a graph showing the change in ripple according to the charge share time when the data voltage between horizontal lines is changed from the middle gray level to the low gray level. And the graph of ② is a graph showing the change of the ripple according to the charge share time when the data voltage between the horizontal lines changes from the high gray level to the middle gray level. In addition, the graphs of ③ and ④ are diagrams showing examples of ripple changes according to the charge share time when changing from a low gray level to a middle gray level and when changing from a middle gray level to a low gray level, respectively.

In the graph of FIG. 12 , the charge share time having the minimum ripple according to the change of the reference gray level may be stored in the form of a look-up table (not shown). In other words, the signal controller 15 may select from the look-up table a charge share period in which a ripple is caused to a minimum in each pattern. In this case, the specific time may be set in consideration of the panel characteristics or the charging time of the data voltage. For example, although FIG. 12 shows an example in which the ripple is minimal when the charge share period is 0.2 μs, the charge share period for inducing the minimum ripple when changing from a low grayscale to a middle grayscale may vary depending on the panel.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: afterimage improvement part 20: liquid crystal panel
30: timing controller 40: gate driving circuit
50: data driving circuit 60: backlight unit

Claims (13)

a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect;
a data driver configured to output a data voltage to the data lines during a low logic period of the source output enable signal and perform charge sharing by shorting adjacent data lines during a high logic period of the source output enable signal;
a timing controller transmitting input image data to the data driver and generating the source output enable signal defining an output timing of the data voltage and a timing of the charge share; and
Detects a problem pattern of a preset specific type from the input image, and when the problem pattern is detected, the high logic section of the source output enable signal is varied based on the grayscale change between the data of vertically adjacent horizontal lines Including an afterimage improvement unit that
The afterimage improvement part,
A liquid crystal display for controlling an initial output voltage provided to the horizontal lines by varying a high logic section of the source output enable signal.
The method of claim 1,
The afterimage improvement part
a line memory for storing the data of the input image for each horizontal line;
a pattern analysis unit that determines whether the input image is a problem pattern image based on data changes stored in each memory area of the line memory; and
and a signal control unit for adjusting a width of a high logic section of the source output enable signal when the problem pattern image is input.
3. The method of claim 2,
The pattern analysis unit
It is determined whether each pixel of the mth horizontal line and the (m+1)th horizontal line belongs to a reference grayscale selected within a range that can be displayed by the liquid crystal panel,
When the number of pixels having the same reference gradation in the m-th horizontal line and the (m+1)-th horizontal line is greater than a predetermined ratio compared to the total number of pixels in the horizontal line, the m-th horizontal line and the (m+)-th horizontal line 1) A liquid crystal display device, characterized in that the horizontal line is determined as a problem pattern.
4. The method of claim 3,
The reference gradation is
a gradation of '0' or a low gradation set to a range value including the gradation of '0';
a high gradation set to a maximum gradation or a range value including the maximum gradation; and
An average value of the low grayscale and the high grayscale, or an intermediate grayscale set as a range value including the average value.
5. The method of claim 4,
The signal control unit
The high logic section of the source output enable signal is increased when the data voltage of the mth horizontal line belongs to the half gray level and the data voltage of the (m+1)th horizontal line belongs to the low gray level. liquid crystal display device.
5. The method of claim 4,
The signal control unit
When the data voltage of the mth horizontal line belongs to the high grayscale and the data voltage of the (m+1)th horizontal line belongs to the half grayscale, the initial voltage of the (m+1)th horizontal line is the halftone voltage and a period for reaching the level is set as a high logic period of the source output enable signal.
5. The method of claim 4,
The signal control unit
When the reference grayscale of the data voltage of the (m+1)th horizontal line is higher than the reference grayscale of the data voltage of the mth horizontal line, the high logic section of the source output enable signal is reduced. liquid crystal display device.
A first step of storing the data of the input image in a line memory for each horizontal line;
a second step of determining whether the input image is a problem pattern image based on the amount of data change in each memory area of the line memory; and
a third step of adjusting the width of the high logic section of the source output enable signal when the problem pattern image is input;
The width of the high logic section of the source output enable signal is,
A driving method of a liquid crystal display controlled to control an initial output voltage provided to the horizontal lines.
9. The method of claim 8,
In the second step, it is determined whether the data stored in the memory area belongs to a reference grayscale, and it is determined whether the input image is the problem pattern based on a change in the reference grayscale between the adjacent horizontal lines. A method of driving a liquid crystal display device.
10. The method of claim 9,
The reference gradation is
a gradation of '0' or a low gradation set to a range value including the gradation of '0';
a high gradation set to a maximum gradation or a range value including the maximum gradation; and
An average value of the low grayscale and the high grayscale, or a middle grayscale set as a range value including the average value.
11. The method of claim 10,
The third step is
The high logic section of the source output enable signal is increased when the data voltage of the mth horizontal line belongs to the intermediate grayscale and the data voltage of the (m+1)th horizontal line belongs to the low grayscale. A method of driving a display device.
11. The method of claim 10,
The third step is
When the data voltage of the mth horizontal line belongs to the high grayscale and the data voltage of the (m+1)th horizontal line belongs to the half grayscale, the initial voltage of the (m+1)th horizontal line falls to the halftone voltage level. A driving method of a liquid crystal display device, characterized in that the arrival period is set as a high logic period of the source output enable signal.
11. The method of claim 10,
The third step is
Liquid crystal, characterized in that, when the reference grayscale of the data voltage of the (m+1)th horizontal line is higher than the reference grayscale of the data voltage of the mth horizontal line, the high logic section of the source output enable signal is reduced. A method of driving a display device.

Images